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Akshay Saraswatacbb1eb2013-03-20 21:00:56 +00001/*
2 * Header file for Advanced Crypto Engine - SFR definitions
3 *
4 * Copyright (c) 2012 Samsung Electronics
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Akshay Saraswatacbb1eb2013-03-20 21:00:56 +00007 */
8
9#ifndef __ACE_SHA_H
10#define __ACE_SHA_H
11
12struct exynos_ace_sfr {
13 unsigned int fc_intstat; /* base + 0 */
14 unsigned int fc_intenset;
15 unsigned int fc_intenclr;
16 unsigned int fc_intpend;
17 unsigned int fc_fifostat;
18 unsigned int fc_fifoctrl;
19 unsigned int fc_global;
20 unsigned int res1;
21 unsigned int fc_brdmas;
22 unsigned int fc_brdmal;
23 unsigned int fc_brdmac;
24 unsigned int res2;
25 unsigned int fc_btdmas;
26 unsigned int fc_btdmal;
27 unsigned int fc_btdmac;
28 unsigned int res3;
29 unsigned int fc_hrdmas;
30 unsigned int fc_hrdmal;
31 unsigned int fc_hrdmac;
32 unsigned int res4;
33 unsigned int fc_pkdmas;
34 unsigned int fc_pkdmal;
35 unsigned int fc_pkdmac;
36 unsigned int fc_pkdmao;
37 unsigned char res5[0x1a0];
38
39 unsigned int aes_control; /* base + 0x200 */
40 unsigned int aes_status;
41 unsigned char res6[0x8];
42 unsigned int aes_in[4];
43 unsigned int aes_out[4];
44 unsigned int aes_iv[4];
45 unsigned int aes_cnt[4];
46 unsigned char res7[0x30];
47 unsigned int aes_key[8];
48 unsigned char res8[0x60];
49
50 unsigned int tdes_control; /* base + 0x300 */
51 unsigned int tdes_status;
52 unsigned char res9[0x8];
53 unsigned int tdes_key[6];
54 unsigned int tdes_iv[2];
55 unsigned int tdes_in[2];
56 unsigned int tdes_out[2];
57 unsigned char res10[0xc0];
58
59 unsigned int hash_control; /* base + 0x400 */
60 unsigned int hash_control2;
61 unsigned int hash_fifo_mode;
62 unsigned int hash_byteswap;
63 unsigned int hash_status;
64 unsigned char res11[0xc];
65 unsigned int hash_msgsize_low;
66 unsigned int hash_msgsize_high;
67 unsigned int hash_prelen_low;
68 unsigned int hash_prelen_high;
69 unsigned int hash_in[16];
70 unsigned int hash_key_in[16];
71 unsigned int hash_iv[8];
72 unsigned char res12[0x30];
73 unsigned int hash_result[8];
74 unsigned char res13[0x20];
Przemyslaw Marczak0bd93722014-03-25 10:58:21 +010075 unsigned int hash_seed[5];
76 unsigned char res14[12];
77 unsigned int hash_prng[5];
78 unsigned char res15[0x18c];
Akshay Saraswatacbb1eb2013-03-20 21:00:56 +000079
80 unsigned int pka_sfr[5]; /* base + 0x700 */
81};
82
83/* ACE_FC_INT */
84#define ACE_FC_PKDMA (1 << 0)
85#define ACE_FC_HRDMA (1 << 1)
86#define ACE_FC_BTDMA (1 << 2)
87#define ACE_FC_BRDMA (1 << 3)
88#define ACE_FC_PRNG_ERROR (1 << 4)
89#define ACE_FC_MSG_DONE (1 << 5)
90#define ACE_FC_PRNG_DONE (1 << 6)
91#define ACE_FC_PARTIAL_DONE (1 << 7)
92
93/* ACE_FC_FIFOSTAT */
94#define ACE_FC_PKFIFO_EMPTY (1 << 0)
95#define ACE_FC_PKFIFO_FULL (1 << 1)
96#define ACE_FC_HRFIFO_EMPTY (1 << 2)
97#define ACE_FC_HRFIFO_FULL (1 << 3)
98#define ACE_FC_BTFIFO_EMPTY (1 << 4)
99#define ACE_FC_BTFIFO_FULL (1 << 5)
100#define ACE_FC_BRFIFO_EMPTY (1 << 6)
101#define ACE_FC_BRFIFO_FULL (1 << 7)
102
103/* ACE_FC_FIFOCTRL */
104#define ACE_FC_SELHASH_MASK (3 << 0)
105#define ACE_FC_SELHASH_EXOUT (0 << 0) /* independent source */
106#define ACE_FC_SELHASH_BCIN (1 << 0) /* blk cipher input */
107#define ACE_FC_SELHASH_BCOUT (2 << 0) /* blk cipher output */
108#define ACE_FC_SELBC_MASK (1 << 2)
109#define ACE_FC_SELBC_AES (0 << 2)
110#define ACE_FC_SELBC_DES (1 << 2)
111
112/* ACE_FC_GLOBAL */
113#define ACE_FC_SSS_RESET (1 << 0)
114#define ACE_FC_DMA_RESET (1 << 1)
115#define ACE_FC_AES_RESET (1 << 2)
116#define ACE_FC_DES_RESET (1 << 3)
117#define ACE_FC_HASH_RESET (1 << 4)
118#define ACE_FC_AXI_ENDIAN_MASK (3 << 6)
119#define ACE_FC_AXI_ENDIAN_LE (0 << 6)
120#define ACE_FC_AXI_ENDIAN_BIBE (1 << 6)
121#define ACE_FC_AXI_ENDIAN_WIBE (2 << 6)
122
123/* Feed control - BRDMA control */
124#define ACE_FC_BRDMACFLUSH_OFF (0 << 0)
125#define ACE_FC_BRDMACFLUSH_ON (1 << 0)
126#define ACE_FC_BRDMACSWAP_ON (1 << 1)
127#define ACE_FC_BRDMACARPROT_MASK (0x7 << 2)
128#define ACE_FC_BRDMACARPROT_OFS 2
129#define ACE_FC_BRDMACARCACHE_MASK (0xf << 5)
130#define ACE_FC_BRDMACARCACHE_OFS 5
131
132/* Feed control - BTDMA control */
133#define ACE_FC_BTDMACFLUSH_OFF (0 << 0)
134#define ACE_FC_BTDMACFLUSH_ON (1 << 0)
135#define ACE_FC_BTDMACSWAP_ON (1 << 1)
136#define ACE_FC_BTDMACAWPROT_MASK (0x7 << 2)
137#define ACE_FC_BTDMACAWPROT_OFS 2
138#define ACE_FC_BTDMACAWCACHE_MASK (0xf << 5)
139#define ACE_FC_BTDMACAWCACHE_OFS 5
140
141/* Feed control - HRDMA control */
142#define ACE_FC_HRDMACFLUSH_OFF (0 << 0)
143#define ACE_FC_HRDMACFLUSH_ON (1 << 0)
144#define ACE_FC_HRDMACSWAP_ON (1 << 1)
145#define ACE_FC_HRDMACARPROT_MASK (0x7 << 2)
146#define ACE_FC_HRDMACARPROT_OFS 2
147#define ACE_FC_HRDMACARCACHE_MASK (0xf << 5)
148#define ACE_FC_HRDMACARCACHE_OFS 5
149
150/* Feed control - PKDMA control */
151#define ACE_FC_PKDMACBYTESWAP_ON (1 << 3)
152#define ACE_FC_PKDMACDESEND_ON (1 << 2)
153#define ACE_FC_PKDMACTRANSMIT_ON (1 << 1)
154#define ACE_FC_PKDMACFLUSH_ON (1 << 0)
155
156/* Feed control - PKDMA offset */
157#define ACE_FC_SRAMOFFSET_MASK 0xfff
158
159/* AES control */
160#define ACE_AES_MODE_MASK (1 << 0)
161#define ACE_AES_MODE_ENC (0 << 0)
162#define ACE_AES_MODE_DEC (1 << 0)
163#define ACE_AES_OPERMODE_MASK (3 << 1)
164#define ACE_AES_OPERMODE_ECB (0 << 1)
165#define ACE_AES_OPERMODE_CBC (1 << 1)
166#define ACE_AES_OPERMODE_CTR (2 << 1)
167#define ACE_AES_FIFO_MASK (1 << 3)
168#define ACE_AES_FIFO_OFF (0 << 3) /* CPU mode */
169#define ACE_AES_FIFO_ON (1 << 3) /* FIFO mode */
170#define ACE_AES_KEYSIZE_MASK (3 << 4)
171#define ACE_AES_KEYSIZE_128 (0 << 4)
172#define ACE_AES_KEYSIZE_192 (1 << 4)
173#define ACE_AES_KEYSIZE_256 (2 << 4)
174#define ACE_AES_KEYCNGMODE_MASK (1 << 6)
175#define ACE_AES_KEYCNGMODE_OFF (0 << 6)
176#define ACE_AES_KEYCNGMODE_ON (1 << 6)
177#define ACE_AES_SWAP_MASK (0x1f << 7)
178#define ACE_AES_SWAPKEY_OFF (0 << 7)
179#define ACE_AES_SWAPKEY_ON (1 << 7)
180#define ACE_AES_SWAPCNT_OFF (0 << 8)
181#define ACE_AES_SWAPCNT_ON (1 << 8)
182#define ACE_AES_SWAPIV_OFF (0 << 9)
183#define ACE_AES_SWAPIV_ON (1 << 9)
184#define ACE_AES_SWAPDO_OFF (0 << 10)
185#define ACE_AES_SWAPDO_ON (1 << 10)
186#define ACE_AES_SWAPDI_OFF (0 << 11)
187#define ACE_AES_SWAPDI_ON (1 << 11)
188#define ACE_AES_COUNTERSIZE_MASK (3 << 12)
189#define ACE_AES_COUNTERSIZE_128 (0 << 12)
190#define ACE_AES_COUNTERSIZE_64 (1 << 12)
191#define ACE_AES_COUNTERSIZE_32 (2 << 12)
192#define ACE_AES_COUNTERSIZE_16 (3 << 12)
193
194/* AES status */
195#define ACE_AES_OUTRDY_MASK (1 << 0)
196#define ACE_AES_OUTRDY_OFF (0 << 0)
197#define ACE_AES_OUTRDY_ON (1 << 0)
198#define ACE_AES_INRDY_MASK (1 << 1)
199#define ACE_AES_INRDY_OFF (0 << 1)
200#define ACE_AES_INRDY_ON (1 << 1)
201#define ACE_AES_BUSY_MASK (1 << 2)
202#define ACE_AES_BUSY_OFF (0 << 2)
203#define ACE_AES_BUSY_ON (1 << 2)
204
205/* TDES control */
206#define ACE_TDES_MODE_MASK (1 << 0)
207#define ACE_TDES_MODE_ENC (0 << 0)
208#define ACE_TDES_MODE_DEC (1 << 0)
209#define ACE_TDES_OPERMODE_MASK (1 << 1)
210#define ACE_TDES_OPERMODE_ECB (0 << 1)
211#define ACE_TDES_OPERMODE_CBC (1 << 1)
212#define ACE_TDES_SEL_MASK (3 << 3)
213#define ACE_TDES_SEL_DES (0 << 3)
214#define ACE_TDES_SEL_TDESEDE (1 << 3) /* TDES EDE mode */
215#define ACE_TDES_SEL_TDESEEE (3 << 3) /* TDES EEE mode */
216#define ACE_TDES_FIFO_MASK (1 << 5)
217#define ACE_TDES_FIFO_OFF (0 << 5) /* CPU mode */
218#define ACE_TDES_FIFO_ON (1 << 5) /* FIFO mode */
219#define ACE_TDES_SWAP_MASK (0xf << 6)
220#define ACE_TDES_SWAPKEY_OFF (0 << 6)
221#define ACE_TDES_SWAPKEY_ON (1 << 6)
222#define ACE_TDES_SWAPIV_OFF (0 << 7)
223#define ACE_TDES_SWAPIV_ON (1 << 7)
224#define ACE_TDES_SWAPDO_OFF (0 << 8)
225#define ACE_TDES_SWAPDO_ON (1 << 8)
226#define ACE_TDES_SWAPDI_OFF (0 << 9)
227#define ACE_TDES_SWAPDI_ON (1 << 9)
228
229/* TDES status */
230#define ACE_TDES_OUTRDY_MASK (1 << 0)
231#define ACE_TDES_OUTRDY_OFF (0 << 0)
232#define ACE_TDES_OUTRDY_ON (1 << 0)
233#define ACE_TDES_INRDY_MASK (1 << 1)
234#define ACE_TDES_INRDY_OFF (0 << 1)
235#define ACE_TDES_INRDY_ON (1 << 1)
236#define ACE_TDES_BUSY_MASK (1 << 2)
237#define ACE_TDES_BUSY_OFF (0 << 2)
238#define ACE_TDES_BUSY_ON (1 << 2)
239
240/* Hash control */
241#define ACE_HASH_ENGSEL_MASK (0xf << 0)
242#define ACE_HASH_ENGSEL_SHA1HASH (0x0 << 0)
243#define ACE_HASH_ENGSEL_SHA1HMAC (0x1 << 0)
244#define ACE_HASH_ENGSEL_SHA1HMACIN (0x1 << 0)
245#define ACE_HASH_ENGSEL_SHA1HMACOUT (0x9 << 0)
246#define ACE_HASH_ENGSEL_MD5HASH (0x2 << 0)
247#define ACE_HASH_ENGSEL_MD5HMAC (0x3 << 0)
248#define ACE_HASH_ENGSEL_MD5HMACIN (0x3 << 0)
249#define ACE_HASH_ENGSEL_MD5HMACOUT (0xb << 0)
250#define ACE_HASH_ENGSEL_SHA256HASH (0x4 << 0)
251#define ACE_HASH_ENGSEL_SHA256HMAC (0x5 << 0)
252#define ACE_HASH_ENGSEL_PRNG (0x8 << 0)
253#define ACE_HASH_STARTBIT_ON (1 << 4)
254#define ACE_HASH_USERIV_EN (1 << 5)
255#define ACE_HASH_PAUSE_ON (1 << 0)
256
257/* Hash control - FIFO mode */
258#define ACE_HASH_FIFO_MASK (1 << 0)
259#define ACE_HASH_FIFO_OFF (0 << 0)
260#define ACE_HASH_FIFO_ON (1 << 0)
261
262/* Hash control - byte swap */
263#define ACE_HASH_SWAP_MASK (0xf << 0)
264#define ACE_HASH_SWAPKEY_OFF (0 << 0)
265#define ACE_HASH_SWAPKEY_ON (1 << 0)
266#define ACE_HASH_SWAPIV_OFF (0 << 1)
267#define ACE_HASH_SWAPIV_ON (1 << 1)
268#define ACE_HASH_SWAPDO_OFF (0 << 2)
269#define ACE_HASH_SWAPDO_ON (1 << 2)
270#define ACE_HASH_SWAPDI_OFF (0 << 3)
271#define ACE_HASH_SWAPDI_ON (1 << 3)
272
273/* Hash status */
274#define ACE_HASH_BUFRDY_MASK (1 << 0)
275#define ACE_HASH_BUFRDY_OFF (0 << 0)
276#define ACE_HASH_BUFRDY_ON (1 << 0)
277#define ACE_HASH_SEEDSETTING_MASK (1 << 1)
278#define ACE_HASH_SEEDSETTING_OFF (0 << 1)
279#define ACE_HASH_SEEDSETTING_ON (1 << 1)
280#define ACE_HASH_PRNGBUSY_MASK (1 << 2)
281#define ACE_HASH_PRNGBUSY_OFF (0 << 2)
282#define ACE_HASH_PRNGBUSY_ON (1 << 2)
283#define ACE_HASH_PARTIALDONE_MASK (1 << 4)
284#define ACE_HASH_PARTIALDONE_OFF (0 << 4)
285#define ACE_HASH_PARTIALDONE_ON (1 << 4)
286#define ACE_HASH_PRNGDONE_MASK (1 << 5)
287#define ACE_HASH_PRNGDONE_OFF (0 << 5)
288#define ACE_HASH_PRNGDONE_ON (1 << 5)
289#define ACE_HASH_MSGDONE_MASK (1 << 6)
290#define ACE_HASH_MSGDONE_OFF (0 << 6)
291#define ACE_HASH_MSGDONE_ON (1 << 6)
292#define ACE_HASH_PRNGERROR_MASK (1 << 7)
293#define ACE_HASH_PRNGERROR_OFF (0 << 7)
294#define ACE_HASH_PRNGERROR_ON (1 << 7)
Przemyslaw Marczak0bd93722014-03-25 10:58:21 +0100295#define ACE_HASH_PRNG_REG_NUM 5
Akshay Saraswatacbb1eb2013-03-20 21:00:56 +0000296
297#define ACE_SHA_TYPE_SHA1 1
298#define ACE_SHA_TYPE_SHA256 2
299
300/**
301 * Computes hash value of input pbuf using ACE
302 *
303 * @param in_addr A pointer to the input buffer
304 * @param bufleni Byte length of input buffer
305 * @param out_addr A pointer to the output buffer. When complete
306 * 32 bytes are copied to pout[0]...pout[31]. Thus, a user
307 * should allocate at least 32 bytes at pOut in advance.
308 * @param hash_type SHA1 or SHA256
309 *
310 * @return 0 on Success, -1 on Failure (Timeout)
311 */
312int ace_sha_hash_digest(const uchar * in_addr, uint buflen,
313 uchar * out_addr, uint hash_type);
314#endif