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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * Cirrus Logic CS8900A Ethernet
3 *
Ben Warrenb1c0eaa2009-08-25 13:09:37 -07004 * (C) 2009 Ben Warren , biggerbadderben@gmail.com
5 * Converted to use CONFIG_NET_MULTI API
6 *
wdenk6069ff22003-02-28 00:49:47 +00007 * (C) 2003 Wolfgang Denk, wd@denx.de
8 * Extension to synchronize ethaddr environment variable
9 * against value in EEPROM
10 *
wdenkc6097192002-11-03 00:24:07 +000011 * (C) Copyright 2002
12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13 * Marius Groeger <mgroeger@sysgo.de>
14 *
15 * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is loaded into SRAM in bootstrap mode, where it waits
21 * for commands on UART1 to read and write memory, jump to code etc.
22 * A design goal for this program is to be entirely independent of the
23 * target board. Anything with a CL-PS7111 or EP7211 should be able to run
24 * this code in bootstrap mode. All the board specifics can be handled on
25 * the host.
26 *
27 * This program is free software; you can redistribute it and/or modify
28 * it under the terms of the GNU General Public License as published by
29 * the Free Software Foundation; either version 2 of the License, or
30 * (at your option) any later version.
31 *
32 * This program is distributed in the hope that it will be useful,
33 * but WITHOUT ANY WARRANTY; without even the implied warranty of
34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 * GNU General Public License for more details.
36 *
37 * You should have received a copy of the GNU General Public License
38 * along with this program; if not, write to the Free Software
39 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
40 */
41
42#include <common.h>
43#include <command.h>
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070044#include <asm/io.h>
wdenkc6097192002-11-03 00:24:07 +000045#include <net.h>
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070046#include <malloc.h>
47#include "cs8900.h"
wdenkc6097192002-11-03 00:24:07 +000048
wdenka2663ea2003-12-07 18:32:37 +000049#undef DEBUG
wdenkc6097192002-11-03 00:24:07 +000050
51/* packet page register access functions */
52
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070053#ifdef CONFIG_CS8900_BUS32
54
55#define REG_WRITE(v, a) writel((v),(a))
56#define REG_READ(a) readl((a))
57
wdenkc6097192002-11-03 00:24:07 +000058/* we don't need 16 bit initialisation on 32 bit bus */
59#define get_reg_init_bus(x) get_reg((x))
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070060
wdenkc6097192002-11-03 00:24:07 +000061#else
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070062
63#define REG_WRITE(v, a) writew((v),(a))
64#define REG_READ(a) readw((a))
65
66static u16 get_reg_init_bus(struct eth_device *dev, int regno)
wdenkc6097192002-11-03 00:24:07 +000067{
wdenk6069ff22003-02-28 00:49:47 +000068 /* force 16 bit busmode */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070069 volatile u8 c;
70 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
71 uint8_t volatile * const iob = (uint8_t volatile * const)dev->iobase;
wdenkc6097192002-11-03 00:24:07 +000072
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070073 c = readb(iob);
74 c = readb(iob + 1);
75 c = readb(iob);
76 c = readb(iob + 1);
77 c = readb(iob);
wdenk6069ff22003-02-28 00:49:47 +000078
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070079 REG_WRITE(regno, &priv->regs->pptr);
80 return REG_READ(&priv->regs->pdata);
wdenkc6097192002-11-03 00:24:07 +000081}
82#endif
83
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070084static u16 get_reg(struct eth_device *dev, int regno)
wdenkc6097192002-11-03 00:24:07 +000085{
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070086 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
87 REG_WRITE(regno, &priv->regs->pptr);
88 return REG_READ(&priv->regs->pdata);
wdenkc6097192002-11-03 00:24:07 +000089}
90
91
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070092static void put_reg(struct eth_device *dev, int regno, u16 val)
wdenkc6097192002-11-03 00:24:07 +000093{
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070094 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
95 REG_WRITE(regno, &priv->regs->pptr);
96 REG_WRITE(val, &priv->regs->pdata);
wdenkc6097192002-11-03 00:24:07 +000097}
98
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070099static void cs8900_reset(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000100{
wdenk6069ff22003-02-28 00:49:47 +0000101 int tmo;
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700102 u16 us;
wdenkc6097192002-11-03 00:24:07 +0000103
wdenk6069ff22003-02-28 00:49:47 +0000104 /* reset NIC */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700105 put_reg(dev, PP_SelfCTL, get_reg(dev, PP_SelfCTL) | PP_SelfCTL_Reset);
wdenkc6097192002-11-03 00:24:07 +0000106
wdenk6069ff22003-02-28 00:49:47 +0000107 /* wait for 200ms */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700108 udelay(200000);
wdenk6069ff22003-02-28 00:49:47 +0000109 /* Wait until the chip is reset */
wdenkc6097192002-11-03 00:24:07 +0000110
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700111 tmo = get_timer(0) + 1 * CONFIG_SYS_HZ;
112 while ((((us = get_reg_init_bus(dev, PP_SelfSTAT)) &
113 PP_SelfSTAT_InitD) == 0) && tmo < get_timer(0))
wdenk6069ff22003-02-28 00:49:47 +0000114 /*NOP*/;
wdenkc6097192002-11-03 00:24:07 +0000115}
116
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700117static void cs8900_reginit(struct eth_device *dev)
wdenka2663ea2003-12-07 18:32:37 +0000118{
119 /* receive only error free packets addressed to this card */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700120 put_reg(dev, PP_RxCTL,
121 PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
wdenka2663ea2003-12-07 18:32:37 +0000122 /* do not generate any interrupts on receive operations */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700123 put_reg(dev, PP_RxCFG, 0);
wdenka2663ea2003-12-07 18:32:37 +0000124 /* do not generate any interrupts on transmit operations */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700125 put_reg(dev, PP_TxCFG, 0);
wdenka2663ea2003-12-07 18:32:37 +0000126 /* do not generate any interrupts on buffer operations */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700127 put_reg(dev, PP_BufCFG, 0);
wdenka2663ea2003-12-07 18:32:37 +0000128 /* enable transmitter/receiver mode */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700129 put_reg(dev, PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
wdenka2663ea2003-12-07 18:32:37 +0000130}
131
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700132void cs8900_get_enetaddr(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000133{
wdenk6069ff22003-02-28 00:49:47 +0000134 int i;
wdenk6069ff22003-02-28 00:49:47 +0000135
136 /* verify chip id */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700137 if (get_reg_init_bus(dev, PP_ChipID) != 0x630e)
wdenk6069ff22003-02-28 00:49:47 +0000138 return;
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700139 cs8900_reset(dev);
140 if ((get_reg(dev, PP_SelfSTAT) &
141 (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
142 (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {
wdenk6069ff22003-02-28 00:49:47 +0000143
144 /* Load the MAC from EEPROM */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700145 for (i = 0; i < 3; i++) {
146 u32 Addr;
wdenk6069ff22003-02-28 00:49:47 +0000147
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700148 Addr = get_reg(dev, PP_IA + i * 2);
149 dev->enetaddr[i * 2] = Addr & 0xFF;
150 dev->enetaddr[i * 2 + 1] = Addr >> 8;
wdenk6069ff22003-02-28 00:49:47 +0000151 }
wdenk6069ff22003-02-28 00:49:47 +0000152 }
wdenkc6097192002-11-03 00:24:07 +0000153}
154
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700155void cs8900_halt(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000156{
wdenk6069ff22003-02-28 00:49:47 +0000157 /* disable transmitter/receiver mode */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700158 put_reg(dev, PP_LineCTL, 0);
wdenkc6097192002-11-03 00:24:07 +0000159
wdenk6069ff22003-02-28 00:49:47 +0000160 /* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700161 get_reg_init_bus(dev, PP_ChipID);
wdenkc6097192002-11-03 00:24:07 +0000162}
163
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700164static int cs8900_init(struct eth_device *dev, bd_t * bd)
wdenkc6097192002-11-03 00:24:07 +0000165{
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700166 uchar *enetaddr = dev->enetaddr;
167 u16 id;
Mike Frysinger0a5238c2009-02-11 19:06:09 -0500168
wdenk6069ff22003-02-28 00:49:47 +0000169 /* verify chip id */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700170 id = get_reg_init_bus(dev, PP_ChipID);
171 if (id != 0x630e) {
172 printf ("CS8900 Ethernet chip not found: "
173 "ID=0x%04x instead 0x%04x\n", id, 0x630e);
174 return 1;
wdenk6069ff22003-02-28 00:49:47 +0000175 }
176
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700177 cs8900_reset (dev);
wdenk6069ff22003-02-28 00:49:47 +0000178 /* set the ethernet address */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700179 put_reg(dev, PP_IA + 0, enetaddr[0] | (enetaddr[1] << 8));
180 put_reg(dev, PP_IA + 2, enetaddr[2] | (enetaddr[3] << 8));
181 put_reg(dev, PP_IA + 4, enetaddr[4] | (enetaddr[5] << 8));
wdenk6069ff22003-02-28 00:49:47 +0000182
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700183 cs8900_reginit(dev);
wdenkc6097192002-11-03 00:24:07 +0000184 return 0;
wdenkc6097192002-11-03 00:24:07 +0000185}
186
187/* Get a data block via Ethernet */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700188static int cs8900_recv(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000189{
wdenk6069ff22003-02-28 00:49:47 +0000190 int i;
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700191 u16 rxlen;
192 u16 *addr;
193 u16 status;
wdenkc6097192002-11-03 00:24:07 +0000194
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700195 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
196
197 status = get_reg(dev, PP_RER);
wdenkc6097192002-11-03 00:24:07 +0000198
wdenk6069ff22003-02-28 00:49:47 +0000199 if ((status & PP_RER_RxOK) == 0)
200 return 0;
wdenkc6097192002-11-03 00:24:07 +0000201
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700202 status = REG_READ(&priv->regs->rtdata);
203 rxlen = REG_READ(&priv->regs->rtdata);
wdenkc6097192002-11-03 00:24:07 +0000204
wdenk6069ff22003-02-28 00:49:47 +0000205 if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700206 debug("packet too big!\n");
207 for (addr = (u16 *) NetRxPackets[0], i = rxlen >> 1; i > 0;
wdenk6069ff22003-02-28 00:49:47 +0000208 i--)
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700209 *addr++ = REG_READ(&priv->regs->rtdata);
wdenk6069ff22003-02-28 00:49:47 +0000210 if (rxlen & 1)
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700211 *addr++ = REG_READ(&priv->regs->rtdata);
wdenkc6097192002-11-03 00:24:07 +0000212
wdenk6069ff22003-02-28 00:49:47 +0000213 /* Pass the packet up to the protocol layers. */
214 NetReceive (NetRxPackets[0], rxlen);
wdenk6069ff22003-02-28 00:49:47 +0000215 return rxlen;
wdenkc6097192002-11-03 00:24:07 +0000216}
217
218/* Send a data block via Ethernet. */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700219static int cs8900_send(struct eth_device *dev,
220 volatile void *packet, int length)
wdenkc6097192002-11-03 00:24:07 +0000221{
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700222 volatile u16 *addr;
wdenk6069ff22003-02-28 00:49:47 +0000223 int tmo;
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700224 u16 s;
225 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
wdenkc6097192002-11-03 00:24:07 +0000226
227retry:
wdenk6069ff22003-02-28 00:49:47 +0000228 /* initiate a transmit sequence */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700229 REG_WRITE(PP_TxCmd_TxStart_Full, &priv->regs->txcmd);
230 REG_WRITE(length, &priv->regs->txlen);
wdenkc6097192002-11-03 00:24:07 +0000231
wdenk6069ff22003-02-28 00:49:47 +0000232 /* Test to see if the chip has allocated memory for the packet */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700233 if ((get_reg(dev, PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
wdenk6069ff22003-02-28 00:49:47 +0000234 /* Oops... this should not happen! */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700235 debug("cs: unable to send packet; retrying...\n");
236 for (tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
237 get_timer(0) < tmo;)
wdenk6069ff22003-02-28 00:49:47 +0000238 /*NOP*/;
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700239 cs8900_reset(dev);
240 cs8900_reginit(dev);
wdenk6069ff22003-02-28 00:49:47 +0000241 goto retry;
242 }
wdenkc6097192002-11-03 00:24:07 +0000243
wdenk6069ff22003-02-28 00:49:47 +0000244 /* Write the contents of the packet */
245 /* assume even number of bytes */
246 for (addr = packet; length > 0; length -= 2)
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700247 REG_WRITE(*addr++, &priv->regs->rtdata);
wdenkc6097192002-11-03 00:24:07 +0000248
wdenk6069ff22003-02-28 00:49:47 +0000249 /* wait for transfer to succeed */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700250 tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
251 while ((s = get_reg(dev, PP_TER) & ~0x1F) == 0) {
252 if (get_timer(0) >= tmo)
wdenk6069ff22003-02-28 00:49:47 +0000253 break;
254 }
wdenkc6097192002-11-03 00:24:07 +0000255
wdenk6069ff22003-02-28 00:49:47 +0000256 /* nothing */ ;
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700257 if((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) {
258 debug("\ntransmission error %#x\n", s);
wdenk6069ff22003-02-28 00:49:47 +0000259 }
wdenkc6097192002-11-03 00:24:07 +0000260
wdenk6069ff22003-02-28 00:49:47 +0000261 return 0;
wdenkc6097192002-11-03 00:24:07 +0000262}
263
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700264static void cs8900_e2prom_ready(struct eth_device *dev)
wdenk1cb8e982003-03-06 21:55:29 +0000265{
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700266 while (get_reg(dev, PP_SelfSTAT) & SI_BUSY)
Guennadi Liakhovetski13e0b8f2008-04-03 13:36:18 +0200267 ;
wdenk1cb8e982003-03-06 21:55:29 +0000268}
269
270/***********************************************************/
271/* read a 16-bit word out of the EEPROM */
272/***********************************************************/
273
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700274int cs8900_e2prom_read(struct eth_device *dev,
275 u8 addr, u16 *value)
wdenk1cb8e982003-03-06 21:55:29 +0000276{
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700277 cs8900_e2prom_ready(dev);
278 put_reg(dev, PP_EECMD, EEPROM_READ_CMD | addr);
279 cs8900_e2prom_ready(dev);
280 *value = get_reg(dev, PP_EEData);
wdenk1cb8e982003-03-06 21:55:29 +0000281
282 return 0;
283}
284
285
286/***********************************************************/
287/* write a 16-bit word into the EEPROM */
288/***********************************************************/
289
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700290int cs8900_e2prom_write(struct eth_device *dev, u8 addr, u16 value)
wdenk1cb8e982003-03-06 21:55:29 +0000291{
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700292 cs8900_e2prom_ready(dev);
293 put_reg(dev, PP_EECMD, EEPROM_WRITE_EN);
294 cs8900_e2prom_ready(dev);
295 put_reg(dev, PP_EEData, value);
296 put_reg(dev, PP_EECMD, EEPROM_WRITE_CMD | addr);
297 cs8900_e2prom_ready(dev);
298 put_reg(dev, PP_EECMD, EEPROM_WRITE_DIS);
299 cs8900_e2prom_ready(dev);
wdenk1cb8e982003-03-06 21:55:29 +0000300
wdenk06d01db2003-03-14 20:47:52 +0000301 return 0;
wdenk1cb8e982003-03-06 21:55:29 +0000302}
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700303
304int cs8900_initialize(u8 dev_num, int base_addr)
305{
306 struct eth_device *dev;
307 struct cs8900_priv *priv;
308
309 dev = malloc(sizeof(*dev));
310 if (!dev) {
311 free(dev);
312 return 0;
313 }
314 memset(dev, 0, sizeof(*dev));
315
316 priv = malloc(sizeof(*priv));
317 if (!priv) {
318 free(priv);
319 return 0;
320 }
321 memset(priv, 0, sizeof(*priv));
322 priv->regs = (struct cs8900_regs *)base_addr;
323
324 /* Load MAC address from EEPROM */
325 cs8900_get_enetaddr(dev);
326
327 dev->iobase = base_addr;
328 dev->priv = priv;
329 dev->init = cs8900_init;
330 dev->halt = cs8900_halt;
331 dev->send = cs8900_send;
332 dev->recv = cs8900_recv;
333 sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);
334
335 eth_register(dev);
336 return 0;
337}