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TsiChungLiewe2756f42008-01-14 17:47:23 -06001/*
2 * MCF5227x Internal Memory Map
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __MCF5227X__
27#define __MCF5227X__
28
TsiChung Liew012522f2008-10-21 10:03:07 +000029/* Interrupt Controller (INTC) */
TsiChungLiewe2756f42008-01-14 17:47:23 -060030#define INT0_LO_RSVD0 (0)
31#define INT0_LO_EPORT1 (1)
32#define INT0_LO_EPORT4 (4)
33#define INT0_LO_EPORT7 (7)
34#define INT0_LO_EDMA_00 (8)
35#define INT0_LO_EDMA_01 (9)
36#define INT0_LO_EDMA_02 (10)
37#define INT0_LO_EDMA_03 (11)
38#define INT0_LO_EDMA_04 (12)
39#define INT0_LO_EDMA_05 (13)
40#define INT0_LO_EDMA_06 (14)
41#define INT0_LO_EDMA_07 (15)
42#define INT0_LO_EDMA_08 (16)
43#define INT0_LO_EDMA_09 (17)
44#define INT0_LO_EDMA_10 (18)
45#define INT0_LO_EDMA_11 (19)
46#define INT0_LO_EDMA_12 (20)
47#define INT0_LO_EDMA_13 (21)
48#define INT0_LO_EDMA_14 (22)
49#define INT0_LO_EDMA_15 (23)
50#define INT0_LO_EDMA_ERR (24)
51#define INT0_LO_SCM_CWIC (25)
52#define INT0_LO_UART0 (26)
53#define INT0_LO_UART1 (27)
54#define INT0_LO_UART2 (28)
55#define INT0_LO_I2C (30)
56#define INT0_LO_DSPI (31)
57#define INT0_HI_DTMR0 (32)
58#define INT0_HI_DTMR1 (33)
59#define INT0_HI_DTMR2 (34)
60#define INT0_HI_DTMR3 (35)
61#define INT0_HI_SCMIR (62)
62#define INT0_HI_RTC_ISR (63)
63
64#define INT1_HI_CAN_BOFFINT (1)
65#define INT1_HI_CAN_ERRINT (3)
66#define INT1_HI_CAN_BUF0I (4)
67#define INT1_HI_CAN_BUF1I (5)
68#define INT1_HI_CAN_BUF2I (6)
69#define INT1_HI_CAN_BUF3I (7)
70#define INT1_HI_CAN_BUF4I (8)
71#define INT1_HI_CAN_BUF5I (9)
72#define INT1_HI_CAN_BUF6I (10)
73#define INT1_HI_CAN_BUF7I (11)
74#define INT1_HI_CAN_BUF8I (12)
75#define INT1_HI_CAN_BUF9I (13)
76#define INT1_HI_CAN_BUF10I (14)
77#define INT1_HI_CAN_BUF11I (15)
78#define INT1_HI_CAN_BUF12I (16)
79#define INT1_HI_CAN_BUF13I (17)
80#define INT1_HI_CAN_BUF14I (18)
81#define INT1_HI_CAN_BUF15I (19)
82#define INT1_HI_PIT0_PIF (43)
83#define INT1_HI_PIT1_PIF (44)
84#define INT1_HI_USBOTG_STS (47)
85#define INT1_HI_SSI_ISR (49)
86#define INT1_HI_PWM_INT (50)
87#define INT1_HI_LCDC_ISR (51)
88#define INT1_HI_CCM_UOCSR (53)
89#define INT1_HI_DSPI_EOQF (54)
90#define INT1_HI_DSPI_TFFF (55)
91#define INT1_HI_DSPI_TCF (56)
92#define INT1_HI_DSPI_TFUF (57)
93#define INT1_HI_DSPI_RFDF (58)
94#define INT1_HI_DSPI_RFOF (59)
95#define INT1_HI_DSPI_RFOF_TFUF (60)
96#define INT1_HI_TOUCH_ADC (61)
97#define INT1_HI_PLL_LOCKS (62)
98
TsiChungLiewe2756f42008-01-14 17:47:23 -060099/*********************************************************************
100* Reset Controller Module (RCM)
101*********************************************************************/
102
103/* Bit definitions and macros for RCR */
104#define RCM_RCR_FRCRSTOUT (0x40)
105#define RCM_RCR_SOFTRST (0x80)
106
107/* Bit definitions and macros for RSR */
108#define RCM_RSR_LOL (0x01)
109#define RCM_RSR_WDR_CORE (0x02)
110#define RCM_RSR_EXT (0x04)
111#define RCM_RSR_POR (0x08)
112#define RCM_RSR_SOFT (0x20)
113
114/*********************************************************************
115* Chip Configuration Module (CCM)
116*********************************************************************/
117
118/* Bit definitions and macros for CCR */
119#define CCM_CCR_DRAMSEL (0x0100)
120#define CCM_CCR_CSC_MASK (0xFF3F)
121#define CCM_CCR_CSC_FBCS5_CS4 (0x00C0)
122#define CCM_CCR_CSC_FBCS5_A22 (0x0080)
123#define CCM_CCR_CSC_FB_A23_A22 (0x0040)
124#define CCM_CCR_LIMP (0x0020)
125#define CCM_CCR_LOAD (0x0010)
126#define CCM_CCR_BOOTPS_MASK (0xFFF3)
127#define CCM_CCR_BOOTPS_PS16 (0x0008)
128#define CCM_CCR_BOOTPS_PS8 (0x0004)
129#define CCM_CCR_BOOTPS_PS32 (0x0000)
130#define CCM_CCR_OSCMODE_OSCBYPASS (0x0002)
131
132/* Bit definitions and macros for RCON */
133#define CCM_RCON_CSC_MASK (0xFF3F)
134#define CCM_RCON_CSC_FBCS5_CS4 (0x00C0)
135#define CCM_RCON_CSC_FBCS5_A22 (0x0080)
136#define CCM_RCON_CSC_FB_A23_A22 (0x0040)
137#define CCM_RCON_LIMP (0x0020)
138#define CCM_RCON_LOAD (0x0010)
139#define CCM_RCON_BOOTPS_MASK (0xFFF3)
140#define CCM_RCON_BOOTPS_PS16 (0x0008)
141#define CCM_RCON_BOOTPS_PS8 (0x0004)
142#define CCM_RCON_BOOTPS_PS32 (0x0000)
143#define CCM_RCON_OSCMODE_OSCBYPASS (0x0002)
144
145/* Bit definitions and macros for CIR */
146#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */
147#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */
148#define CCM_CIR_PIN_MASK (0xFFC0)
149#define CCM_CIR_PRN_MASK (0x003F)
150#define CCM_CIR_PIN_MCF52277 (0x0000)
151
152/* Bit definitions and macros for MISCCR */
153#define CCM_MISCCR_RTCSRC (0x4000)
154#define CCM_MISCCR_USBPUE (0x2000) /* USB transceiver pull-up */
155#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
156
157#define CCM_MISCCR_BME (0x0800) /* Bus monitor ext en bit */
158#define CCM_MISCCR_BMT_65536 (0)
159#define CCM_MISCCR_BMT_32768 (1)
160#define CCM_MISCCR_BMT_16384 (2)
161#define CCM_MISCCR_BMT_8192 (3)
162#define CCM_MISCCR_BMT_4096 (4)
163#define CCM_MISCCR_BMT_2048 (5)
164#define CCM_MISCCR_BMT_1024 (6)
165#define CCM_MISCCR_BMT_512 (7)
166
167#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
168#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
169#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
170#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
171#define CCM_MISCCR_LCDCHEN (0x0004) /* LCD Int CLK en */
172#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense pol */
173#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
174
175/* Bit definitions and macros for CDR */
176#define CCM_CDR_USBDIV(x) (((x)&0x0003)<<12)
177#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clk div */
178#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clk div */
179
180/* Bit definitions and macros for UOCSR */
181#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (rd-only) */
182#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (rd-only) */
183#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (rd-only) */
184#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor en (rd-only) */
185#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (rd-only) */
186#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
187#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
188#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
189#define CCM_UOCSR_SEND (0x0010) /* Session end */
190#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
191#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt en */
192#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down en */
193
194/*********************************************************************
195* General Purpose I/O Module (GPIO)
196*********************************************************************/
197/* Bit definitions and macros for PAR_BE */
198#define GPIO_PAR_BE_MASK (0x0F)
199#define GPIO_PAR_BE_BE3_BE3 (0x08)
200#define GPIO_PAR_BE_BE3_GPIO (0x00)
201#define GPIO_PAR_BE_BE2_BE2 (0x04)
202#define GPIO_PAR_BE_BE2_GPIO (0x00)
203#define GPIO_PAR_BE_BE1_BE1 (0x02)
204#define GPIO_PAR_BE_BE1_GPIO (0x00)
205#define GPIO_PAR_BE_BE0_BE0 (0x01)
206#define GPIO_PAR_BE_BE0_GPIO (0x00)
207
208/* Bit definitions and macros for PAR_CS */
209#define GPIO_PAR_CS_CS3 (0x10)
210#define GPIO_PAR_CS_CS2 (0x08)
211#define GPIO_PAR_CS_CS1_FBCS1 (0x06)
212#define GPIO_PAR_CS_CS1_SDCS1 (0x04)
213#define GPIO_PAR_CS_CS1_GPIO (0x00)
214#define GPIO_PAR_CS_CS0 (0x01)
215
216/* Bit definitions and macros for PAR_FBCTL */
217#define GPIO_PAR_FBCTL_OE (0x80)
218#define GPIO_PAR_FBCTL_TA (0x40)
219#define GPIO_PAR_FBCTL_RW (0x20)
220#define GPIO_PAR_FBCTL_TS_MASK (0xE7)
221#define GPIO_PAR_FBCTL_TS_FBTS (0x18)
222#define GPIO_PAR_FBCTL_TS_DMAACK (0x10)
223#define GPIO_PAR_FBCTL_TS_GPIO (0x00)
224
225/* Bit definitions and macros for PAR_FECI2C */
226#define GPIO_PAR_I2C_SCL_MASK (0xF3)
227#define GPIO_PAR_I2C_SCL_SCL (0x0C)
228#define GPIO_PAR_I2C_SCL_CANTXD (0x08)
229#define GPIO_PAR_I2C_SCL_U2TXD (0x04)
230#define GPIO_PAR_I2C_SCL_GPIO (0x00)
231
232#define GPIO_PAR_I2C_SDA_MASK (0xFC)
233#define GPIO_PAR_I2C_SDA_SDA (0x03)
234#define GPIO_PAR_I2C_SDA_CANRXD (0x02)
235#define GPIO_PAR_I2C_SDA_U2RXD (0x01)
236#define GPIO_PAR_I2C_SDA_GPIO (0x00)
237
238/* Bit definitions and macros for PAR_UART */
239#define GPIO_PAR_UART_U1CTS_MASK (0x3FFF)
240#define GPIO_PAR_UART_U1CTS_U1CTS (0xC000)
241#define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000)
242#define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000)
243#define GPIO_PAR_UART_U1CTS_GPIO (0x0000)
244
245#define GPIO_PAR_UART_U1RTS_MASK (0xCFFF)
246#define GPIO_PAR_UART_U1RTS_U1RTS (0x3000)
247#define GPIO_PAR_UART_U1RTS_SSIFS (0x2000)
248#define GPIO_PAR_UART_U1RTS_LCDPS (0x1000)
249#define GPIO_PAR_UART_U1RTS_GPIO (0x0000)
250
251#define GPIO_PAR_UART_U1RXD_MASK (0xF3FF)
252#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)
253#define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800)
254#define GPIO_PAR_UART_U1RXD_GPIO (0x0000)
255
256#define GPIO_PAR_UART_U1TXD_MASK (0xFCFF)
257#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)
258#define GPIO_PAR_UART_U1TXD_SSITXD (0x0200)
259#define GPIO_PAR_UART_U1TXD_GPIO (0x0000)
260
261#define GPIO_PAR_UART_U0CTS_MASK (0xFF3F)
262#define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0)
263#define GPIO_PAR_UART_U0CTS_T1OUT (0x0080)
264#define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040)
265#define GPIO_PAR_UART_U0CTS_GPIO (0x0000)
266
267#define GPIO_PAR_UART_U0RTS_MASK (0xFFCF)
268#define GPIO_PAR_UART_U0RTS_U0RTS (0x0030)
269#define GPIO_PAR_UART_U0RTS_T1IN (0x0020)
270#define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010)
271#define GPIO_PAR_UART_U0RTS_GPIO (0x0000)
272
273#define GPIO_PAR_UART_U0RXD_MASK (0xFFF3)
274#define GPIO_PAR_UART_U0RXD_U0RXD (0x000C)
275#define GPIO_PAR_UART_U0RXD_CANRX (0x0008)
276#define GPIO_PAR_UART_U0RXD_GPIO (0x0000)
277
278#define GPIO_PAR_UART_U0TXD_MASK (0xFFFC)
279#define GPIO_PAR_UART_U0TXD_U0TXD (0x0003)
280#define GPIO_PAR_UART_U0TXD_CANTX (0x0002)
281#define GPIO_PAR_UART_U0TXD_GPIO (0x0000)
282
283/* Bit definitions and macros for PAR_DSPI */
284#define GPIO_PAR_DSPI_PCS0_MASK (0x3F)
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000285#define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0)
286#define GPIO_PAR_DSPI_PCS0_U2RTS (0x80)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600287#define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
288#define GPIO_PAR_DSPI_SIN_MASK (0xCF)
289#define GPIO_PAR_DSPI_SIN_SIN (0x30)
290#define GPIO_PAR_DSPI_SIN_U2RXD (0x20)
291#define GPIO_PAR_DSPI_SIN_GPIO (0x00)
292#define GPIO_PAR_DSPI_SOUT_MASK (0xF3)
293#define GPIO_PAR_DSPI_SOUT_SOUT (0x0C)
294#define GPIO_PAR_DSPI_SOUT_U2TXD (0x08)
295#define GPIO_PAR_DSPI_SOUT_GPIO (0x00)
296#define GPIO_PAR_DSPI_SCK_MASK (0xFC)
297#define GPIO_PAR_DSPI_SCK_SCK (0x03)
298#define GPIO_PAR_DSPI_SCK_U2CTS (0x02)
299#define GPIO_PAR_DSPI_SCK_GPIO (0x00)
300
301/* Bit definitions and macros for PAR_TIMER */
302#define GPIO_PAR_TIMER_T3IN_MASK (0x3F)
303#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
304#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
305#define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40)
306#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
307#define GPIO_PAR_TIMER_T2IN_MASK (0xCF)
308#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
309#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
310#define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10)
311#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
312#define GPIO_PAR_TIMER_T1IN_MASK (0xF3)
313#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
314#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
315#define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04)
316#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
317#define GPIO_PAR_TIMER_T0IN_MASK (0xFC)
318#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
319#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
320#define GPIO_PAR_TIMER_T0IN_LCDREV (0x01)
321#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
322
323/* Bit definitions and macros for GPIO_PAR_LCDCTL */
324#define GPIO_PAR_LCDCTL_ACDOE_MASK (0xE7)
325#define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18)
326#define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10)
327#define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00)
328#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x04)
329#define GPIO_PAR_LCDCTL_LP_HSYNC (0x02)
330#define GPIO_PAR_LCDCTL_LSCLK (0x01)
331
332/* Bit definitions and macros for PAR_IRQ */
333#define GPIO_PAR_IRQ_IRQ4_MASK (0xF3)
334#define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C)
335#define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08)
336#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
337#define GPIO_PAR_IRQ_IRQ1_MASK (0xFC)
338#define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03)
339#define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02)
340#define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01)
341#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
342
343/* Bit definitions and macros for GPIO_PAR_LCDH */
344#define GPIO_PAR_LCDH_LD17_MASK (0xFFFFF3FF)
345#define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00)
346#define GPIO_PAR_LCDH_LD17_LD11 (0x00000800)
347#define GPIO_PAR_LCDH_LD17_GPIO (0x00000000)
348
349#define GPIO_PAR_LCDH_LD16_MASK (0xFFFFFCFF)
350#define GPIO_PAR_LCDH_LD16_LD16 (0x00000300)
351#define GPIO_PAR_LCDH_LD16_LD10 (0x00000200)
352#define GPIO_PAR_LCDH_LD16_GPIO (0x00000000)
353
354#define GPIO_PAR_LCDH_LD15_MASK (0xFFFFFF3F)
355#define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0)
356#define GPIO_PAR_LCDH_LD15_LD9 (0x00000080)
357#define GPIO_PAR_LCDH_LD15_GPIO (0x00000000)
358
359#define GPIO_PAR_LCDH_LD14_MASK (0xFFFFFFCF)
360#define GPIO_PAR_LCDH_LD14_LD14 (0x00000030)
361#define GPIO_PAR_LCDH_LD14_LD8 (0x00000020)
362#define GPIO_PAR_LCDH_LD14_GPIO (0x00000000)
363
364#define GPIO_PAR_LCDH_LD13_MASK (0xFFFFFFF3)
365#define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C)
366#define GPIO_PAR_LCDH_LD13_CANTX (0x00000008)
367#define GPIO_PAR_LCDH_LD13_GPIO (0x00000000)
368
369#define GPIO_PAR_LCDH_LD12_MASK (0xFFFFFFFC)
370#define GPIO_PAR_LCDH_LD12_LD12 (0x00000003)
371#define GPIO_PAR_LCDH_LD12_CANRX (0x00000002)
372#define GPIO_PAR_LCDH_LD12_GPIO (0x00000000)
373
374/* Bit definitions and macros for GPIO_PAR_LCDL */
375#define GPIO_PAR_LCDL_LD11_MASK (0x3FFFFFFF)
376#define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000)
377#define GPIO_PAR_LCDL_LD11_LD7 (0x80000000)
378#define GPIO_PAR_LCDL_LD11_GPIO (0x00000000)
379
380#define GPIO_PAR_LCDL_LD10_MASK (0xCFFFFFFF)
381#define GPIO_PAR_LCDL_LD10_LD10 (0x30000000)
382#define GPIO_PAR_LCDL_LD10_LD6 (0x20000000)
383#define GPIO_PAR_LCDL_LD10_GPIO (0x00000000)
384
385#define GPIO_PAR_LCDL_LD9_MASK (0xF3FFFFFF)
386#define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000)
387#define GPIO_PAR_LCDL_LD9_LD5 (0x08000000)
388#define GPIO_PAR_LCDL_LD9_GPIO (0x00000000)
389
390#define GPIO_PAR_LCDL_LD8_MASK (0xFCFFFFFF)
391#define GPIO_PAR_LCDL_LD8_LD8 (0x03000000)
392#define GPIO_PAR_LCDL_LD8_LD4 (0x02000000)
393#define GPIO_PAR_LCDL_LD8_GPIO (0x00000000)
394
395#define GPIO_PAR_LCDL_LD7_MASK (0xFF3FFFFF)
396#define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000)
397#define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000)
398#define GPIO_PAR_LCDL_LD7_GPIO (0x00000000)
399
400#define GPIO_PAR_LCDL_LD6_MASK (0xFFCFFFFF)
401#define GPIO_PAR_LCDL_LD6_LD6 (0x00300000)
402#define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000)
403#define GPIO_PAR_LCDL_LD6_GPIO (0x00000000)
404
405#define GPIO_PAR_LCDL_LD5_MASK (0xFFF3FFFF)
406#define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000)
407#define GPIO_PAR_LCDL_LD5_LD3 (0x00080000)
408#define GPIO_PAR_LCDL_LD5_GPIO (0x00000000)
409
410#define GPIO_PAR_LCDL_LD4_MASK (0xFFFCFFFF)
411#define GPIO_PAR_LCDL_LD4_LD4 (0x00030000)
412#define GPIO_PAR_LCDL_LD4_LD2 (0x00020000)
413#define GPIO_PAR_LCDL_LD4_GPIO (0x00000000)
414
415#define GPIO_PAR_LCDL_LD3_MASK (0xFFFF3FFF)
416#define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000)
417#define GPIO_PAR_LCDL_LD3_LD1 (0x00008000)
418#define GPIO_PAR_LCDL_LD3_GPIO (0x00000000)
419
420#define GPIO_PAR_LCDL_LD2_MASK (0xFFFFCFFF)
421#define GPIO_PAR_LCDL_LD2_LD2 (0x00003000)
422#define GPIO_PAR_LCDL_LD2_LD0 (0x00002000)
423#define GPIO_PAR_LCDL_LD2_GPIO (0x00000000)
424
425#define GPIO_PAR_LCDL_LD1_MASK (0xFFFFF3FF)
426#define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00)
427#define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800)
428#define GPIO_PAR_LCDL_LD1_GPIO (0x00000000)
429
430#define GPIO_PAR_LCDL_LD0_MASK (0xFFFFFCFF)
431#define GPIO_PAR_LCDL_LD0_LD0 (0x00000300)
432#define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200)
433#define GPIO_PAR_LCDL_LD0_GPIO (0x00000000)
434
435/* Bit definitions and macros for MSCR_FB */
436#define GPIO_MSCR_FB_DUPPER_MASK (0xCF)
437#define GPIO_MSCR_FB_DUPPER_25V_33V (0x30)
438#define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20)
439#define GPIO_MSCR_FB_DUPPER_OD (0x10)
440#define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00)
441
442#define GPIO_MSCR_FB_DLOWER_MASK (0xF3)
443#define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C)
444#define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08)
445#define GPIO_MSCR_FB_DLOWER_OD (0x04)
446#define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00)
447
448#define GPIO_MSCR_FB_ADDRCTL_MASK (0xFC)
449#define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03)
450#define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02)
451#define GPIO_MSCR_FB_ADDRCTL_OD (0x01)
452#define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00)
453
454/* Bit definitions and macros for MSCR_SDRAM */
455#define GPIO_MSCR_SDRAM_SDCLKB_MASK (0xCF)
456#define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30)
457#define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20)
458#define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10)
459#define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00)
460
461#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3)
462#define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C)
463#define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08)
464#define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04)
465#define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00)
466
467#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC)
468#define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03)
469#define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02)
470#define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01)
471#define GPIO_MSCR_SDRAM_SDCTL_HALF_18V (0x00)
472
473/* Bit definitions and macros for Drive Strength Control */
474#define DSCR_LOAD_50PF (0x03)
475#define DSCR_LOAD_30PF (0x02)
476#define DSCR_LOAD_20PF (0x01)
477#define DSCR_LOAD_10PF (0x00)
478
479/*********************************************************************
480* SDRAM Controller (SDRAMC)
481*********************************************************************/
482
483/* Bit definitions and macros for SDMR */
484#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
485#define SDRAMC_SDMR_CMD (0x00010000) /* Command */
486#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
487#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
488#define SDRAMC_SDMR_BK_LMR (0x00000000)
489#define SDRAMC_SDMR_BK_LEMR (0x40000000)
490
491/* Bit definitions and macros for SDCR */
492#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
493#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
494#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
495#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
496#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
497#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
498#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
499#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */
500#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
501#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
502#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
503#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
504#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */
505#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000)
506
507/* Bit definitions and macros for SDCFG1 */
508#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */
509#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */
510#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */
511#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */
512#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */
513#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
514#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
515
516/* Bit definitions and macros for SDCFG2 */
517#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */
518#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */
519#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
520#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
521
522/* Bit definitions and macros for SDCS group */
523#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
524#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
525#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
526#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
527#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
528#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
529#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
530#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
531#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
532#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
533#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
534#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
535#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
536#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
537#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
538#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
539#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
540
541/*********************************************************************
542* Phase Locked Loop (PLL)
543*********************************************************************/
544
545/* Bit definitions and macros for PCR */
546#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */
547#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for bus/flexbus clock frequency */
548#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for SDRAM clock frequency */
549#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */
550#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */
551#define PLL_PCR_PFDR_MASK (0x000F0000)
552#define PLL_PCR_OUTDIV5_MASK (0x000F0000)
553#define PLL_PCR_OUTDIV3_MASK (0x00000F00)
554#define PLL_PCR_OUTDIV2_MASK (0x000000F0)
555#define PLL_PCR_OUTDIV1_MASK (0x0000000F)
556
557/* Bit definitions and macros for PSR */
558#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */
559#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */
560#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */
561#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */
562
563/********************************************************************/
564
565#endif /* __MCF5227X__ */