blob: c351b23b6334ac5f46b613f8a6a21b304b761b35 [file] [log] [blame]
Graeme Russ8c63d472009-02-24 21:14:45 +11001/*
2 * (C) Copyright 2002
3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/io.h>
26#include <asm/i8254.h>
27#include <asm/ibmpc.h>
Graeme Russea0c3772009-08-23 12:59:47 +100028#include <asm/interrupt.h>
Graeme Russ8c63d472009-02-24 21:14:45 +110029
30#define TIMER0_VALUE 0x04aa /* 1kHz 1.9318MHz / 1000 */
31#define TIMER2_VALUE 0x0a8e /* 440Hz */
32
Graeme Russea0c3772009-08-23 12:59:47 +100033static int timer_init_done = 0;
34
Graeme Russ8c63d472009-02-24 21:14:45 +110035int timer_init(void)
36{
37 /* initialize timer 0 and 2
38 *
39 * Timer 0 is used to increment system_tick 1000 times/sec
40 * Timer 1 was used for DRAM refresh in early PC's
41 * Timer 2 is used to drive the speaker
42 * (to stasrt a beep: write 3 to port 0x61,
43 * to stop it again: write 0)
44 */
45 outb (PIT_CMD_CTR0 | PIT_CMD_BOTH | PIT_CMD_MODE2,
46 PIT_BASE + PIT_COMMAND);
47 outb (TIMER0_VALUE & 0xff, PIT_BASE + PIT_T0);
48 outb (TIMER0_VALUE >> 8, PIT_BASE + PIT_T0);
49
50 outb (PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3,
51 PIT_BASE + PIT_COMMAND);
52 outb (TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2);
53 outb (TIMER2_VALUE >> 8, PIT_BASE + PIT_T2);
54
55 irq_install_handler (0, timer_isr, NULL);
56 unmask_irq (0);
57
Graeme Russea0c3772009-08-23 12:59:47 +100058 timer_init_done = 1;
59
Graeme Russ8c63d472009-02-24 21:14:45 +110060 return 0;
61}
62
63static u16 read_pit(void)
64{
65 u8 low;
66
67 outb (PIT_CMD_LATCH, PIT_BASE + PIT_COMMAND);
68 low = inb (PIT_BASE + PIT_T0);
69
70 return ((inb (PIT_BASE + PIT_T0) << 8) | low);
71}
72
73/* this is not very exact */
74void udelay (unsigned long usec)
75{
76 int counter;
77 int wraps;
78
79 if (timer_init_done)
80 {
81 counter = read_pit ();
82 wraps = usec / 1000;
83 usec = usec % 1000;
84
85 usec *= 1194;
86 usec /= 1000;
87 usec += counter;
88
89 while (usec > 1194) {
90 usec -= 1194;
91 wraps++;
92 }
93
94 while (1) {
95 int new_count = read_pit ();
96
97 if (((new_count < usec) && !wraps) || wraps < 0)
98 break;
99
100 if (new_count > counter)
101 wraps--;
102
103 counter = new_count;
104 }
105 }
106
107}