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wdenkdb2f721f2003-03-06 00:58:30 +00001/*
2 * (C) Copyright 2003
3 * EMK Elektronik GmbH <www.emk-elektronik.de>
4 * Reinhard Meyer <r.meyer@emk-elektronik.de>
5 *
6 * Configuation settings for the TOP860 board.
7 *
8 * -----------------------------------------------------------------
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27/*
wdenk945af8d2003-07-16 21:53:01 +000028 * TOP860 is a simple module:
29 * 16-bit wide FLASH on CS0 (2MB or more)
30 * 32-bit wide DRAM on CS2 (either 4MB or 16MB)
31 * FEC with Am79C874 100-Base-T and Fiber Optic
32 * Ports available, but we choose SMC1 for Console
wdenkdb2f721f2003-03-06 00:58:30 +000033 * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set
wdenk945af8d2003-07-16 21:53:01 +000034 * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
35 *
36 * This config has been copied from MBX.h / MBX860T.h
wdenkdb2f721f2003-03-06 00:58:30 +000037 */
38/*
39 * board/config.h - configuration options, board specific
40 */
41
42#ifndef __CONFIG_H
43#define __CONFIG_H
44
45/*
46 * High Level Configuration Options
47 * (easy to change)
48 */
49
50/*-----------------------------------------------------------------------
51 * CPU and BOARD type
52 */
53#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
54#define CONFIG_MPC860T 1 /* even better... an FEC! */
55#define CONFIG_TOP860 1 /* ...on a TOP860 module */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020056
57#define CONFIG_SYS_TEXT_BASE 0x80000000
58
wdenkdb2f721f2003-03-06 00:58:30 +000059#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk945af8d2003-07-16 21:53:01 +000060#define CONFIG_IDENT_STRING " EMK TOP860"
wdenkdb2f721f2003-03-06 00:58:30 +000061
62/*-----------------------------------------------------------------------
63 * CLOCK settings
64 */
wdenk945af8d2003-07-16 21:53:01 +000065#define CONFIG_SYSCLK 49152000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_XTAL 32768
wdenk945af8d2003-07-16 21:53:01 +000067#define CONFIG_EBDF 1
68#define CONFIG_COM 3
69#define CONFIG_RTC_MPC8xx
70
wdenkdb2f721f2003-03-06 00:58:30 +000071/*-----------------------------------------------------------------------
72 * Physical memory map as defined by EMK
73 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register */
75#define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH in final mapping */
76#define CONFIG_SYS_DRAM_BASE 0x00000000 /* DRAM in final mapping */
77#define CONFIG_SYS_FLASH_MAX 0x00400000 /* max FLASH to expect */
78#define CONFIG_SYS_DRAM_MAX 0x01000000 /* max DRAM to expect */
wdenk945af8d2003-07-16 21:53:01 +000079
wdenkdb2f721f2003-03-06 00:58:30 +000080/*-----------------------------------------------------------------------
81 * derived values
82 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_MF (CONFIG_SYSCLK/CONFIG_SYS_XTAL)
84#define CONFIG_SYS_CPUCLOCK CONFIG_SYSCLK
85#define CONFIG_SYS_BRGCLOCK CONFIG_SYSCLK
86#define CONFIG_SYS_BUSCLOCK (CONFIG_SYSCLK >> CONFIG_EBDF)
87#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk945af8d2003-07-16 21:53:01 +000088#define CONFIG_8xx_GCLK_FREQ CONFIG_SYSCLK
89
wdenkdb2f721f2003-03-06 00:58:30 +000090/*-----------------------------------------------------------------------
91 * FLASH organization
92 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
94#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenkdb2f721f2003-03-06 00:58:30 +000095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
97#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk945af8d2003-07-16 21:53:01 +000098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_FLASH_CFI
wdenkdb2f721f2003-03-06 00:58:30 +0000100
101/*-----------------------------------------------------------------------
102 * Command interpreter
103 */
104#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
105#undef CONFIG_8xx_CONS_SMC2
106#define CONFIG_BAUDRATE 9600
wdenk945af8d2003-07-16 21:53:01 +0000107
wdenkdb2f721f2003-03-06 00:58:30 +0000108/*
109 * Allow partial commands to be matched to uniqueness.
110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_MATCH_PARTIAL_CMD
wdenkdb2f721f2003-03-06 00:58:30 +0000112
Jon Loeligera5562902007-07-08 15:31:57 -0500113
wdenkdb2f721f2003-03-06 00:58:30 +0000114/*
Jon Loeligera5562902007-07-08 15:31:57 -0500115 * Command line configuration.
wdenkdb2f721f2003-03-06 00:58:30 +0000116 */
Jon Loeligera5562902007-07-08 15:31:57 -0500117#include <config_cmd_default.h>
118
119#define CONFIG_CMD_ASKENV
120#define CONFIG_CMD_DHCP
121#define CONFIG_CMD_I2C
122#define CONFIG_CMD_EEPROM
123#define CONFIG_CMD_REGINFO
124#define CONFIG_CMD_IMMAP
125#define CONFIG_CMD_ELF
126#define CONFIG_CMD_DATE
127#define CONFIG_CMD_MII
128#define CONFIG_CMD_BEDBUG
129
wdenkdb2f721f2003-03-06 00:58:30 +0000130
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200131#define CONFIG_SOURCE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
wdenkdb2f721f2003-03-06 00:58:30 +0000133#undef CONFIG_LOADS_ECHO /* NO echo on for serial download */
134
wdenkdb2f721f2003-03-06 00:58:30 +0000135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_LONGHELP /* undef to save memory */
137#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk945af8d2003-07-16 21:53:01 +0000138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */
wdenk945af8d2003-07-16 21:53:01 +0000140
wdenk945af8d2003-07-16 21:53:01 +0000141
Jon Loeligera5562902007-07-08 15:31:57 -0500142#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000144#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000146#endif
wdenk945af8d2003-07-16 21:53:01 +0000147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
149#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
150#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000151
152/*-----------------------------------------------------------------------
153 * Memory Test Command
154 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
156#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk945af8d2003-07-16 21:53:01 +0000157
wdenkdb2f721f2003-03-06 00:58:30 +0000158/*-----------------------------------------------------------------------
159 * Environment handler
160 * only the first 6k in EEPROM are available for user. Of that we use 256b
161 */
wdenk945af8d2003-07-16 21:53:01 +0000162#define CONFIG_SOFT_I2C
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200163#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200164#define CONFIG_ENV_OFFSET 0x1000
165#define CONFIG_ENV_SIZE 0x0700
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
167#define CONFIG_SYS_FACT_OFFSET 0x1800
168#define CONFIG_SYS_FACT_SIZE 0x0800
169#define CONFIG_SYS_I2C_FACT_ADDR 0x57
170#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
171#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
172#define CONFIG_SYS_EEPROM_SIZE 0x2000
173#define CONFIG_SYS_I2C_SPEED 100000
174#define CONFIG_SYS_I2C_SLAVE 0xFE
175#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
wdenk945af8d2003-07-16 21:53:01 +0000176#define CONFIG_ENV_OVERWRITE
177#define CONFIG_MISC_INIT_R
178
179#if defined (CONFIG_SOFT_I2C)
180#define SDA 0x00010
181#define SCL 0x00020
Wolfgang Denkf57f70a2005-10-13 01:45:54 +0200182#define __I2C_DIR immr->im_cpm.cp_pbdir
183#define __I2C_DAT immr->im_cpm.cp_pbdat
184#define __I2C_PAR immr->im_cpm.cp_pbpar
185#define __I2C_ODR immr->im_cpm.cp_pbodr
186#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \
187 __I2C_ODR &= ~(SDA|SCL); \
188 __I2C_DAT |= (SDA|SCL); \
189 __I2C_DIR|=(SDA|SCL); }
190#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
191#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
192#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
193#define I2C_DELAY { udelay(5); }
194#define I2C_ACTIVE { __I2C_DIR |= SDA; }
195#define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
wdenkdb2f721f2003-03-06 00:58:30 +0000196#endif
197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenkdb2f721f2003-03-06 00:58:30 +0000199
200/*-----------------------------------------------------------------------
201 * defines we need to get FEC running
wdenk945af8d2003-07-16 21:53:01 +0000202 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200203#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */
204#define FEC_ENET 1 /* eth.c needs it that way... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_DISCOVER_PHY 1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200206#define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500207#define CONFIG_MII_INIT 1
wdenkdb2f721f2003-03-06 00:58:30 +0000208#define CONFIG_PHY_ADDR 31
wdenk945af8d2003-07-16 21:53:01 +0000209
wdenkdb2f721f2003-03-06 00:58:30 +0000210/*-----------------------------------------------------------------------
211 * adresses
wdenk945af8d2003-07-16 21:53:01 +0000212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200214#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk945af8d2003-07-16 21:53:01 +0000216
wdenkdb2f721f2003-03-06 00:58:30 +0000217/*-----------------------------------------------------------------------
218 * Start addresses for the final memory configuration
219 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkdb2f721f2003-03-06 00:58:30 +0000221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_SDRAM_BASE 0x00000000
223#define CONFIG_SYS_FLASH_BASE 0x80000000
wdenk945af8d2003-07-16 21:53:01 +0000224
wdenkdb2f721f2003-03-06 00:58:30 +0000225/*-----------------------------------------------------------------------
226 * Definitions for initial stack pointer and data area (in DPRAM)
227 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200229#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200230#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
232#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
233#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8)
wdenkdb2f721f2003-03-06 00:58:30 +0000234
235/*-----------------------------------------------------------------------
236 * Cache Configuration
237 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligera5562902007-07-08 15:31:57 -0500239#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkdb2f721f2003-03-06 00:58:30 +0000241#endif
242
243/* Interrupt level assignments.
244*/
245#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
246
wdenkdb2f721f2003-03-06 00:58:30 +0000247/*-----------------------------------------------------------------------
248 * Debug Enable Register
249 *-----------------------------------------------------------------------
250 *
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_DER 0 /* used in start.S */
wdenkdb2f721f2003-03-06 00:58:30 +0000253
254/*-----------------------------------------------------------------------
255 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
256 *-----------------------------------------------------------------------
wdenk945af8d2003-07-16 21:53:01 +0000257 * set up PLPRCR (PLL, Low-Power, and Reset Control Register)
258 * 12 MF calculated Multiplication factor
259 * 4 0 0000
260 * 1 SPLSS 0 System PLL lock status sticky
261 * 1 TEXPS 1 Timer expired status
262 * 1 0 0
263 * 1 TMIST 0 Timers interrupt status
264 * 1 0 0
265 * 1 CSRC 0 Clock source (0=DFNH, 1=DFNL)
266 * 2 LPM 00 Low-power modes
267 * 1 CSR 0 Checkstop reset enable
268 * 1 LOLRE 0 Loss-of-lock reset enable
269 * 1 FIOPD 0 Force I/O pull down
wdenk42d1f032003-10-15 23:53:47 +0000270 * 5 0 00000
wdenkdb2f721f2003-03-06 00:58:30 +0000271 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_PLPRCR (PLPRCR_TEXPS | ((CONFIG_SYS_MF-1)<<20))
wdenk945af8d2003-07-16 21:53:01 +0000273
wdenkdb2f721f2003-03-06 00:58:30 +0000274/*-----------------------------------------------------------------------
275 * SYPCR - System Protection Control 11-9
276 * SYPCR can only be written once after reset!
277 *-----------------------------------------------------------------------
wdenk945af8d2003-07-16 21:53:01 +0000278 * set up SYPCR:
279 * 16 SWTC 0xffff Software watchdog timer count
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200280 * 8 BMT 0xff Bus monitor timing
wdenk945af8d2003-07-16 21:53:01 +0000281 * 1 BME 1 Bus monitor enable
282 * 3 0 000
283 * 1 SWF 1 Software watchdog freeze
284 * 1 SWE 0/1 Software watchdog enable
285 * 1 SWRI 0/1 Software watchdog reset/interrupt select (1=HRESET)
286 * 1 SWP 0/1 Software watchdog prescale (1=/2048)
wdenkdb2f721f2003-03-06 00:58:30 +0000287 */
288#if defined (CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200290 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
wdenkdb2f721f2003-03-06 00:58:30 +0000291#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
wdenkdb2f721f2003-03-06 00:58:30 +0000293#endif
294
295/*-----------------------------------------------------------------------
296 * SIUMCR - SIU Module Configuration 11-6
297 *-----------------------------------------------------------------------
wdenk945af8d2003-07-16 21:53:01 +0000298 * set up SIUMCR
299 * 1 EARB 0 External arbitration
300 * 3 EARP 000 External arbitration request priority
301 * 4 0 0000
302 * 1 DSHW 0 Data show cycles
303 * 2 DBGC 00 Debug pin configuration
304 * 2 DBPC 00 Debug port pins configuration
305 * 1 0 0
306 * 1 FRC 0 FRZ pin configuration
307 * 1 DLK 0 Debug register lock
308 * 1 OPAR 0 Odd parity
309 * 1 PNCS 0 Parity enable for non memory controller regions
310 * 1 DPC 0 Data parity pins configuration
311 * 1 MPRE 0 Multiprocessor reservation enable
312 * 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
313 * 1 AEME 0 Async external master enable
314 * 1 SEME 0 Sync external master enable
315 * 1 BSC 0 Byte strobe configuration
316 * 1 GB5E 0 GPL_B5 enable
wdenk42d1f032003-10-15 23:53:47 +0000317 * 1 B2DD 0 Bank 2 double drive
318 * 1 B3DD 0 Bank 3 double drive
wdenk945af8d2003-07-16 21:53:01 +0000319 * 4 0 0000
wdenkdb2f721f2003-03-06 00:58:30 +0000320 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC11)
wdenk945af8d2003-07-16 21:53:01 +0000322
wdenkdb2f721f2003-03-06 00:58:30 +0000323/*-----------------------------------------------------------------------
324 * TBSCR - Time Base Status and Control 11-26
325 *-----------------------------------------------------------------------
326 * Clear Reference Interrupt Status, Timebase freezing enabled
327 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkdb2f721f2003-03-06 00:58:30 +0000329
330/*-----------------------------------------------------------------------
331 * PISCR - Periodic Interrupt Status and Control 11-31
332 *-----------------------------------------------------------------------
333 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
334 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
wdenkdb2f721f2003-03-06 00:58:30 +0000336
337/*-----------------------------------------------------------------------
338 * SCCR - System Clock and reset Control Register 15-27
339 *-----------------------------------------------------------------------
wdenk945af8d2003-07-16 21:53:01 +0000340 * set up SCCR (System Clock and Reset Control Register)
341 * 1 0 0
342 * 2 COM 11 Clock output module (00=full, 01=half, 11=off)
343 * 3 0 000
344 * 1 TBS 1 Timebase source (0=OSCCLK, 1=GCLK2)
345 * 1 RTDIV 0 Real-time clock divide (0=/4, 1=/512)
346 * 1 RTSEL 0 Real-time clock select (0=OSCM, 1=EXTCLK)
347 * 1 CRQEN 0 CPM request enable
348 * 1 PRQEN 0 Power management request enable
349 * 2 0 00
350 * 2 EBDF xx External bus division factor
351 * 2 0 00
352 * 2 DFSYNC 00 Division factor for SYNCLK
353 * 2 DFBRG 00 Division factor for BRGCLK
354 * 3 DFNL 000 Division factor low frequency
355 * 3 DFNH 000 Division factor high frequency
356 * 5 0 00000
wdenkdb2f721f2003-03-06 00:58:30 +0000357 */
358#define SCCR_MASK 0
wdenk42dfe7a2004-03-14 22:25:36 +0000359#ifdef CONFIG_EBDF
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360 #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
wdenk945af8d2003-07-16 21:53:01 +0000361#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362 #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS)
wdenk945af8d2003-07-16 21:53:01 +0000363#endif
wdenkdb2f721f2003-03-06 00:58:30 +0000364
365/*-----------------------------------------------------------------------
366 * Chip Select 0 - FLASH
367 *-----------------------------------------------------------------------
368 * Preliminary Values
369 */
370/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR)
372#define CONFIG_SYS_OR0_PRELIM (-CONFIG_SYS_FLASH_MAX | CONFIG_SYS_OR_TIMING_FLASH)
373#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V )
wdenk945af8d2003-07-16 21:53:01 +0000374
wdenkdb2f721f2003-03-06 00:58:30 +0000375/*-----------------------------------------------------------------------
376 * misc
377 *-----------------------------------------------------------------------
378 *
379 */
380/*
381 * Set the autoboot delay in seconds. A delay of -1 disables autoboot
382 */
383#define CONFIG_BOOTDELAY 5
384
385/*
386 * Pass the clock frequency to the Linux kernel in units of MHz
387 */
388#define CONFIG_CLOCKS_IN_MHZ
389
390#define CONFIG_PREBOOT \
391 "echo;echo"
392
393#undef CONFIG_BOOTARGS
394#define CONFIG_BOOTCOMMAND \
395 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100396 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
397 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenkdb2f721f2003-03-06 00:58:30 +0000398 "bootm"
399
400/*
401 * BOOTP options
402 */
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500403#define CONFIG_BOOTP_SUBNETMASK
404#define CONFIG_BOOTP_GATEWAY
405#define CONFIG_BOOTP_HOSTNAME
406#define CONFIG_BOOTP_BOOTPATH
407#define CONFIG_BOOTP_BOOTFILESIZE
wdenk42d1f032003-10-15 23:53:47 +0000408
wdenkdb2f721f2003-03-06 00:58:30 +0000409
410/*
411 * Set default IP stuff just to get bootstrap entries into the
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200412 * environment so that we can source the full default environment.
wdenkdb2f721f2003-03-06 00:58:30 +0000413 */
414#define CONFIG_ETHADDR 9a:52:63:15:85:25
415#define CONFIG_SERVERIP 10.0.4.200
416#define CONFIG_IPADDR 10.0.4.111
wdenk945af8d2003-07-16 21:53:01 +0000417
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
419#define CONFIG_SYS_TFTP_LOADADDR 0x00100000
wdenk945af8d2003-07-16 21:53:01 +0000420
wdenkdb2f721f2003-03-06 00:58:30 +0000421/*
422 * For booting Linux, the board info and command line data
423 * have to be in the first 8 MB of memory, since this is
424 * the maximum mapped by the Linux kernel during initialization.
425 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkdb2f721f2003-03-06 00:58:30 +0000427
wdenkdb2f721f2003-03-06 00:58:30 +0000428#endif /* __CONFIG_H */