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Haavard Skinnemoen667568d2007-10-29 13:02:54 +01001/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * Configuration settings for the ATSTK1003 CPU daughterboard
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
Andreas Bießmann5d73bc72010-11-04 23:15:30 +000027#include <asm/arch/hardware.h>
Haavard Skinnemoena23e2772008-05-19 11:36:28 +020028
Andreas Bießmann38a39392011-04-18 04:12:37 +000029#define CONFIG_AVR32
30#define CONFIG_AT32AP
31#define CONFIG_AT32AP7001
32#define CONFIG_ATSTK1003
33#define CONFIG_ATSTK1000
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010034
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010035/*
36 * Timer clock frequency. We're using the CPU-internal COUNT register
37 * for this, so this is equivalent to the CPU core clock frequency
38 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_HZ 1000
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010040
41/*
42 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
43 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
44 * PLL frequency.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010046 */
Andreas Bießmann38a39392011-04-18 04:12:37 +000047#define CONFIG_PLL
48#define CONFIG_SYS_POWER_MANAGER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_OSC0_HZ 20000000
50#define CONFIG_SYS_PLL0_DIV 1
51#define CONFIG_SYS_PLL0_MUL 7
52#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010053/*
54 * Set the CPU running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010056 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_CLKDIV_CPU 0
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010058/*
59 * Set the HSB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010061 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_CLKDIV_HSB 1
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010063/*
64 * Set the PBA running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010066 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_CLKDIV_PBA 2
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010068/*
69 * Set the PBB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010071 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_CLKDIV_PBB 1
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010073
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070074/* Reserve VM regions for SDRAM and NOR flash */
75#define CONFIG_SYS_NR_VM_REGIONS 2
76
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010077/*
78 * The PLLOPT register controls the PLL like this:
79 * icp = PLLOPT<2>
80 * ivco = PLLOPT<1:0>
81 *
82 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
83 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_PLL0_OPT 0x04
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010085
Andreas Bießmannf4278b72010-11-04 23:15:31 +000086#define CONFIG_USART_BASE ATMEL_BASE_USART1
87#define CONFIG_USART_ID 1
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010088
89/* User serviceable stuff */
Andreas Bießmann38a39392011-04-18 04:12:37 +000090#define CONFIG_DOS_PARTITION
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010091
Andreas Bießmann38a39392011-04-18 04:12:37 +000092#define CONFIG_CMDLINE_TAG
93#define CONFIG_SETUP_MEMORY_TAGS
94#define CONFIG_INITRD_TAG
Haavard Skinnemoen667568d2007-10-29 13:02:54 +010095
96#define CONFIG_STACKSIZE (2048)
97
98#define CONFIG_BAUDRATE 115200
99#define CONFIG_BOOTARGS \
100 "console=ttyS0 root=/dev/mmcblk0p1 rootwait"
101
102#define CONFIG_BOOTCOMMAND \
Sven Schnelle72fa4672011-10-21 14:49:25 +0200103 "mmc rescan; ext2load mmc 0:1 0x10400000 /boot/uImage; bootm"
Haavard Skinnemoen667568d2007-10-29 13:02:54 +0100104
105/*
106 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
107 * data on the serial line may interrupt the boot sequence.
108 */
109#define CONFIG_BOOTDELAY 1
Andreas Bießmann38a39392011-04-18 04:12:37 +0000110#define CONFIG_AUTOBOOT
111#define CONFIG_AUTOBOOT_KEYED
Wolfgang Denkc37207d2008-07-16 16:38:59 +0200112#define CONFIG_AUTOBOOT_PROMPT \
113 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Haavard Skinnemoen667568d2007-10-29 13:02:54 +0100114#define CONFIG_AUTOBOOT_DELAY_STR "d"
115#define CONFIG_AUTOBOOT_STOP_STR " "
116
117/*
118 * Command line configuration.
119 */
120#include <config_cmd_default.h>
121
122#define CONFIG_CMD_ASKENV
123#define CONFIG_CMD_EXT2
124#define CONFIG_CMD_FAT
125#define CONFIG_CMD_JFFS2
126#define CONFIG_CMD_MMC
127
128#undef CONFIG_CMD_FPGA
129#undef CONFIG_CMD_NET
130#undef CONFIG_CMD_NFS
131#undef CONFIG_CMD_SETGETDCR
132#undef CONFIG_CMD_XIMG
133
Andreas Bießmann38a39392011-04-18 04:12:37 +0000134#define CONFIG_ATMEL_USART
135#define CONFIG_PORTMUX_PIO
136#define CONFIG_SYS_HSDRAMC
137#define CONFIG_MMC
Sven Schnelle72fa4672011-10-21 14:49:25 +0200138#define CONFIG_GENERIC_ATMEL_MCI
139#define CONFIG_GENERIC_MMC
140#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1
Haavard Skinnemoen667568d2007-10-29 13:02:54 +0100141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_DCACHE_LINESZ 32
143#define CONFIG_SYS_ICACHE_LINESZ 32
Haavard Skinnemoen667568d2007-10-29 13:02:54 +0100144
145#define CONFIG_NR_DRAM_BANKS 1
146
Andreas Bießmann22178652011-06-28 04:15:58 +0000147#define CONFIG_SYS_FLASH_CFI
148#define CONFIG_FLASH_CFI_DRIVER
Haavard Skinnemoen667568d2007-10-29 13:02:54 +0100149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_FLASH_BASE 0x00000000
151#define CONFIG_SYS_FLASH_SIZE 0x800000
152#define CONFIG_SYS_MAX_FLASH_BANKS 1
153#define CONFIG_SYS_MAX_FLASH_SECT 135
Haavard Skinnemoen667568d2007-10-29 13:02:54 +0100154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmann47293c12011-04-18 04:12:44 +0000156#define CONFIG_SYS_TEXT_BASE 0x00000000
Haavard Skinnemoen667568d2007-10-29 13:02:54 +0100157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
159#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
160#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
Haavard Skinnemoen667568d2007-10-29 13:02:54 +0100161
Andreas Bießmann38a39392011-04-18 04:12:37 +0000162#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200163#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Haavard Skinnemoen667568d2007-10-29 13:02:54 +0100165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Haavard Skinnemoen667568d2007-10-29 13:02:54 +0100167
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_MALLOC_LEN (256*1024)
Haavard Skinnemoen667568d2007-10-29 13:02:54 +0100169
170/* Allow 4MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
172#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Haavard Skinnemoen667568d2007-10-29 13:02:54 +0100173
174/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_PROMPT "U-Boot> "
176#define CONFIG_SYS_CBSIZE 256
177#define CONFIG_SYS_MAXARGS 16
178#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Andreas Bießmann38a39392011-04-18 04:12:37 +0000179#define CONFIG_SYS_LONGHELP
Haavard Skinnemoen667568d2007-10-29 13:02:54 +0100180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
182#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
183#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Haavard Skinnemoen667568d2007-10-29 13:02:54 +0100184
185#endif /* __CONFIG_H */