Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 1 | if TEGRA |
| 2 | |
Simon Glass | 53b5bf3 | 2016-09-12 23:18:39 -0600 | [diff] [blame] | 3 | config SPL_GPIO_SUPPORT |
| 4 | default y |
| 5 | |
Simon Glass | 77d2f7f | 2016-09-12 23:18:41 -0600 | [diff] [blame] | 6 | config SPL_LIBCOMMON_SUPPORT |
| 7 | default y |
| 8 | |
Simon Glass | cc4288e | 2016-09-12 23:18:43 -0600 | [diff] [blame] | 9 | config SPL_LIBGENERIC_SUPPORT |
| 10 | default y |
| 11 | |
Simon Glass | e00f76c | 2016-09-12 23:18:56 -0600 | [diff] [blame] | 12 | config SPL_SERIAL_SUPPORT |
| 13 | default y |
| 14 | |
Stephen Warren | 49626ea | 2016-07-18 12:17:11 -0600 | [diff] [blame] | 15 | config TEGRA_IVC |
| 16 | bool "Tegra IVC protocol" |
| 17 | help |
| 18 | IVC (Inter-VM Communication) protocol is a Tegra-specific IPC |
| 19 | (Inter Processor Communication) framework. Within the context of |
| 20 | U-Boot, it is typically used for communication between the main CPU |
| 21 | and various auxiliary processors. |
| 22 | |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 23 | config TEGRA_COMMON |
| 24 | bool "Tegra common options" |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame^] | 25 | select BINMAN |
| 26 | select BOARD_EARLY_INIT_F |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 27 | select CLK |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 28 | select DM |
Simon Glass | 96350f7 | 2015-11-29 13:18:01 -0700 | [diff] [blame] | 29 | select DM_ETH |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 30 | select DM_GPIO |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 31 | select DM_I2C |
Simon Glass | f77f5e9 | 2015-10-18 21:17:16 -0600 | [diff] [blame] | 32 | select DM_KEYBOARD |
Tom Warren | 6a474db | 2016-09-13 10:45:48 -0600 | [diff] [blame] | 33 | select DM_MMC |
Simon Glass | 91c08af | 2016-01-30 16:38:01 -0700 | [diff] [blame] | 34 | select DM_PWM |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 35 | select DM_RESET |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 36 | select DM_SERIAL |
| 37 | select DM_SPI |
| 38 | select DM_SPI_FLASH |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 39 | select MISC |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 40 | select OF_CONTROL |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame^] | 41 | select SPI |
Simon Glass | d6ef8a6 | 2016-02-16 18:09:19 -0700 | [diff] [blame] | 42 | select VIDCONSOLE_AS_LCD if DM_VIDEO |
Daniel Thompson | 221a949 | 2017-05-19 17:26:58 +0100 | [diff] [blame] | 43 | imply CRC32_VERIFY |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 44 | |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 45 | config TEGRA_NO_BPMP |
| 46 | bool "Tegra common options for SoCs without BPMP" |
| 47 | select TEGRA_CAR |
| 48 | select TEGRA_CAR_CLOCK |
| 49 | select TEGRA_CAR_RESET |
| 50 | |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 51 | config TEGRA_ARMV7_COMMON |
| 52 | bool "Tegra 32-bit common options" |
Lokesh Vutla | acf1500 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 53 | select CPU_V7A |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 54 | select SPL |
Ley Foon Tan | 0680f1b | 2017-05-03 17:13:32 +0800 | [diff] [blame] | 55 | select SPL_BOARD_INIT if SPL |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 56 | select SUPPORT_SPL |
| 57 | select TEGRA_COMMON |
Stephen Warren | 601800b | 2016-05-12 12:07:41 -0600 | [diff] [blame] | 58 | select TEGRA_GPIO |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 59 | select TEGRA_NO_BPMP |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 60 | |
| 61 | config TEGRA_ARMV8_COMMON |
| 62 | bool "Tegra 64-bit common options" |
| 63 | select ARM64 |
Stephen Warren | ddecaaf | 2018-01-03 14:31:52 -0700 | [diff] [blame] | 64 | select LINUX_KERNEL_IMAGE_HEADER |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 65 | select TEGRA_COMMON |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 66 | |
Stephen Warren | ddecaaf | 2018-01-03 14:31:52 -0700 | [diff] [blame] | 67 | if TEGRA_ARMV8_COMMON |
| 68 | config LNX_KRNL_IMG_TEXT_OFFSET_BASE |
| 69 | default 0x80000000 |
| 70 | endif |
| 71 | |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 72 | choice |
| 73 | prompt "Tegra SoC select" |
Joe Hershberger | a26cd04 | 2015-05-12 14:46:23 -0500 | [diff] [blame] | 74 | optional |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 75 | |
| 76 | config TEGRA20 |
| 77 | bool "Tegra20 family" |
Tom Rini | 8dda2e2 | 2017-03-07 07:13:42 -0500 | [diff] [blame] | 78 | select ARM_ERRATA_716044 |
| 79 | select ARM_ERRATA_742230 |
| 80 | select ARM_ERRATA_751472 |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 81 | select TEGRA_ARMV7_COMMON |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 82 | |
| 83 | config TEGRA30 |
| 84 | bool "Tegra30 family" |
Tom Rini | 8dda2e2 | 2017-03-07 07:13:42 -0500 | [diff] [blame] | 85 | select ARM_ERRATA_743622 |
| 86 | select ARM_ERRATA_751472 |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 87 | select TEGRA_ARMV7_COMMON |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 88 | |
| 89 | config TEGRA114 |
| 90 | bool "Tegra114 family" |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 91 | select TEGRA_ARMV7_COMMON |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 92 | |
| 93 | config TEGRA124 |
| 94 | bool "Tegra124 family" |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 95 | select TEGRA_ARMV7_COMMON |
Simon Glass | 66de3ee | 2017-07-25 08:29:58 -0600 | [diff] [blame] | 96 | imply REGMAP |
| 97 | imply SYSCON |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 98 | |
Tom Warren | 7aaa5a6 | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 99 | config TEGRA210 |
| 100 | bool "Tegra210 family" |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 101 | select TEGRA_ARMV8_COMMON |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame^] | 102 | select TEGRA_GPIO |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 103 | select TEGRA_NO_BPMP |
Tom Warren | 7aaa5a6 | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 104 | |
Stephen Warren | c7ba99c | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 105 | config TEGRA186 |
| 106 | bool "Tegra186 family" |
Stephen Warren | 0f67e23 | 2016-06-17 09:43:57 -0600 | [diff] [blame] | 107 | select DM_MAILBOX |
Stephen Warren | 73dd5c4 | 2016-08-08 09:41:34 -0600 | [diff] [blame] | 108 | select TEGRA186_BPMP |
Stephen Warren | d9fd700 | 2016-08-08 11:28:24 -0600 | [diff] [blame] | 109 | select TEGRA186_CLOCK |
Stephen Warren | c7ba99c | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 110 | select TEGRA186_GPIO |
Stephen Warren | 4dd99d1 | 2016-08-08 11:28:25 -0600 | [diff] [blame] | 111 | select TEGRA186_RESET |
Stephen Warren | c7ba99c | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 112 | select TEGRA_ARMV8_COMMON |
Stephen Warren | 0f67e23 | 2016-06-17 09:43:57 -0600 | [diff] [blame] | 113 | select TEGRA_HSP |
Stephen Warren | 49626ea | 2016-07-18 12:17:11 -0600 | [diff] [blame] | 114 | select TEGRA_IVC |
Stephen Warren | c7ba99c | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 115 | |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 116 | endchoice |
| 117 | |
Stephen Warren | dd8204d | 2016-01-26 10:59:42 -0700 | [diff] [blame] | 118 | config TEGRA_DISCONNECT_UDC_ON_BOOT |
| 119 | bool "Disconnect USB device mode controller on boot" |
| 120 | default y |
| 121 | help |
| 122 | When loading U-Boot into RAM over USB protocols using tools such as |
| 123 | tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device |
| 124 | mode controller is initialized and enumerated by the host PC running |
| 125 | the tool. Unfortunately, these tools do not shut down the USB |
| 126 | controller before executing the downloaded code, and so the host PC |
| 127 | does not "de-enumerate" the USB device. This option shuts down the |
| 128 | USB controller when U-Boot boots to avoid leaving a stale USB device |
| 129 | present. |
| 130 | |
Simon Glass | b724bd7 | 2015-02-11 16:32:59 -0700 | [diff] [blame] | 131 | config SYS_MALLOC_F_LEN |
| 132 | default 0x1800 |
| 133 | |
Masahiro Yamada | 09f455d | 2015-02-20 17:04:04 +0900 | [diff] [blame] | 134 | source "arch/arm/mach-tegra/tegra20/Kconfig" |
| 135 | source "arch/arm/mach-tegra/tegra30/Kconfig" |
| 136 | source "arch/arm/mach-tegra/tegra114/Kconfig" |
| 137 | source "arch/arm/mach-tegra/tegra124/Kconfig" |
Tom Warren | 7aaa5a6 | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 138 | source "arch/arm/mach-tegra/tegra210/Kconfig" |
Stephen Warren | c7ba99c | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 139 | source "arch/arm/mach-tegra/tegra186/Kconfig" |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 140 | |
Simon Glass | 42e6f85 | 2017-05-17 03:25:11 -0600 | [diff] [blame] | 141 | config CMD_ENTERRCM |
| 142 | bool "Enable 'enterrcm' command" |
| 143 | default y |
| 144 | help |
| 145 | Tegra's boot ROM supports a mode whereby code may be downloaded and |
| 146 | flash-programmed over a USB connection. On dev boards, this is |
| 147 | typically entered by holding down a "force recovery" button and |
| 148 | resetting the CPU. However, not all boards have such a button (one |
| 149 | example is the Compulab Trimslice), so a method to enter RCM from |
| 150 | software is useful. |
| 151 | |
| 152 | Even on boards other than Trimslice, controlling this over a UART |
| 153 | may be useful, e.g. to allow simple remote control without the need |
| 154 | for mechanical button actuators, or hooking up relays/... to the |
| 155 | button. |
| 156 | |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 157 | endif |