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wdenkf12e5682003-07-07 20:07:54 +00001/*
Wolfgang Denk29f8f582008-08-09 23:17:32 +02002 * (C) Copyright 2000-2008
wdenkf12e5682003-07-07 20:07:54 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */
38
Wolfgang Denk2ae18242010-10-06 09:05:45 +020039#define CONFIG_SYS_TEXT_BASE 0x40000000
40
wdenkf12e5682003-07-07 20:07:54 +000041#ifdef CONFIG_LCD /* with LCD controller ? */
wdenkfd3103b2003-11-25 16:55:19 +000042/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */
wdenkf12e5682003-07-07 20:07:54 +000043#endif
44
45#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020046#define CONFIG_SYS_SMC_RXBUFLEN 128
47#define CONFIG_SYS_MAXIDLE 10
wdenkf12e5682003-07-07 20:07:54 +000048#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
wdenkf12e5682003-07-07 20:07:54 +000049
wdenkae3af052003-08-07 22:18:11 +000050#define CONFIG_BOOTCOUNT_LIMIT
51
52#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf12e5682003-07-07 20:07:54 +000053
54#define CONFIG_BOARD_TYPES 1 /* support board types */
55
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010056#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenkf12e5682003-07-07 20:07:54 +000057
58#undef CONFIG_BOOTARGS
59
60#define CONFIG_EXTRA_ENV_SETTINGS \
61 "netdev=eth0\0" \
62 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010063 "nfsroot=${serverip}:${rootpath}\0" \
wdenkf12e5682003-07-07 20:07:54 +000064 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010065 "addip=setenv bootargs ${bootargs} " \
66 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
67 ":${hostname}:${netdev}:off panic=1\0" \
wdenkf12e5682003-07-07 20:07:54 +000068 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010069 "bootm ${kernel_addr}\0" \
wdenkf12e5682003-07-07 20:07:54 +000070 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010071 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
72 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkf12e5682003-07-07 20:07:54 +000073 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020074 "hostname=TQM823M\0" \
75 "bootfile=TQM823M/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020076 "fdt_addr=40080000\0" \
77 "kernel_addr=400A0000\0" \
78 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020079 "u-boot=TQM823M/u-image.bin\0" \
80 "load=tftp 200000 ${u-boot}\0" \
81 "update=prot off 40000000 +${filesize};" \
82 "era 40000000 +${filesize};" \
83 "cp.b 200000 40000000 ${filesize};" \
84 "sete filesize;save\0" \
wdenkf12e5682003-07-07 20:07:54 +000085 ""
86#define CONFIG_BOOTCOMMAND "run flash_self"
87
88#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf12e5682003-07-07 20:07:54 +000090
91#undef CONFIG_WATCHDOG /* watchdog disabled */
92
93#ifdef CONFIG_LCD
94# undef CONFIG_STATUS_LED /* disturbs display */
95#else
96# define CONFIG_STATUS_LED 1 /* Status LED enabled */
97#endif /* CONFIG_LCD */
98
99#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
100
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500101/*
102 * BOOTP options
103 */
104#define CONFIG_BOOTP_SUBNETMASK
105#define CONFIG_BOOTP_GATEWAY
106#define CONFIG_BOOTP_HOSTNAME
107#define CONFIG_BOOTP_BOOTPATH
108#define CONFIG_BOOTP_BOOTFILESIZE
109
wdenkf12e5682003-07-07 20:07:54 +0000110
111#define CONFIG_MAC_PARTITION
112#define CONFIG_DOS_PARTITION
113
114#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
115
wdenkf12e5682003-07-07 20:07:54 +0000116
Jon Loeliger26946902007-07-04 22:30:50 -0500117/*
118 * Command line configuration.
119 */
120#include <config_cmd_default.h>
121
122#define CONFIG_CMD_ASKENV
123#define CONFIG_CMD_DATE
124#define CONFIG_CMD_DHCP
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200125#define CONFIG_CMD_ELF
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100126#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500127#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200128#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500129#define CONFIG_CMD_NFS
130#define CONFIG_CMD_SNTP
131
wdenkf12e5682003-07-07 20:07:54 +0000132
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200133#define CONFIG_NETCONSOLE
134
135
wdenkf12e5682003-07-07 20:07:54 +0000136/*
137 * Miscellaneous configurable options
138 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_LONGHELP /* undef to save memory */
140#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkf12e5682003-07-07 20:07:54 +0000141
Wolfgang Denk2751a952006-10-28 02:29:14 +0200142#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
144#ifdef CONFIG_SYS_HUSH_PARSER
145#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkf12e5682003-07-07 20:07:54 +0000146#endif
147
Jon Loeliger26946902007-07-04 22:30:50 -0500148#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000150#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000152#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
154#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
155#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
158#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf12e5682003-07-07 20:07:54 +0000159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf12e5682003-07-07 20:07:54 +0000161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkf12e5682003-07-07 20:07:54 +0000163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkf12e5682003-07-07 20:07:54 +0000165
166/*
167 * Low Level Configuration Settings
168 * (address mappings, register initial values, etc.)
169 * You should know what you are doing if you make changes here.
170 */
171/*-----------------------------------------------------------------------
172 * Internal Memory Mapped Register
173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf12e5682003-07-07 20:07:54 +0000175
176/*-----------------------------------------------------------------------
177 * Definitions for initial stack pointer and data area (in DPRAM)
178 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200180#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200181#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf12e5682003-07-07 20:07:54 +0000183
184/*-----------------------------------------------------------------------
185 * Start addresses for the final memory configuration
186 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf12e5682003-07-07 20:07:54 +0000188 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_SDRAM_BASE 0x00000000
190#define CONFIG_SYS_FLASH_BASE 0x40000000
191#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
192#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
193#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf12e5682003-07-07 20:07:54 +0000194
195/*
196 * For booting Linux, the board info and command line data
197 * have to be in the first 8 MB of memory, since this is
198 * the maximum mapped by the Linux kernel during initialization.
199 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf12e5682003-07-07 20:07:54 +0000201
202/*-----------------------------------------------------------------------
203 * FLASH organization
204 */
wdenkf12e5682003-07-07 20:07:54 +0000205
Martin Krausee318d9e2007-09-27 11:10:08 +0200206/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200208#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
210#define CONFIG_SYS_FLASH_EMPTY_INFO
211#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
212#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
213#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkf12e5682003-07-07 20:07:54 +0000214
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200215#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200216#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
217#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
218#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
wdenkf12e5682003-07-07 20:07:54 +0000219
220/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200221#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
222#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf12e5682003-07-07 20:07:54 +0000223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200225
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200226#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
227
wdenkf12e5682003-07-07 20:07:54 +0000228/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200229 * Dynamic MTD partition support
230 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100231#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200232#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
233#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200234#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
235
236#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
237 "128k(dtb)," \
238 "1920k(kernel)," \
239 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200240 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200241
242/*-----------------------------------------------------------------------
wdenkf12e5682003-07-07 20:07:54 +0000243 * Hardware Information Block
244 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
246#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
247#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf12e5682003-07-07 20:07:54 +0000248
249/*-----------------------------------------------------------------------
250 * Cache Configuration
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500253#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf12e5682003-07-07 20:07:54 +0000255#endif
256
257/*-----------------------------------------------------------------------
258 * SYPCR - System Protection Control 11-9
259 * SYPCR can only be written once after reset!
260 *-----------------------------------------------------------------------
261 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
262 */
263#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf12e5682003-07-07 20:07:54 +0000265 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
266#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf12e5682003-07-07 20:07:54 +0000268#endif
269
270/*-----------------------------------------------------------------------
271 * SIUMCR - SIU Module Configuration 11-6
272 *-----------------------------------------------------------------------
273 * PCMCIA config., multi-function pin tri-state
274 */
275#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000277#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000279#endif /* CONFIG_CAN_DRIVER */
280
281/*-----------------------------------------------------------------------
282 * TBSCR - Time Base Status and Control 11-26
283 *-----------------------------------------------------------------------
284 * Clear Reference Interrupt Status, Timebase freezing enabled
285 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf12e5682003-07-07 20:07:54 +0000287
288/*-----------------------------------------------------------------------
289 * RTCSC - Real-Time Clock Status and Control Register 11-27
290 *-----------------------------------------------------------------------
291 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf12e5682003-07-07 20:07:54 +0000293
294/*-----------------------------------------------------------------------
295 * PISCR - Periodic Interrupt Status and Control 11-31
296 *-----------------------------------------------------------------------
297 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
298 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf12e5682003-07-07 20:07:54 +0000300
301/*-----------------------------------------------------------------------
302 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
303 *-----------------------------------------------------------------------
304 * Reset PLL lock status sticky bit, timer expired status bit and timer
305 * interrupt status bit
wdenkf12e5682003-07-07 20:07:54 +0000306 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf12e5682003-07-07 20:07:54 +0000308
309/*-----------------------------------------------------------------------
310 * SCCR - System Clock and reset Control Register 15-27
311 *-----------------------------------------------------------------------
312 * Set clock output, timebase and RTC source and divider,
313 * power management and some other internal clocks
314 */
315#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf12e5682003-07-07 20:07:54 +0000317 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
318 SCCR_DFALCD00)
wdenkf12e5682003-07-07 20:07:54 +0000319
320/*-----------------------------------------------------------------------
321 * PCMCIA stuff
322 *-----------------------------------------------------------------------
323 *
324 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
326#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
327#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
328#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
329#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
330#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
331#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
332#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf12e5682003-07-07 20:07:54 +0000333
334/*-----------------------------------------------------------------------
335 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
336 *-----------------------------------------------------------------------
337 */
338
339#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
340
341#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
342#undef CONFIG_IDE_LED /* LED for ide not supported */
343#undef CONFIG_IDE_RESET /* reset for ide not supported */
344
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
346#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf12e5682003-07-07 20:07:54 +0000347
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf12e5682003-07-07 20:07:54 +0000349
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf12e5682003-07-07 20:07:54 +0000351
352/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000354
355/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000357
358/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf12e5682003-07-07 20:07:54 +0000360
361/*-----------------------------------------------------------------------
362 *
363 *-----------------------------------------------------------------------
364 *
365 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_DER 0
wdenkf12e5682003-07-07 20:07:54 +0000367
368/*
369 * Init Memory Controller:
370 *
371 * BR0/1 and OR0/1 (FLASH)
372 */
373
374#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
375#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
376
377/* used to re-map FLASH both when starting from SRAM or FLASH:
378 * restrict access enough to keep SRAM working (if any)
379 * but not too much to meddle with FLASH accesses
380 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
382#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf12e5682003-07-07 20:07:54 +0000383
384/*
385 * FLASH timing:
386 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf12e5682003-07-07 20:07:54 +0000388 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf12e5682003-07-07 20:07:54 +0000389
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
391#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
392#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000393
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
395#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
396#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000397
398/*
399 * BR2/3 and OR2/3 (SDRAM)
400 *
401 */
402#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
403#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
404#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
405
406/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf12e5682003-07-07 20:07:54 +0000408
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
410#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000411
412#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
414#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000415#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
417#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
418#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
419#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf12e5682003-07-07 20:07:54 +0000420 BR_PS_8 | BR_MS_UPMB | BR_V )
421#endif /* CONFIG_CAN_DRIVER */
422
423/*
424 * Memory Periodic Timer Prescaler
425 *
426 * The Divider for PTA (refresh timer) configuration is based on an
427 * example SDRAM configuration (64 MBit, one bank). The adjustment to
428 * the number of chip selects (NCS) and the actually needed refresh
429 * rate is done by setting MPTPR.
430 *
431 * PTA is calculated from
432 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
433 *
434 * gclk CPU clock (not bus clock!)
435 * Trefresh Refresh cycle * 4 (four word bursts used)
436 *
437 * 4096 Rows from SDRAM example configuration
438 * 1000 factor s -> ms
439 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
440 * 4 Number of refresh cycles per period
441 * 64 Refresh cycle in ms per number of rows
442 * --------------------------------------------
443 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
444 *
445 * 50 MHz => 50.000.000 / Divider = 98
446 * 66 Mhz => 66.000.000 / Divider = 129
447 * 80 Mhz => 80.000.000 / Divider = 156
448 */
wdenke9132ea2004-04-24 23:23:30 +0000449
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
451#define CONFIG_SYS_MAMR_PTA 98
wdenkf12e5682003-07-07 20:07:54 +0000452
453/*
454 * For 16 MBit, refresh rates could be 31.3 us
455 * (= 64 ms / 2K = 125 / quad bursts).
456 * For a simpler initialization, 15.6 us is used instead.
457 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
459 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf12e5682003-07-07 20:07:54 +0000460 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
462#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000463
464/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
466#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000467
468/*
469 * MAMR settings for SDRAM
470 */
471
472/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000474 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
475 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
476/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000478 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
479 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
480
Heiko Schocher7026ead2010-02-09 15:50:27 +0100481/* pass open firmware flat tree */
482#define CONFIG_OF_LIBFDT 1
483#define CONFIG_OF_BOARD_SETUP 1
484#define CONFIG_HWCONFIG 1
485
wdenkf12e5682003-07-07 20:07:54 +0000486#endif /* __CONFIG_H */