| TsiChungLiew | 48dbfea | 2007-07-05 22:39:07 -0500 | [diff] [blame] | 1 | /* |
| 2 | * ColdFire Internal Memory Map and Defines |
| 3 | * |
| 4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
| 5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 6 | * |
| 7 | * See file CREDITS for list of people who contributed to this |
| 8 | * project. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
| 26 | #ifndef __IMMAP_H |
| 27 | #define __IMMAP_H |
| Stefan Roese | c883f6e | 2007-07-16 13:11:12 +0200 | [diff] [blame] | 28 | |
| TsiChungLiew | 1552af7 | 2008-01-14 17:43:33 -0600 | [diff] [blame] | 29 | #ifdef CONFIG_M52277 |
| 30 | #include <asm/immap_5227x.h> |
| 31 | #include <asm/m5227x.h> |
| 32 | |
| 33 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) |
| 34 | |
| 35 | #define CFG_MCFRTC_BASE (MMAP_RTC) |
| 36 | |
| 37 | #ifdef CONFIG_LCD |
| 38 | #define CFG_LCD_BASE (MMAP_LCD) |
| 39 | #endif |
| 40 | |
| 41 | /* Timer */ |
| 42 | #ifdef CONFIG_MCFTMR |
| 43 | #define CFG_UDELAY_BASE (MMAP_DTMR0) |
| 44 | #define CFG_TMR_BASE (MMAP_DTMR1) |
| 45 | #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) |
| 46 | #define CFG_TMRINTR_NO (INT0_HI_DTMR1) |
| 47 | #define CFG_TMRINTR_MASK (INTC_IPRH_INT33) |
| 48 | #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) |
| 49 | #define CFG_TMRINTR_PRI (6) |
| 50 | #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
| 51 | #endif |
| 52 | |
| 53 | #ifdef CONFIG_MCFPIT |
| 54 | #define CFG_UDELAY_BASE (MMAP_PIT0) |
| 55 | #define CFG_PIT_BASE (MMAP_PIT1) |
| 56 | #define CFG_PIT_PRESCALE (6) |
| 57 | #endif |
| 58 | |
| 59 | #define CFG_INTR_BASE (MMAP_INTC0) |
| 60 | #define CFG_NUM_IRQS (128) |
| 61 | #endif /* CONFIG_M52277 */ |
| 62 | |
| TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 63 | #ifdef CONFIG_M5235 |
| 64 | #include <asm/immap_5235.h> |
| 65 | #include <asm/m5235.h> |
| 66 | |
| 67 | #define CFG_FEC0_IOBASE (MMAP_FEC) |
| 68 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) |
| 69 | |
| 70 | /* Timer */ |
| 71 | #ifdef CONFIG_MCFTMR |
| 72 | #define CFG_UDELAY_BASE (MMAP_DTMR0) |
| 73 | #define CFG_TMR_BASE (MMAP_DTMR3) |
| 74 | #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) |
| 75 | #define CFG_TMRINTR_NO (INT0_LO_DTMR3) |
| 76 | #define CFG_TMRINTR_MASK (INTC_IPRL_INT22) |
| 77 | #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) |
| 78 | #define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ |
| 79 | #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
| 80 | #endif |
| 81 | |
| 82 | #ifdef CONFIG_MCFPIT |
| 83 | #define CFG_UDELAY_BASE (MMAP_PIT0) |
| 84 | #define CFG_PIT_BASE (MMAP_PIT1) |
| 85 | #define CFG_PIT_PRESCALE (6) |
| 86 | #endif |
| 87 | |
| 88 | #define CFG_INTR_BASE (MMAP_INTC0) |
| 89 | #define CFG_NUM_IRQS (128) |
| 90 | #endif /* CONFIG_M5235 */ |
| 91 | |
| TsiChungLiew | 5611566 | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 92 | #ifdef CONFIG_M5249 |
| 93 | #include <asm/immap_5249.h> |
| 94 | #include <asm/m5249.h> |
| 95 | |
| 96 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) |
| 97 | |
| 98 | #define CFG_INTR_BASE (MMAP_INTC) |
| 99 | #define CFG_NUM_IRQS (64) |
| 100 | |
| 101 | /* Timer */ |
| 102 | #ifdef CONFIG_MCFTMR |
| 103 | #define CFG_UDELAY_BASE (MMAP_DTMR0) |
| 104 | #define CFG_TMR_BASE (MMAP_DTMR1) |
| 105 | #define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) |
| 106 | #define CFG_TMRINTR_NO (31) |
| 107 | #define CFG_TMRINTR_MASK (0x00000400) |
| 108 | #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) |
| TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 109 | #define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) |
| TsiChungLiew | 5611566 | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 110 | #define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) |
| 111 | #endif |
| 112 | #endif /* CONFIG_M5249 */ |
| 113 | |
| TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 114 | #ifdef CONFIG_M5253 |
| 115 | #include <asm/immap_5253.h> |
| 116 | #include <asm/m5249.h> |
| 117 | #include <asm/m5253.h> |
| 118 | |
| 119 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) |
| 120 | |
| 121 | #define CFG_INTR_BASE (MMAP_INTC) |
| 122 | #define CFG_NUM_IRQS (64) |
| 123 | |
| 124 | /* Timer */ |
| 125 | #ifdef CONFIG_MCFTMR |
| 126 | #define CFG_UDELAY_BASE (MMAP_DTMR0) |
| 127 | #define CFG_TMR_BASE (MMAP_DTMR1) |
| 128 | #define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) |
| 129 | #define CFG_TMRINTR_NO (27) |
| 130 | #define CFG_TMRINTR_MASK (0x00000400) |
| 131 | #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) |
| 132 | #define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3) |
| 133 | #define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) |
| 134 | #endif |
| 135 | #endif /* CONFIG_M5253 */ |
| 136 | |
| TsiChungLiew | 5611566 | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 137 | #ifdef CONFIG_M5271 |
| 138 | #include <asm/immap_5271.h> |
| 139 | #include <asm/m5271.h> |
| 140 | |
| 141 | #define CFG_FEC0_IOBASE (MMAP_FEC) |
| 142 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) |
| 143 | |
| 144 | /* Timer */ |
| 145 | #ifdef CONFIG_MCFTMR |
| 146 | #define CFG_UDELAY_BASE (MMAP_DTMR0) |
| 147 | #define CFG_TMR_BASE (MMAP_DTMR3) |
| 148 | #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) |
| 149 | #define CFG_TMRINTR_NO (INT0_LO_DTMR3) |
| 150 | #define CFG_TMRINTR_MASK (INTC_IPRL_INT22) |
| 151 | #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) |
| 152 | #define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */ |
| 153 | #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
| 154 | #endif |
| 155 | |
| 156 | #define CFG_INTR_BASE (MMAP_INTC0) |
| 157 | #define CFG_NUM_IRQS (128) |
| 158 | #endif /* CONFIG_M5271 */ |
| 159 | |
| 160 | #ifdef CONFIG_M5272 |
| 161 | #include <asm/immap_5272.h> |
| 162 | #include <asm/m5272.h> |
| 163 | |
| 164 | #define CFG_FEC0_IOBASE (MMAP_FEC) |
| 165 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) |
| 166 | |
| 167 | #define CFG_INTR_BASE (MMAP_INTC) |
| 168 | #define CFG_NUM_IRQS (64) |
| 169 | |
| 170 | /* Timer */ |
| 171 | #ifdef CONFIG_MCFTMR |
| 172 | #define CFG_UDELAY_BASE (MMAP_TMR0) |
| 173 | #define CFG_TMR_BASE (MMAP_TMR3) |
| 174 | #define CFG_TMRPND_REG (((volatile intctrl_t *)(CFG_INTR_BASE))->int_isr) |
| 175 | #define CFG_TMRINTR_NO (INT_TMR3) |
| 176 | #define CFG_TMRINTR_MASK (INT_ISR_INT24) |
| 177 | #define CFG_TMRINTR_PEND (0) |
| 178 | #define CFG_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5)) |
| 179 | #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
| 180 | #endif |
| 181 | #endif /* CONFIG_M5272 */ |
| 182 | |
| 183 | #ifdef CONFIG_M5282 |
| 184 | #include <asm/immap_5282.h> |
| 185 | #include <asm/m5282.h> |
| 186 | |
| 187 | #define CFG_FEC0_IOBASE (MMAP_FEC) |
| 188 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) |
| 189 | |
| 190 | #define CFG_INTR_BASE (MMAP_INTC0) |
| 191 | #define CFG_NUM_IRQS (128) |
| 192 | |
| 193 | /* Timer */ |
| 194 | #ifdef CONFIG_MCFTMR |
| 195 | #define CFG_UDELAY_BASE (MMAP_DTMR0) |
| 196 | #define CFG_TMR_BASE (MMAP_DTMR3) |
| 197 | #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) |
| 198 | #define CFG_TMRINTR_NO (INT0_LO_DTMR3) |
| 199 | #define CFG_TMRINTR_MASK (1 << INT0_LO_DTMR3) |
| 200 | #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) |
| 201 | #define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ |
| 202 | #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
| 203 | #endif |
| 204 | #endif /* CONFIG_M5282 */ |
| 205 | |
| TsiChungLiew | aa5f1f9 | 2008-01-14 17:23:08 -0600 | [diff] [blame] | 206 | #if defined(CONFIG_M5329) || defined(CONFIG_M5373) |
| TsiChungLiew | 48dbfea | 2007-07-05 22:39:07 -0500 | [diff] [blame] | 207 | #include <asm/immap_5329.h> |
| 208 | #include <asm/m5329.h> |
| 209 | |
| 210 | #define CFG_FEC0_IOBASE (MMAP_FEC) |
| 211 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) |
| 212 | #define CFG_MCFRTC_BASE (MMAP_RTC) |
| 213 | |
| 214 | /* Timer */ |
| 215 | #ifdef CONFIG_MCFTMR |
| 216 | #define CFG_UDELAY_BASE (MMAP_DTMR0) |
| 217 | #define CFG_TMR_BASE (MMAP_DTMR1) |
| TsiChungLiew | ab77bc5 | 2007-08-15 15:39:17 -0500 | [diff] [blame] | 218 | #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) |
| TsiChungLiew | 48dbfea | 2007-07-05 22:39:07 -0500 | [diff] [blame] | 219 | #define CFG_TMRINTR_NO (INT0_HI_DTMR1) |
| 220 | #define CFG_TMRINTR_MASK (INTC_IPRH_INT33) |
| TsiChungLiew | ab77bc5 | 2007-08-15 15:39:17 -0500 | [diff] [blame] | 221 | #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) |
| TsiChungLiew | 48dbfea | 2007-07-05 22:39:07 -0500 | [diff] [blame] | 222 | #define CFG_TMRINTR_PRI (6) |
| TsiChungLiew | 99c03c1 | 2007-08-05 03:58:52 -0500 | [diff] [blame] | 223 | #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
| TsiChungLiew | 48dbfea | 2007-07-05 22:39:07 -0500 | [diff] [blame] | 224 | #endif |
| 225 | |
| 226 | #ifdef CONFIG_MCFPIT |
| 227 | #define CFG_UDELAY_BASE (MMAP_PIT0) |
| 228 | #define CFG_PIT_BASE (MMAP_PIT1) |
| 229 | #define CFG_PIT_PRESCALE (6) |
| 230 | #endif |
| 231 | |
| 232 | #define CFG_INTR_BASE (MMAP_INTC0) |
| 233 | #define CFG_NUM_IRQS (128) |
| TsiChungLiew | aa5f1f9 | 2008-01-14 17:23:08 -0600 | [diff] [blame] | 234 | #endif /* CONFIG_M5329 && CONFIG_M5373 */ |
| Stefan Roese | c883f6e | 2007-07-16 13:11:12 +0200 | [diff] [blame] | 235 | |
| TsiChungLiew | 8ae158c | 2007-08-16 15:05:11 -0500 | [diff] [blame] | 236 | #ifdef CONFIG_M54455 |
| 237 | #include <asm/immap_5445x.h> |
| 238 | #include <asm/m5445x.h> |
| 239 | |
| 240 | #define CFG_FEC0_IOBASE (MMAP_FEC0) |
| 241 | #define CFG_FEC1_IOBASE (MMAP_FEC1) |
| 242 | |
| 243 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) |
| 244 | |
| 245 | #define CFG_MCFRTC_BASE (MMAP_RTC) |
| 246 | |
| 247 | /* Timer */ |
| 248 | #ifdef CONFIG_MCFTMR |
| 249 | #define CFG_UDELAY_BASE (MMAP_DTMR0) |
| 250 | #define CFG_TMR_BASE (MMAP_DTMR1) |
| 251 | #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) |
| 252 | #define CFG_TMRINTR_NO (INT0_HI_DTMR1) |
| 253 | #define CFG_TMRINTR_MASK (INTC_IPRH_INT33) |
| 254 | #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) |
| 255 | #define CFG_TMRINTR_PRI (6) |
| 256 | #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
| 257 | #endif |
| 258 | |
| 259 | #ifdef CONFIG_MCFPIT |
| 260 | #define CFG_UDELAY_BASE (MMAP_PIT0) |
| 261 | #define CFG_PIT_BASE (MMAP_PIT1) |
| 262 | #define CFG_PIT_PRESCALE (6) |
| 263 | #endif |
| 264 | |
| 265 | #define CFG_INTR_BASE (MMAP_INTC0) |
| 266 | #define CFG_NUM_IRQS (128) |
| 267 | |
| 268 | #ifdef CONFIG_PCI |
| TsiChungLiew | 2e72ad0 | 2008-01-14 17:11:47 -0600 | [diff] [blame] | 269 | #define CFG_PCI_BAR0 (CFG_MBAR) |
| 270 | #define CFG_PCI_BAR5 (CFG_SDRAM_BASE) |
| 271 | #define CFG_PCI_TBATR0 (CFG_MBAR) |
| 272 | #define CFG_PCI_TBATR5 (CFG_SDRAM_BASE) |
| TsiChungLiew | 8ae158c | 2007-08-16 15:05:11 -0500 | [diff] [blame] | 273 | #endif |
| 274 | #endif /* CONFIG_M54455 */ |
| 275 | |
| TsiChungLiew | 4621fc3 | 2008-01-15 13:39:44 -0600 | [diff] [blame] | 276 | #ifdef CONFIG_M547x |
| 277 | #include <asm/immap_547x_8x.h> |
| 278 | #include <asm/m547x_8x.h> |
| 279 | |
| 280 | #ifdef CONFIG_FSLDMAFEC |
| 281 | #define CFG_FEC0_IOBASE (MMAP_FEC0) |
| 282 | #define CFG_FEC1_IOBASE (MMAP_FEC1) |
| 283 | |
| 284 | #define FEC0_RX_TASK 0 |
| 285 | #define FEC0_TX_TASK 1 |
| 286 | #define FEC0_RX_PRIORITY 6 |
| 287 | #define FEC0_TX_PRIORITY 7 |
| 288 | #define FEC0_RX_INIT 16 |
| 289 | #define FEC0_TX_INIT 17 |
| 290 | #define FEC1_RX_TASK 2 |
| 291 | #define FEC1_TX_TASK 3 |
| 292 | #define FEC1_RX_PRIORITY 6 |
| 293 | #define FEC1_TX_PRIORITY 7 |
| 294 | #define FEC1_RX_INIT 30 |
| 295 | #define FEC1_TX_INIT 31 |
| 296 | #endif |
| 297 | |
| 298 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x100)) |
| 299 | |
| 300 | #ifdef CONFIG_SLTTMR |
| 301 | #define CFG_UDELAY_BASE (MMAP_SLT1) |
| 302 | #define CFG_TMR_BASE (MMAP_SLT0) |
| 303 | #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) |
| 304 | #define CFG_TMRINTR_NO (INT0_HI_SLT0) |
| 305 | #define CFG_TMRINTR_MASK (INTC_IPRH_INT54) |
| 306 | #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) |
| 307 | #define CFG_TMRINTR_PRI (0x1E) |
| 308 | #define CFG_TIMER_PRESCALER (gd->bus_clk / 1000000) |
| 309 | #endif |
| 310 | |
| 311 | #define CFG_INTR_BASE (MMAP_INTC0) |
| 312 | #define CFG_NUM_IRQS (128) |
| 313 | |
| 314 | #ifdef CONFIG_PCI |
| 315 | #define CFG_PCI_BAR0 (0x40000000) |
| 316 | #define CFG_PCI_BAR1 (CFG_SDRAM_BASE) |
| 317 | #define CFG_PCI_TBATR0 (CFG_MBAR) |
| 318 | #define CFG_PCI_TBATR1 (CFG_SDRAM_BASE) |
| 319 | #endif |
| 320 | #endif /* CONFIG_M547x */ |
| 321 | |
| 322 | #ifdef CONFIG_M548x |
| 323 | #include <asm/immap_547x_8x.h> |
| 324 | #include <asm/m547x_8x.h> |
| 325 | |
| 326 | #ifdef CONFIG_FSLDMAFEC |
| 327 | #define CFG_FEC0_IOBASE (MMAP_FEC0) |
| 328 | #define CFG_FEC1_IOBASE (MMAP_FEC1) |
| 329 | |
| 330 | #define FEC0_RX_TASK 0 |
| 331 | #define FEC0_TX_TASK 1 |
| 332 | #define FEC0_RX_PRIORITY 6 |
| 333 | #define FEC0_TX_PRIORITY 7 |
| 334 | #define FEC0_RX_INIT 16 |
| 335 | #define FEC0_TX_INIT 17 |
| 336 | #define FEC1_RX_TASK 2 |
| 337 | #define FEC1_TX_TASK 3 |
| 338 | #define FEC1_RX_PRIORITY 6 |
| 339 | #define FEC1_TX_PRIORITY 7 |
| 340 | #define FEC1_RX_INIT 30 |
| 341 | #define FEC1_TX_INIT 31 |
| 342 | #endif |
| 343 | |
| 344 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x100)) |
| 345 | |
| 346 | /* Timer */ |
| 347 | #ifdef CONFIG_SLTTMR |
| 348 | #define CFG_UDELAY_BASE (MMAP_SLT1) |
| 349 | #define CFG_TMR_BASE (MMAP_SLT0) |
| 350 | #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) |
| 351 | #define CFG_TMRINTR_NO (INT0_HI_SLT0) |
| 352 | #define CFG_TMRINTR_MASK (INTC_IPRH_INT54) |
| 353 | #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) |
| 354 | #define CFG_TMRINTR_PRI (0x1E) |
| 355 | #define CFG_TIMER_PRESCALER (gd->bus_clk / 1000000) |
| 356 | #endif |
| 357 | |
| 358 | #define CFG_INTR_BASE (MMAP_INTC0) |
| 359 | #define CFG_NUM_IRQS (128) |
| 360 | |
| 361 | #ifdef CONFIG_PCI |
| 362 | #define CFG_PCI_BAR0 (CFG_MBAR) |
| 363 | #define CFG_PCI_BAR1 (CFG_SDRAM_BASE) |
| 364 | #define CFG_PCI_TBATR0 (CFG_MBAR) |
| 365 | #define CFG_PCI_TBATR1 (CFG_SDRAM_BASE) |
| 366 | #endif |
| 367 | #endif /* CONFIG_M548x */ |
| 368 | |
| TsiChungLiew | 48dbfea | 2007-07-05 22:39:07 -0500 | [diff] [blame] | 369 | #endif /* __IMMAP_H */ |