blob: 5f89d9b125e105d71aa2e968cba8459cc28f2983 [file] [log] [blame]
wdenkf8cac652002-08-26 22:36:39 +00001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
25#include <common.h>
26#include <asm/io.h>
27
28#include "fpga_serial.h"
29#include "hardware.h"
30#include "pcippc2.h"
31
Wolfgang Denkd87080b2006-03-31 18:32:53 +020032DECLARE_GLOBAL_DATA_PTR;
33
wdenkf8cac652002-08-26 22:36:39 +000034 /* 8 data, 1 stop, no parity
35 */
36#define LCRVAL 0x03
37 /* RTS/DTR
38 */
39#define MCRVAL 0x03
40 /* Clear & enable FIFOs
41 */
42#define FCRVAL 0x07
43
44static void fpga_serial_wait (void);
45static void fpga_serial_print (char c);
46
47void fpga_serial_init (int baudrate)
48{
49 int clock_divisor = 115200 / baudrate;
50
51 out8 (FPGA (INT, SERIAL_CONFIG), 0x24);
52 iobarrier_rw ();
53
54 fpga_serial_wait ();
55
56 out8 (UART (IER), 0);
57 out8 (UART (LCR), LCRVAL | 0x80);
58 iobarrier_rw ();
59 out8 (UART (DLL), clock_divisor & 0xff);
60 out8 (UART (DLM), clock_divisor >> 8);
61 iobarrier_rw ();
62 out8 (UART (LCR), LCRVAL);
63 iobarrier_rw ();
64 out8 (UART (MCR), MCRVAL);
65 out8 (UART (FCR), FCRVAL);
66 iobarrier_rw ();
67}
68
69void fpga_serial_putc (char c)
70{
71 if (c) {
72 fpga_serial_print (c);
73 }
74}
75
76void fpga_serial_puts (const char *s)
77{
78 while (*s) {
79 fpga_serial_print (*s++);
80 }
81}
82
83int fpga_serial_getc (void)
84{
85 while ((in8 (UART (LSR)) & 0x01) == 0);
86
87 return in8 (UART (RBR));
88}
89
90int fpga_serial_tstc (void)
91{
92 return (in8 (UART (LSR)) & 0x01) != 0;
93}
94
95void fpga_serial_setbrg (void)
96{
wdenkf8cac652002-08-26 22:36:39 +000097 int clock_divisor = 115200 / gd->baudrate;
98
99 fpga_serial_wait ();
100
101 out8 (UART (LCR), LCRVAL | 0x80);
102 iobarrier_rw ();
103 out8 (UART (DLL), clock_divisor & 0xff);
104 out8 (UART (DLM), clock_divisor >> 8);
105 iobarrier_rw ();
106 out8 (UART (LCR), LCRVAL);
107 iobarrier_rw ();
108}
109
110static void fpga_serial_wait (void)
111{
112 while ((in8 (UART (LSR)) & 0x40) == 0);
113}
114
115static void fpga_serial_print (char c)
116{
117 if (c == '\n') {
118 while ((in8 (UART (LSR)) & 0x20) == 0);
119
120 out8 (UART (THR), '\r');
121 iobarrier_rw ();
122 }
123
124 while ((in8 (UART (LSR)) & 0x20) == 0);
125
126 out8 (UART (THR), c);
127 iobarrier_rw ();
128
129 if (c == '\n') {
130 fpga_serial_wait ();
131 }
132}