blob: 006dd04b9e1c3601eaf558a55d08f37af2975af7 [file] [log] [blame]
Michael Walle383fded2019-12-18 00:09:58 +01001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * NXP FlexSPI(FSPI) controller driver.
4 *
5 * Copyright (c) 2019 Michael Walle <michael@walle.cc>
6 * Copyright (c) 2019 NXP
7 *
8 * This driver was originally ported from the linux kernel v5.4-rc3, which had
9 * the following notes:
10 *
11 * FlexSPI is a flexsible SPI host controller which supports two SPI
12 * channels and up to 4 external devices. Each channel supports
13 * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
14 * data lines).
15 *
16 * FlexSPI controller is driven by the LUT(Look-up Table) registers
17 * LUT registers are a look-up-table for sequences of instructions.
18 * A valid sequence consists of four LUT registers.
19 * Maximum 32 LUT sequences can be programmed simultaneously.
20 *
21 * LUTs are being created at run-time based on the commands passed
22 * from the spi-mem framework, thus using single LUT index.
23 *
24 * Software triggered Flash read/write access by IP Bus.
25 *
26 * Memory mapped read access by AHB Bus.
27 *
28 * Based on SPI MEM interface and spi-fsl-qspi.c driver.
29 *
30 * Author:
31 * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
32 * Boris Brezillon <bbrezillon@kernel.org>
33 * Frieder Schrempf <frieder.schrempf@kontron.de>
34 */
35
36#include <common.h>
Sean Anderson06aaca52020-10-04 21:39:49 -040037#include <clk.h>
38#include <dm.h>
39#include <dm/device_compat.h>
Michael Walle383fded2019-12-18 00:09:58 +010040#include <malloc.h>
41#include <spi.h>
42#include <spi-mem.h>
Sean Anderson06aaca52020-10-04 21:39:49 -040043#include <asm/io.h>
Simon Glasscd93d622020-05-10 11:40:13 -060044#include <linux/bitops.h>
Michael Walle383fded2019-12-18 00:09:58 +010045#include <linux/kernel.h>
46#include <linux/sizes.h>
47#include <linux/iopoll.h>
48#include <linux/bug.h>
Simon Glassf2176512020-02-03 07:36:17 -070049#include <linux/err.h>
Michael Walle383fded2019-12-18 00:09:58 +010050
51/*
52 * The driver only uses one single LUT entry, that is updated on
53 * each call of exec_op(). Index 0 is preset at boot with a basic
54 * read operation, so let's use the last entry (31).
55 */
56#define SEQID_LUT 31
57
58/* Registers used by the driver */
59#define FSPI_MCR0 0x00
60#define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
61#define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16)
62#define FSPI_MCR0_LEARN_EN BIT(15)
63#define FSPI_MCR0_SCRFRUN_EN BIT(14)
64#define FSPI_MCR0_OCTCOMB_EN BIT(13)
65#define FSPI_MCR0_DOZE_EN BIT(12)
66#define FSPI_MCR0_HSEN BIT(11)
67#define FSPI_MCR0_SERCLKDIV BIT(8)
68#define FSPI_MCR0_ATDF_EN BIT(7)
69#define FSPI_MCR0_ARDF_EN BIT(6)
70#define FSPI_MCR0_RXCLKSRC(x) ((x) << 4)
71#define FSPI_MCR0_END_CFG(x) ((x) << 2)
72#define FSPI_MCR0_MDIS BIT(1)
73#define FSPI_MCR0_SWRST BIT(0)
74
75#define FSPI_MCR1 0x04
76#define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16)
77#define FSPI_MCR1_AHB_TIMEOUT(x) (x)
78
79#define FSPI_MCR2 0x08
80#define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24)
81#define FSPI_MCR2_SAMEDEVICEEN BIT(15)
82#define FSPI_MCR2_CLRLRPHS BIT(14)
83#define FSPI_MCR2_ABRDATSZ BIT(8)
84#define FSPI_MCR2_ABRLEARN BIT(7)
85#define FSPI_MCR2_ABR_READ BIT(6)
86#define FSPI_MCR2_ABRWRITE BIT(5)
87#define FSPI_MCR2_ABRDUMMY BIT(4)
88#define FSPI_MCR2_ABR_MODE BIT(3)
89#define FSPI_MCR2_ABRCADDR BIT(2)
90#define FSPI_MCR2_ABRRADDR BIT(1)
91#define FSPI_MCR2_ABR_CMD BIT(0)
92
93#define FSPI_AHBCR 0x0c
94#define FSPI_AHBCR_RDADDROPT BIT(6)
95#define FSPI_AHBCR_PREF_EN BIT(5)
96#define FSPI_AHBCR_BUFF_EN BIT(4)
97#define FSPI_AHBCR_CACH_EN BIT(3)
98#define FSPI_AHBCR_CLRTXBUF BIT(2)
99#define FSPI_AHBCR_CLRRXBUF BIT(1)
100#define FSPI_AHBCR_PAR_EN BIT(0)
101
102#define FSPI_INTEN 0x10
103#define FSPI_INTEN_SCLKSBWR BIT(9)
104#define FSPI_INTEN_SCLKSBRD BIT(8)
105#define FSPI_INTEN_DATALRNFL BIT(7)
106#define FSPI_INTEN_IPTXWE BIT(6)
107#define FSPI_INTEN_IPRXWA BIT(5)
108#define FSPI_INTEN_AHBCMDERR BIT(4)
109#define FSPI_INTEN_IPCMDERR BIT(3)
110#define FSPI_INTEN_AHBCMDGE BIT(2)
111#define FSPI_INTEN_IPCMDGE BIT(1)
112#define FSPI_INTEN_IPCMDDONE BIT(0)
113
114#define FSPI_INTR 0x14
115#define FSPI_INTR_SCLKSBWR BIT(9)
116#define FSPI_INTR_SCLKSBRD BIT(8)
117#define FSPI_INTR_DATALRNFL BIT(7)
118#define FSPI_INTR_IPTXWE BIT(6)
119#define FSPI_INTR_IPRXWA BIT(5)
120#define FSPI_INTR_AHBCMDERR BIT(4)
121#define FSPI_INTR_IPCMDERR BIT(3)
122#define FSPI_INTR_AHBCMDGE BIT(2)
123#define FSPI_INTR_IPCMDGE BIT(1)
124#define FSPI_INTR_IPCMDDONE BIT(0)
125
126#define FSPI_LUTKEY 0x18
127#define FSPI_LUTKEY_VALUE 0x5AF05AF0
128
129#define FSPI_LCKCR 0x1C
130
131#define FSPI_LCKER_LOCK 0x1
132#define FSPI_LCKER_UNLOCK 0x2
133
134#define FSPI_BUFXCR_INVALID_MSTRID 0xE
135#define FSPI_AHBRX_BUF0CR0 0x20
136#define FSPI_AHBRX_BUF1CR0 0x24
137#define FSPI_AHBRX_BUF2CR0 0x28
138#define FSPI_AHBRX_BUF3CR0 0x2C
139#define FSPI_AHBRX_BUF4CR0 0x30
140#define FSPI_AHBRX_BUF5CR0 0x34
141#define FSPI_AHBRX_BUF6CR0 0x38
142#define FSPI_AHBRX_BUF7CR0 0x3C
143#define FSPI_AHBRXBUF0CR7_PREF BIT(31)
144
145#define FSPI_AHBRX_BUF0CR1 0x40
146#define FSPI_AHBRX_BUF1CR1 0x44
147#define FSPI_AHBRX_BUF2CR1 0x48
148#define FSPI_AHBRX_BUF3CR1 0x4C
149#define FSPI_AHBRX_BUF4CR1 0x50
150#define FSPI_AHBRX_BUF5CR1 0x54
151#define FSPI_AHBRX_BUF6CR1 0x58
152#define FSPI_AHBRX_BUF7CR1 0x5C
153
154#define FSPI_FLSHA1CR0 0x60
155#define FSPI_FLSHA2CR0 0x64
156#define FSPI_FLSHB1CR0 0x68
157#define FSPI_FLSHB2CR0 0x6C
158#define FSPI_FLSHXCR0_SZ_KB 10
159#define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB)
160
161#define FSPI_FLSHA1CR1 0x70
162#define FSPI_FLSHA2CR1 0x74
163#define FSPI_FLSHB1CR1 0x78
164#define FSPI_FLSHB2CR1 0x7C
165#define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16)
166#define FSPI_FLSHXCR1_CAS(x) ((x) << 11)
167#define FSPI_FLSHXCR1_WA BIT(10)
168#define FSPI_FLSHXCR1_TCSH(x) ((x) << 5)
169#define FSPI_FLSHXCR1_TCSS(x) (x)
170
171#define FSPI_FLSHA1CR2 0x80
172#define FSPI_FLSHA2CR2 0x84
173#define FSPI_FLSHB1CR2 0x88
174#define FSPI_FLSHB2CR2 0x8C
175#define FSPI_FLSHXCR2_CLRINSP BIT(24)
176#define FSPI_FLSHXCR2_AWRWAIT BIT(16)
177#define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
178#define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
179#define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
180#define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
181
182#define FSPI_IPCR0 0xA0
183
184#define FSPI_IPCR1 0xA4
185#define FSPI_IPCR1_IPAREN BIT(31)
186#define FSPI_IPCR1_SEQNUM_SHIFT 24
187#define FSPI_IPCR1_SEQID_SHIFT 16
188#define FSPI_IPCR1_IDATSZ(x) (x)
189
190#define FSPI_IPCMD 0xB0
191#define FSPI_IPCMD_TRG BIT(0)
192
193#define FSPI_DLPR 0xB4
194
195#define FSPI_IPRXFCR 0xB8
196#define FSPI_IPRXFCR_CLR BIT(0)
197#define FSPI_IPRXFCR_DMA_EN BIT(1)
198#define FSPI_IPRXFCR_WMRK(x) ((x) << 2)
199
200#define FSPI_IPTXFCR 0xBC
201#define FSPI_IPTXFCR_CLR BIT(0)
202#define FSPI_IPTXFCR_DMA_EN BIT(1)
203#define FSPI_IPTXFCR_WMRK(x) ((x) << 2)
204
205#define FSPI_DLLACR 0xC0
206#define FSPI_DLLACR_OVRDEN BIT(8)
207
208#define FSPI_DLLBCR 0xC4
209#define FSPI_DLLBCR_OVRDEN BIT(8)
210
211#define FSPI_STS0 0xE0
212#define FSPI_STS0_DLPHB(x) ((x) << 8)
213#define FSPI_STS0_DLPHA(x) ((x) << 4)
214#define FSPI_STS0_CMD_SRC(x) ((x) << 2)
215#define FSPI_STS0_ARB_IDLE BIT(1)
216#define FSPI_STS0_SEQ_IDLE BIT(0)
217
218#define FSPI_STS1 0xE4
219#define FSPI_STS1_IP_ERRCD(x) ((x) << 24)
220#define FSPI_STS1_IP_ERRID(x) ((x) << 16)
221#define FSPI_STS1_AHB_ERRCD(x) ((x) << 8)
222#define FSPI_STS1_AHB_ERRID(x) (x)
223
224#define FSPI_AHBSPNST 0xEC
225#define FSPI_AHBSPNST_DATLFT(x) ((x) << 16)
226#define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
227#define FSPI_AHBSPNST_ACTIVE BIT(0)
228
229#define FSPI_IPRXFSTS 0xF0
230#define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16)
231#define FSPI_IPRXFSTS_FILL(x) (x)
232
233#define FSPI_IPTXFSTS 0xF4
234#define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16)
235#define FSPI_IPTXFSTS_FILL(x) (x)
236
237#define FSPI_RFDR 0x100
238#define FSPI_TFDR 0x180
239
240#define FSPI_LUT_BASE 0x200
241#define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
242#define FSPI_LUT_REG(idx) \
243 (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
244
245/* register map end */
246
247/* Instruction set for the LUT register. */
248#define LUT_STOP 0x00
249#define LUT_CMD 0x01
250#define LUT_ADDR 0x02
251#define LUT_CADDR_SDR 0x03
252#define LUT_MODE 0x04
253#define LUT_MODE2 0x05
254#define LUT_MODE4 0x06
255#define LUT_MODE8 0x07
256#define LUT_NXP_WRITE 0x08
257#define LUT_NXP_READ 0x09
258#define LUT_LEARN_SDR 0x0A
259#define LUT_DATSZ_SDR 0x0B
260#define LUT_DUMMY 0x0C
261#define LUT_DUMMY_RWDS_SDR 0x0D
262#define LUT_JMP_ON_CS 0x1F
263#define LUT_CMD_DDR 0x21
264#define LUT_ADDR_DDR 0x22
265#define LUT_CADDR_DDR 0x23
266#define LUT_MODE_DDR 0x24
267#define LUT_MODE2_DDR 0x25
268#define LUT_MODE4_DDR 0x26
269#define LUT_MODE8_DDR 0x27
270#define LUT_WRITE_DDR 0x28
271#define LUT_READ_DDR 0x29
272#define LUT_LEARN_DDR 0x2A
273#define LUT_DATSZ_DDR 0x2B
274#define LUT_DUMMY_DDR 0x2C
275#define LUT_DUMMY_RWDS_DDR 0x2D
276
277/*
278 * Calculate number of required PAD bits for LUT register.
279 *
280 * The pad stands for the number of IO lines [0:7].
281 * For example, the octal read needs eight IO lines,
282 * so you should use LUT_PAD(8). This macro
283 * returns 3 i.e. use eight (2^3) IP lines for read.
284 */
285#define LUT_PAD(x) (fls(x) - 1)
286
287/*
288 * Macro for constructing the LUT entries with the following
289 * register layout:
290 *
291 * ---------------------------------------------------
292 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
293 * ---------------------------------------------------
294 */
295#define PAD_SHIFT 8
296#define INSTR_SHIFT 10
297#define OPRND_SHIFT 16
298
299/* Macros for constructing the LUT register. */
300#define LUT_DEF(idx, ins, pad, opr) \
301 ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \
302 (opr)) << (((idx) % 2) * OPRND_SHIFT))
303
304#define POLL_TOUT 5000
305#define NXP_FSPI_MAX_CHIPSELECT 4
306
307struct nxp_fspi_devtype_data {
308 unsigned int rxfifo;
309 unsigned int txfifo;
310 unsigned int ahb_buf_size;
311 unsigned int quirks;
312 bool little_endian;
313};
314
315static const struct nxp_fspi_devtype_data lx2160a_data = {
316 .rxfifo = SZ_512, /* (64 * 64 bits) */
317 .txfifo = SZ_1K, /* (128 * 64 bits) */
318 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
319 .quirks = 0,
320 .little_endian = true, /* little-endian */
321};
322
323struct nxp_fspi {
324 struct udevice *dev;
325 void __iomem *iobase;
326 void __iomem *ahb_addr;
327 u32 memmap_phy;
328 u32 memmap_phy_size;
329 struct clk clk, clk_en;
330 const struct nxp_fspi_devtype_data *devtype_data;
331};
332
333/*
334 * R/W functions for big- or little-endian registers:
335 * The FSPI controller's endianness is independent of
336 * the CPU core's endianness. So far, although the CPU
337 * core is little-endian the FSPI controller can use
338 * big-endian or little-endian.
339 */
340static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
341{
342 if (f->devtype_data->little_endian)
343 out_le32(addr, val);
344 else
345 out_be32(addr, val);
346}
347
348static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
349{
350 if (f->devtype_data->little_endian)
351 return in_le32(addr);
352 else
353 return in_be32(addr);
354}
355
356static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width)
357{
358 switch (width) {
359 case 1:
360 case 2:
361 case 4:
362 case 8:
363 return 0;
364 }
365
366 return -ENOTSUPP;
367}
368
369static bool nxp_fspi_supports_op(struct spi_slave *slave,
370 const struct spi_mem_op *op)
371{
372 struct nxp_fspi *f;
373 struct udevice *bus;
374 int ret;
375
376 bus = slave->dev->parent;
377 f = dev_get_priv(bus);
378
379 ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth);
380
381 if (op->addr.nbytes)
382 ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth);
383
384 if (op->dummy.nbytes)
385 ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth);
386
387 if (op->data.nbytes)
388 ret |= nxp_fspi_check_buswidth(f, op->data.buswidth);
389
390 if (ret)
391 return false;
392
393 /*
394 * The number of address bytes should be equal to or less than 4 bytes.
395 */
396 if (op->addr.nbytes > 4)
397 return false;
398
399 /*
400 * If requested address value is greater than controller assigned
401 * memory mapped space, return error as it didn't fit in the range
402 * of assigned address space.
403 */
404 if (op->addr.val >= f->memmap_phy_size)
405 return false;
406
407 /* Max 64 dummy clock cycles supported */
408 if (op->dummy.buswidth &&
409 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
410 return false;
411
412 /* Max data length, check controller limits and alignment */
413 if (op->data.dir == SPI_MEM_DATA_IN &&
414 (op->data.nbytes > f->devtype_data->ahb_buf_size ||
415 (op->data.nbytes > f->devtype_data->rxfifo - 4 &&
416 !IS_ALIGNED(op->data.nbytes, 8))))
417 return false;
418
419 if (op->data.dir == SPI_MEM_DATA_OUT &&
420 op->data.nbytes > f->devtype_data->txfifo)
421 return false;
422
423 return true;
424}
425
Kuldeep Singh28029c72020-04-27 12:38:51 +0530426/* Instead of busy looping invoke readl_poll_sleep_timeout functionality. */
Michael Walle383fded2019-12-18 00:09:58 +0100427static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
428 u32 mask, u32 delay_us,
429 u32 timeout_us, bool c)
430{
431 u32 reg;
432
433 if (!f->devtype_data->little_endian)
434 mask = (u32)cpu_to_be32(mask);
435
436 if (c)
Kuldeep Singh28029c72020-04-27 12:38:51 +0530437 return readl_poll_sleep_timeout(base, reg, (reg & mask),
438 delay_us, timeout_us);
Michael Walle383fded2019-12-18 00:09:58 +0100439 else
Kuldeep Singh28029c72020-04-27 12:38:51 +0530440 return readl_poll_sleep_timeout(base, reg, !(reg & mask),
441 delay_us, timeout_us);
Michael Walle383fded2019-12-18 00:09:58 +0100442}
443
444/*
445 * If the slave device content being changed by Write/Erase, need to
446 * invalidate the AHB buffer. This can be achieved by doing the reset
447 * of controller after setting MCR0[SWRESET] bit.
448 */
449static inline void nxp_fspi_invalid(struct nxp_fspi *f)
450{
451 u32 reg;
452 int ret;
453
454 reg = fspi_readl(f, f->iobase + FSPI_MCR0);
455 fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0);
456
457 /* w1c register, wait unit clear */
458 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
459 FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
460 WARN_ON(ret);
461}
462
463static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
464 const struct spi_mem_op *op)
465{
466 void __iomem *base = f->iobase;
467 u32 lutval[4] = {};
468 int lutidx = 1, i;
469
470 /* cmd */
471 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
472 op->cmd.opcode);
473
474 /* addr bytes */
475 if (op->addr.nbytes) {
476 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
477 LUT_PAD(op->addr.buswidth),
478 op->addr.nbytes * 8);
479 lutidx++;
480 }
481
482 /* dummy bytes, if needed */
483 if (op->dummy.nbytes) {
484 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
485 /*
486 * Due to FlexSPI controller limitation number of PAD for dummy
487 * buswidth needs to be programmed as equal to data buswidth.
488 */
489 LUT_PAD(op->data.buswidth),
490 op->dummy.nbytes * 8 /
491 op->dummy.buswidth);
492 lutidx++;
493 }
494
495 /* read/write data bytes */
496 if (op->data.nbytes) {
497 lutval[lutidx / 2] |= LUT_DEF(lutidx,
498 op->data.dir == SPI_MEM_DATA_IN ?
499 LUT_NXP_READ : LUT_NXP_WRITE,
500 LUT_PAD(op->data.buswidth),
501 0);
502 lutidx++;
503 }
504
505 /* stop condition. */
506 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
507
508 /* unlock LUT */
509 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
510 fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR);
511
512 /* fill LUT */
513 for (i = 0; i < ARRAY_SIZE(lutval); i++)
514 fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i));
515
516 dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
517 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
518
519 /* lock LUT */
520 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
521 fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR);
522}
523
Alper Nebi Yasak957a3e52020-10-05 09:57:29 +0300524#if CONFIG_IS_ENABLED(CLK)
Michael Walle383fded2019-12-18 00:09:58 +0100525static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f)
526{
527 int ret;
528
529 ret = clk_enable(&f->clk_en);
530 if (ret)
531 return ret;
532
533 ret = clk_enable(&f->clk);
534 if (ret) {
535 clk_disable(&f->clk_en);
536 return ret;
537 }
538
539 return 0;
540}
541
542static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
543{
544 clk_disable(&f->clk);
545 clk_disable(&f->clk_en);
546}
547#endif
548
549/*
550 * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
551 * register and start base address of the slave device.
552 *
553 * (Higher address)
554 * -------- <-- FLSHB2CR0
555 * | B2 |
556 * | |
557 * B2 start address --> -------- <-- FLSHB1CR0
558 * | B1 |
559 * | |
560 * B1 start address --> -------- <-- FLSHA2CR0
561 * | A2 |
562 * | |
563 * A2 start address --> -------- <-- FLSHA1CR0
564 * | A1 |
565 * | |
566 * A1 start address --> -------- (Lower address)
567 *
568 *
569 * Start base address defines the starting address range for given CS and
570 * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS.
571 *
572 * But, different targets are having different combinations of number of CS,
573 * some targets only have single CS or two CS covering controller's full
574 * memory mapped space area.
575 * Thus, implementation is being done as independent of the size and number
576 * of the connected slave device.
577 * Assign controller memory mapped space size as the size to the connected
578 * slave device.
579 * Mark FLSHxxCR0 as zero initially and then assign value only to the selected
580 * chip-select Flash configuration register.
581 *
582 * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the
583 * memory mapped size of the controller.
584 * Value for rest of the CS FLSHxxCR0 register would be zero.
585 *
586 */
587static void nxp_fspi_select_mem(struct nxp_fspi *f, int chip_select)
588{
589 u64 size_kb;
590
591 /* Reset FLSHxxCR0 registers */
592 fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0);
593 fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0);
594 fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0);
595 fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0);
596
597 /* Assign controller memory mapped space as size, KBytes, of flash. */
598 size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);
599
600 fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
601 4 * chip_select);
602
603 dev_dbg(f->dev, "Slave device [CS:%x] selected\n", chip_select);
604}
605
606static void nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
607{
608 u32 len = op->data.nbytes;
609
610 /* Read out the data directly from the AHB buffer. */
611 memcpy_fromio(op->data.buf.in, (f->ahb_addr + op->addr.val), len);
612}
613
614static void nxp_fspi_fill_txfifo(struct nxp_fspi *f,
615 const struct spi_mem_op *op)
616{
617 void __iomem *base = f->iobase;
618 int i, ret;
619 u8 *buf = (u8 *)op->data.buf.out;
620
621 /* clear the TX FIFO. */
622 fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR);
623
624 /*
625 * Default value of water mark level is 8 bytes, hence in single
626 * write request controller can write max 8 bytes of data.
627 */
628
629 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) {
630 /* Wait for TXFIFO empty */
631 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
632 FSPI_INTR_IPTXWE, 0,
633 POLL_TOUT, true);
634 WARN_ON(ret);
635
636 fspi_writel(f, *(u32 *)(buf + i), base + FSPI_TFDR);
637 fspi_writel(f, *(u32 *)(buf + i + 4), base + FSPI_TFDR + 4);
638 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
639 }
640
641 if (i < op->data.nbytes) {
642 u32 data = 0;
643 int j;
644 /* Wait for TXFIFO empty */
645 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
646 FSPI_INTR_IPTXWE, 0,
647 POLL_TOUT, true);
648 WARN_ON(ret);
649
650 for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) {
651 memcpy(&data, buf + i + j, 4);
652 fspi_writel(f, data, base + FSPI_TFDR + j);
653 }
654 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
655 }
656}
657
658static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
659 const struct spi_mem_op *op)
660{
661 void __iomem *base = f->iobase;
662 int i, ret;
663 int len = op->data.nbytes;
664 u8 *buf = (u8 *)op->data.buf.in;
665
666 /*
667 * Default value of water mark level is 8 bytes, hence in single
668 * read request controller can read max 8 bytes of data.
669 */
670 for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) {
671 /* Wait for RXFIFO available */
672 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
673 FSPI_INTR_IPRXWA, 0,
674 POLL_TOUT, true);
675 WARN_ON(ret);
676
677 *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR);
678 *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4);
679 /* move the FIFO pointer */
680 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
681 }
682
683 if (i < len) {
684 u32 tmp;
685 int size, j;
686
687 buf = op->data.buf.in + i;
688 /* Wait for RXFIFO available */
689 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
690 FSPI_INTR_IPRXWA, 0,
691 POLL_TOUT, true);
692 WARN_ON(ret);
693
694 len = op->data.nbytes - i;
695 for (j = 0; j < op->data.nbytes - i; j += 4) {
696 tmp = fspi_readl(f, base + FSPI_RFDR + j);
697 size = min(len, 4);
698 memcpy(buf + j, &tmp, size);
699 len -= size;
700 }
701 }
702
703 /* invalid the RXFIFO */
704 fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR);
705 /* move the FIFO pointer */
706 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
707}
708
709static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
710{
711 void __iomem *base = f->iobase;
712 int seqnum = 0;
713 int err = 0;
714 u32 reg;
715
716 reg = fspi_readl(f, base + FSPI_IPRXFCR);
717 /* invalid RXFIFO first */
718 reg &= ~FSPI_IPRXFCR_DMA_EN;
719 reg = reg | FSPI_IPRXFCR_CLR;
720 fspi_writel(f, reg, base + FSPI_IPRXFCR);
721
722 fspi_writel(f, op->addr.val, base + FSPI_IPCR0);
723 /*
724 * Always start the sequence at the same index since we update
725 * the LUT at each exec_op() call. And also specify the DATA
726 * length, since it's has not been specified in the LUT.
727 */
728 fspi_writel(f, op->data.nbytes |
729 (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
730 (seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
731 base + FSPI_IPCR1);
732
733 /* Trigger the LUT now. */
734 fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD);
735
736 /* Wait for the completion. */
737 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
738 FSPI_STS0_ARB_IDLE, 1, 1000 * 1000, true);
739
740 /* Invoke IP data read, if request is of data read. */
741 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
742 nxp_fspi_read_rxfifo(f, op);
743
744 return err;
745}
746
747static int nxp_fspi_exec_op(struct spi_slave *slave,
748 const struct spi_mem_op *op)
749{
750 struct nxp_fspi *f;
751 struct udevice *bus;
752 int err = 0;
753
754 bus = slave->dev->parent;
755 f = dev_get_priv(bus);
756
757 /* Wait for controller being ready. */
758 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
759 FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
760 WARN_ON(err);
761
762 nxp_fspi_prepare_lut(f, op);
763 /*
764 * If we have large chunks of data, we read them through the AHB bus
765 * by accessing the mapped memory. In all other cases we use
766 * IP commands to access the flash.
767 */
768 if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
769 op->data.dir == SPI_MEM_DATA_IN) {
770 nxp_fspi_read_ahb(f, op);
771 } else {
772 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
773 nxp_fspi_fill_txfifo(f, op);
774
775 err = nxp_fspi_do_op(f, op);
776 }
777
778 /* Invalidate the data in the AHB buffer. */
779 nxp_fspi_invalid(f);
780
781 return err;
782}
783
784static int nxp_fspi_adjust_op_size(struct spi_slave *slave,
785 struct spi_mem_op *op)
786{
787 struct nxp_fspi *f;
788 struct udevice *bus;
789
790 bus = slave->dev->parent;
791 f = dev_get_priv(bus);
792
793 if (op->data.dir == SPI_MEM_DATA_OUT) {
794 if (op->data.nbytes > f->devtype_data->txfifo)
795 op->data.nbytes = f->devtype_data->txfifo;
796 } else {
797 if (op->data.nbytes > f->devtype_data->ahb_buf_size)
798 op->data.nbytes = f->devtype_data->ahb_buf_size;
799 else if (op->data.nbytes > (f->devtype_data->rxfifo - 4))
800 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
801 }
802
803 return 0;
804}
805
806static int nxp_fspi_default_setup(struct nxp_fspi *f)
807{
808 void __iomem *base = f->iobase;
809 int ret, i;
810 u32 reg;
811
Alper Nebi Yasak957a3e52020-10-05 09:57:29 +0300812#if CONFIG_IS_ENABLED(CLK)
Michael Walle383fded2019-12-18 00:09:58 +0100813 /* disable and unprepare clock to avoid glitch pass to controller */
814 nxp_fspi_clk_disable_unprep(f);
815
816 /* the default frequency, we will change it later if necessary. */
817 ret = clk_set_rate(&f->clk, 20000000);
818 if (ret)
819 return ret;
820
821 ret = nxp_fspi_clk_prep_enable(f);
822 if (ret)
823 return ret;
824#endif
825
826 /* Reset the module */
827 /* w1c register, wait unit clear */
828 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
829 FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
830 WARN_ON(ret);
831
832 /* Disable the module */
833 fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
834
835 /* Reset the DLL register to default value */
836 fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
837 fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
838
839 /* enable module */
840 fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | FSPI_MCR0_IP_TIMEOUT(0xFF),
841 base + FSPI_MCR0);
842
843 /*
844 * Disable same device enable bit and configure all slave devices
845 * independently.
846 */
847 reg = fspi_readl(f, f->iobase + FSPI_MCR2);
848 reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);
849 fspi_writel(f, reg, base + FSPI_MCR2);
850
851 /* AHB configuration for access buffer 0~7. */
852 for (i = 0; i < 7; i++)
853 fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i);
854
855 /*
856 * Set ADATSZ with the maximum AHB buffer size to improve the read
857 * performance.
858 */
859 fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 |
860 FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0);
861
862 /* prefetch and no start address alignment limitation */
863 fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
864 base + FSPI_AHBCR);
865
866 /* AHB Read - Set lut sequence ID for all CS. */
867 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
868 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);
869 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2);
870 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2);
871
872 return 0;
873}
874
875static int nxp_fspi_probe(struct udevice *bus)
876{
877 struct nxp_fspi *f = dev_get_priv(bus);
878
879 f->devtype_data =
880 (struct nxp_fspi_devtype_data *)dev_get_driver_data(bus);
881 nxp_fspi_default_setup(f);
882
883 return 0;
884}
885
886static int nxp_fspi_claim_bus(struct udevice *dev)
887{
888 struct nxp_fspi *f;
889 struct udevice *bus;
Simon Glass8a8d24b2020-12-03 16:55:23 -0700890 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
Michael Walle383fded2019-12-18 00:09:58 +0100891
892 bus = dev->parent;
893 f = dev_get_priv(bus);
894
895 nxp_fspi_select_mem(f, slave_plat->cs);
896
897 return 0;
898}
899
900static int nxp_fspi_set_speed(struct udevice *bus, uint speed)
901{
Alper Nebi Yasak957a3e52020-10-05 09:57:29 +0300902#if CONFIG_IS_ENABLED(CLK)
Michael Walle383fded2019-12-18 00:09:58 +0100903 struct nxp_fspi *f = dev_get_priv(bus);
904 int ret;
905
906 nxp_fspi_clk_disable_unprep(f);
907
908 ret = clk_set_rate(&f->clk, speed);
909 if (ret)
910 return ret;
911
912 ret = nxp_fspi_clk_prep_enable(f);
913 if (ret)
914 return ret;
915#endif
916 return 0;
917}
918
919static int nxp_fspi_set_mode(struct udevice *bus, uint mode)
920{
921 /* Nothing to do */
922 return 0;
923}
924
Simon Glassd1998a92020-12-03 16:55:21 -0700925static int nxp_fspi_of_to_plat(struct udevice *bus)
Michael Walle383fded2019-12-18 00:09:58 +0100926{
927 struct nxp_fspi *f = dev_get_priv(bus);
Alper Nebi Yasak957a3e52020-10-05 09:57:29 +0300928#if CONFIG_IS_ENABLED(CLK)
Michael Walle383fded2019-12-18 00:09:58 +0100929 int ret;
930#endif
931
932 fdt_addr_t iobase;
933 fdt_addr_t iobase_size;
934 fdt_addr_t ahb_addr;
935 fdt_addr_t ahb_size;
936
937 f->dev = bus;
938
939 iobase = devfdt_get_addr_size_name(bus, "fspi_base", &iobase_size);
940 if (iobase == FDT_ADDR_T_NONE) {
941 dev_err(bus, "fspi_base regs missing\n");
942 return -ENODEV;
943 }
944 f->iobase = map_physmem(iobase, iobase_size, MAP_NOCACHE);
945
946 ahb_addr = devfdt_get_addr_size_name(bus, "fspi_mmap", &ahb_size);
947 if (ahb_addr == FDT_ADDR_T_NONE) {
948 dev_err(bus, "fspi_mmap regs missing\n");
949 return -ENODEV;
950 }
951 f->ahb_addr = map_physmem(ahb_addr, ahb_size, MAP_NOCACHE);
952 f->memmap_phy_size = ahb_size;
953
Alper Nebi Yasak957a3e52020-10-05 09:57:29 +0300954#if CONFIG_IS_ENABLED(CLK)
Michael Walle383fded2019-12-18 00:09:58 +0100955 ret = clk_get_by_name(bus, "fspi_en", &f->clk_en);
956 if (ret) {
957 dev_err(bus, "failed to get fspi_en clock\n");
958 return ret;
959 }
960
961 ret = clk_get_by_name(bus, "fspi", &f->clk);
962 if (ret) {
963 dev_err(bus, "failed to get fspi clock\n");
964 return ret;
965 }
966#endif
967
968 dev_dbg(bus, "iobase=<0x%llx>, ahb_addr=<0x%llx>\n", iobase, ahb_addr);
969
970 return 0;
971}
972
973static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
974 .adjust_op_size = nxp_fspi_adjust_op_size,
975 .supports_op = nxp_fspi_supports_op,
976 .exec_op = nxp_fspi_exec_op,
977};
978
979static const struct dm_spi_ops nxp_fspi_ops = {
980 .claim_bus = nxp_fspi_claim_bus,
981 .set_speed = nxp_fspi_set_speed,
982 .set_mode = nxp_fspi_set_mode,
983 .mem_ops = &nxp_fspi_mem_ops,
984};
985
986static const struct udevice_id nxp_fspi_ids[] = {
987 { .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, },
988 { }
989};
990
991U_BOOT_DRIVER(nxp_fspi) = {
992 .name = "nxp_fspi",
993 .id = UCLASS_SPI,
994 .of_match = nxp_fspi_ids,
995 .ops = &nxp_fspi_ops,
Simon Glassd1998a92020-12-03 16:55:21 -0700996 .of_to_plat = nxp_fspi_of_to_plat,
Simon Glass41575d82020-12-03 16:55:17 -0700997 .priv_auto = sizeof(struct nxp_fspi),
Michael Walle383fded2019-12-18 00:09:58 +0100998 .probe = nxp_fspi_probe,
999};