blob: 0e6c7be785afd0525bab31e5cbea2fbe1ba21060 [file] [log] [blame]
Michael Walle383fded2019-12-18 00:09:58 +01001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * NXP FlexSPI(FSPI) controller driver.
4 *
5 * Copyright (c) 2019 Michael Walle <michael@walle.cc>
6 * Copyright (c) 2019 NXP
7 *
8 * This driver was originally ported from the linux kernel v5.4-rc3, which had
9 * the following notes:
10 *
11 * FlexSPI is a flexsible SPI host controller which supports two SPI
12 * channels and up to 4 external devices. Each channel supports
13 * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
14 * data lines).
15 *
16 * FlexSPI controller is driven by the LUT(Look-up Table) registers
17 * LUT registers are a look-up-table for sequences of instructions.
18 * A valid sequence consists of four LUT registers.
19 * Maximum 32 LUT sequences can be programmed simultaneously.
20 *
21 * LUTs are being created at run-time based on the commands passed
22 * from the spi-mem framework, thus using single LUT index.
23 *
24 * Software triggered Flash read/write access by IP Bus.
25 *
26 * Memory mapped read access by AHB Bus.
27 *
28 * Based on SPI MEM interface and spi-fsl-qspi.c driver.
29 *
30 * Author:
31 * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
32 * Boris Brezillon <bbrezillon@kernel.org>
33 * Frieder Schrempf <frieder.schrempf@kontron.de>
34 */
35
36#include <common.h>
37#include <asm/io.h>
38#include <malloc.h>
39#include <spi.h>
40#include <spi-mem.h>
41#include <dm.h>
42#include <clk.h>
43#include <linux/kernel.h>
44#include <linux/sizes.h>
45#include <linux/iopoll.h>
46#include <linux/bug.h>
Simon Glassf2176512020-02-03 07:36:17 -070047#include <linux/err.h>
Michael Walle383fded2019-12-18 00:09:58 +010048
49/*
50 * The driver only uses one single LUT entry, that is updated on
51 * each call of exec_op(). Index 0 is preset at boot with a basic
52 * read operation, so let's use the last entry (31).
53 */
54#define SEQID_LUT 31
55
56/* Registers used by the driver */
57#define FSPI_MCR0 0x00
58#define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
59#define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16)
60#define FSPI_MCR0_LEARN_EN BIT(15)
61#define FSPI_MCR0_SCRFRUN_EN BIT(14)
62#define FSPI_MCR0_OCTCOMB_EN BIT(13)
63#define FSPI_MCR0_DOZE_EN BIT(12)
64#define FSPI_MCR0_HSEN BIT(11)
65#define FSPI_MCR0_SERCLKDIV BIT(8)
66#define FSPI_MCR0_ATDF_EN BIT(7)
67#define FSPI_MCR0_ARDF_EN BIT(6)
68#define FSPI_MCR0_RXCLKSRC(x) ((x) << 4)
69#define FSPI_MCR0_END_CFG(x) ((x) << 2)
70#define FSPI_MCR0_MDIS BIT(1)
71#define FSPI_MCR0_SWRST BIT(0)
72
73#define FSPI_MCR1 0x04
74#define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16)
75#define FSPI_MCR1_AHB_TIMEOUT(x) (x)
76
77#define FSPI_MCR2 0x08
78#define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24)
79#define FSPI_MCR2_SAMEDEVICEEN BIT(15)
80#define FSPI_MCR2_CLRLRPHS BIT(14)
81#define FSPI_MCR2_ABRDATSZ BIT(8)
82#define FSPI_MCR2_ABRLEARN BIT(7)
83#define FSPI_MCR2_ABR_READ BIT(6)
84#define FSPI_MCR2_ABRWRITE BIT(5)
85#define FSPI_MCR2_ABRDUMMY BIT(4)
86#define FSPI_MCR2_ABR_MODE BIT(3)
87#define FSPI_MCR2_ABRCADDR BIT(2)
88#define FSPI_MCR2_ABRRADDR BIT(1)
89#define FSPI_MCR2_ABR_CMD BIT(0)
90
91#define FSPI_AHBCR 0x0c
92#define FSPI_AHBCR_RDADDROPT BIT(6)
93#define FSPI_AHBCR_PREF_EN BIT(5)
94#define FSPI_AHBCR_BUFF_EN BIT(4)
95#define FSPI_AHBCR_CACH_EN BIT(3)
96#define FSPI_AHBCR_CLRTXBUF BIT(2)
97#define FSPI_AHBCR_CLRRXBUF BIT(1)
98#define FSPI_AHBCR_PAR_EN BIT(0)
99
100#define FSPI_INTEN 0x10
101#define FSPI_INTEN_SCLKSBWR BIT(9)
102#define FSPI_INTEN_SCLKSBRD BIT(8)
103#define FSPI_INTEN_DATALRNFL BIT(7)
104#define FSPI_INTEN_IPTXWE BIT(6)
105#define FSPI_INTEN_IPRXWA BIT(5)
106#define FSPI_INTEN_AHBCMDERR BIT(4)
107#define FSPI_INTEN_IPCMDERR BIT(3)
108#define FSPI_INTEN_AHBCMDGE BIT(2)
109#define FSPI_INTEN_IPCMDGE BIT(1)
110#define FSPI_INTEN_IPCMDDONE BIT(0)
111
112#define FSPI_INTR 0x14
113#define FSPI_INTR_SCLKSBWR BIT(9)
114#define FSPI_INTR_SCLKSBRD BIT(8)
115#define FSPI_INTR_DATALRNFL BIT(7)
116#define FSPI_INTR_IPTXWE BIT(6)
117#define FSPI_INTR_IPRXWA BIT(5)
118#define FSPI_INTR_AHBCMDERR BIT(4)
119#define FSPI_INTR_IPCMDERR BIT(3)
120#define FSPI_INTR_AHBCMDGE BIT(2)
121#define FSPI_INTR_IPCMDGE BIT(1)
122#define FSPI_INTR_IPCMDDONE BIT(0)
123
124#define FSPI_LUTKEY 0x18
125#define FSPI_LUTKEY_VALUE 0x5AF05AF0
126
127#define FSPI_LCKCR 0x1C
128
129#define FSPI_LCKER_LOCK 0x1
130#define FSPI_LCKER_UNLOCK 0x2
131
132#define FSPI_BUFXCR_INVALID_MSTRID 0xE
133#define FSPI_AHBRX_BUF0CR0 0x20
134#define FSPI_AHBRX_BUF1CR0 0x24
135#define FSPI_AHBRX_BUF2CR0 0x28
136#define FSPI_AHBRX_BUF3CR0 0x2C
137#define FSPI_AHBRX_BUF4CR0 0x30
138#define FSPI_AHBRX_BUF5CR0 0x34
139#define FSPI_AHBRX_BUF6CR0 0x38
140#define FSPI_AHBRX_BUF7CR0 0x3C
141#define FSPI_AHBRXBUF0CR7_PREF BIT(31)
142
143#define FSPI_AHBRX_BUF0CR1 0x40
144#define FSPI_AHBRX_BUF1CR1 0x44
145#define FSPI_AHBRX_BUF2CR1 0x48
146#define FSPI_AHBRX_BUF3CR1 0x4C
147#define FSPI_AHBRX_BUF4CR1 0x50
148#define FSPI_AHBRX_BUF5CR1 0x54
149#define FSPI_AHBRX_BUF6CR1 0x58
150#define FSPI_AHBRX_BUF7CR1 0x5C
151
152#define FSPI_FLSHA1CR0 0x60
153#define FSPI_FLSHA2CR0 0x64
154#define FSPI_FLSHB1CR0 0x68
155#define FSPI_FLSHB2CR0 0x6C
156#define FSPI_FLSHXCR0_SZ_KB 10
157#define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB)
158
159#define FSPI_FLSHA1CR1 0x70
160#define FSPI_FLSHA2CR1 0x74
161#define FSPI_FLSHB1CR1 0x78
162#define FSPI_FLSHB2CR1 0x7C
163#define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16)
164#define FSPI_FLSHXCR1_CAS(x) ((x) << 11)
165#define FSPI_FLSHXCR1_WA BIT(10)
166#define FSPI_FLSHXCR1_TCSH(x) ((x) << 5)
167#define FSPI_FLSHXCR1_TCSS(x) (x)
168
169#define FSPI_FLSHA1CR2 0x80
170#define FSPI_FLSHA2CR2 0x84
171#define FSPI_FLSHB1CR2 0x88
172#define FSPI_FLSHB2CR2 0x8C
173#define FSPI_FLSHXCR2_CLRINSP BIT(24)
174#define FSPI_FLSHXCR2_AWRWAIT BIT(16)
175#define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
176#define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
177#define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
178#define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
179
180#define FSPI_IPCR0 0xA0
181
182#define FSPI_IPCR1 0xA4
183#define FSPI_IPCR1_IPAREN BIT(31)
184#define FSPI_IPCR1_SEQNUM_SHIFT 24
185#define FSPI_IPCR1_SEQID_SHIFT 16
186#define FSPI_IPCR1_IDATSZ(x) (x)
187
188#define FSPI_IPCMD 0xB0
189#define FSPI_IPCMD_TRG BIT(0)
190
191#define FSPI_DLPR 0xB4
192
193#define FSPI_IPRXFCR 0xB8
194#define FSPI_IPRXFCR_CLR BIT(0)
195#define FSPI_IPRXFCR_DMA_EN BIT(1)
196#define FSPI_IPRXFCR_WMRK(x) ((x) << 2)
197
198#define FSPI_IPTXFCR 0xBC
199#define FSPI_IPTXFCR_CLR BIT(0)
200#define FSPI_IPTXFCR_DMA_EN BIT(1)
201#define FSPI_IPTXFCR_WMRK(x) ((x) << 2)
202
203#define FSPI_DLLACR 0xC0
204#define FSPI_DLLACR_OVRDEN BIT(8)
205
206#define FSPI_DLLBCR 0xC4
207#define FSPI_DLLBCR_OVRDEN BIT(8)
208
209#define FSPI_STS0 0xE0
210#define FSPI_STS0_DLPHB(x) ((x) << 8)
211#define FSPI_STS0_DLPHA(x) ((x) << 4)
212#define FSPI_STS0_CMD_SRC(x) ((x) << 2)
213#define FSPI_STS0_ARB_IDLE BIT(1)
214#define FSPI_STS0_SEQ_IDLE BIT(0)
215
216#define FSPI_STS1 0xE4
217#define FSPI_STS1_IP_ERRCD(x) ((x) << 24)
218#define FSPI_STS1_IP_ERRID(x) ((x) << 16)
219#define FSPI_STS1_AHB_ERRCD(x) ((x) << 8)
220#define FSPI_STS1_AHB_ERRID(x) (x)
221
222#define FSPI_AHBSPNST 0xEC
223#define FSPI_AHBSPNST_DATLFT(x) ((x) << 16)
224#define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
225#define FSPI_AHBSPNST_ACTIVE BIT(0)
226
227#define FSPI_IPRXFSTS 0xF0
228#define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16)
229#define FSPI_IPRXFSTS_FILL(x) (x)
230
231#define FSPI_IPTXFSTS 0xF4
232#define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16)
233#define FSPI_IPTXFSTS_FILL(x) (x)
234
235#define FSPI_RFDR 0x100
236#define FSPI_TFDR 0x180
237
238#define FSPI_LUT_BASE 0x200
239#define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
240#define FSPI_LUT_REG(idx) \
241 (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
242
243/* register map end */
244
245/* Instruction set for the LUT register. */
246#define LUT_STOP 0x00
247#define LUT_CMD 0x01
248#define LUT_ADDR 0x02
249#define LUT_CADDR_SDR 0x03
250#define LUT_MODE 0x04
251#define LUT_MODE2 0x05
252#define LUT_MODE4 0x06
253#define LUT_MODE8 0x07
254#define LUT_NXP_WRITE 0x08
255#define LUT_NXP_READ 0x09
256#define LUT_LEARN_SDR 0x0A
257#define LUT_DATSZ_SDR 0x0B
258#define LUT_DUMMY 0x0C
259#define LUT_DUMMY_RWDS_SDR 0x0D
260#define LUT_JMP_ON_CS 0x1F
261#define LUT_CMD_DDR 0x21
262#define LUT_ADDR_DDR 0x22
263#define LUT_CADDR_DDR 0x23
264#define LUT_MODE_DDR 0x24
265#define LUT_MODE2_DDR 0x25
266#define LUT_MODE4_DDR 0x26
267#define LUT_MODE8_DDR 0x27
268#define LUT_WRITE_DDR 0x28
269#define LUT_READ_DDR 0x29
270#define LUT_LEARN_DDR 0x2A
271#define LUT_DATSZ_DDR 0x2B
272#define LUT_DUMMY_DDR 0x2C
273#define LUT_DUMMY_RWDS_DDR 0x2D
274
275/*
276 * Calculate number of required PAD bits for LUT register.
277 *
278 * The pad stands for the number of IO lines [0:7].
279 * For example, the octal read needs eight IO lines,
280 * so you should use LUT_PAD(8). This macro
281 * returns 3 i.e. use eight (2^3) IP lines for read.
282 */
283#define LUT_PAD(x) (fls(x) - 1)
284
285/*
286 * Macro for constructing the LUT entries with the following
287 * register layout:
288 *
289 * ---------------------------------------------------
290 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
291 * ---------------------------------------------------
292 */
293#define PAD_SHIFT 8
294#define INSTR_SHIFT 10
295#define OPRND_SHIFT 16
296
297/* Macros for constructing the LUT register. */
298#define LUT_DEF(idx, ins, pad, opr) \
299 ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \
300 (opr)) << (((idx) % 2) * OPRND_SHIFT))
301
302#define POLL_TOUT 5000
303#define NXP_FSPI_MAX_CHIPSELECT 4
304
305struct nxp_fspi_devtype_data {
306 unsigned int rxfifo;
307 unsigned int txfifo;
308 unsigned int ahb_buf_size;
309 unsigned int quirks;
310 bool little_endian;
311};
312
313static const struct nxp_fspi_devtype_data lx2160a_data = {
314 .rxfifo = SZ_512, /* (64 * 64 bits) */
315 .txfifo = SZ_1K, /* (128 * 64 bits) */
316 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
317 .quirks = 0,
318 .little_endian = true, /* little-endian */
319};
320
321struct nxp_fspi {
322 struct udevice *dev;
323 void __iomem *iobase;
324 void __iomem *ahb_addr;
325 u32 memmap_phy;
326 u32 memmap_phy_size;
327 struct clk clk, clk_en;
328 const struct nxp_fspi_devtype_data *devtype_data;
329};
330
331/*
332 * R/W functions for big- or little-endian registers:
333 * The FSPI controller's endianness is independent of
334 * the CPU core's endianness. So far, although the CPU
335 * core is little-endian the FSPI controller can use
336 * big-endian or little-endian.
337 */
338static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
339{
340 if (f->devtype_data->little_endian)
341 out_le32(addr, val);
342 else
343 out_be32(addr, val);
344}
345
346static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
347{
348 if (f->devtype_data->little_endian)
349 return in_le32(addr);
350 else
351 return in_be32(addr);
352}
353
354static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width)
355{
356 switch (width) {
357 case 1:
358 case 2:
359 case 4:
360 case 8:
361 return 0;
362 }
363
364 return -ENOTSUPP;
365}
366
367static bool nxp_fspi_supports_op(struct spi_slave *slave,
368 const struct spi_mem_op *op)
369{
370 struct nxp_fspi *f;
371 struct udevice *bus;
372 int ret;
373
374 bus = slave->dev->parent;
375 f = dev_get_priv(bus);
376
377 ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth);
378
379 if (op->addr.nbytes)
380 ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth);
381
382 if (op->dummy.nbytes)
383 ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth);
384
385 if (op->data.nbytes)
386 ret |= nxp_fspi_check_buswidth(f, op->data.buswidth);
387
388 if (ret)
389 return false;
390
391 /*
392 * The number of address bytes should be equal to or less than 4 bytes.
393 */
394 if (op->addr.nbytes > 4)
395 return false;
396
397 /*
398 * If requested address value is greater than controller assigned
399 * memory mapped space, return error as it didn't fit in the range
400 * of assigned address space.
401 */
402 if (op->addr.val >= f->memmap_phy_size)
403 return false;
404
405 /* Max 64 dummy clock cycles supported */
406 if (op->dummy.buswidth &&
407 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
408 return false;
409
410 /* Max data length, check controller limits and alignment */
411 if (op->data.dir == SPI_MEM_DATA_IN &&
412 (op->data.nbytes > f->devtype_data->ahb_buf_size ||
413 (op->data.nbytes > f->devtype_data->rxfifo - 4 &&
414 !IS_ALIGNED(op->data.nbytes, 8))))
415 return false;
416
417 if (op->data.dir == SPI_MEM_DATA_OUT &&
418 op->data.nbytes > f->devtype_data->txfifo)
419 return false;
420
421 return true;
422}
423
424/* Instead of busy looping invoke readl_poll_timeout functionality. */
425static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
426 u32 mask, u32 delay_us,
427 u32 timeout_us, bool c)
428{
429 u32 reg;
430
431 if (!f->devtype_data->little_endian)
432 mask = (u32)cpu_to_be32(mask);
433
434 if (c)
435 return readl_poll_timeout(base, reg, (reg & mask),
436 timeout_us);
437 else
438 return readl_poll_timeout(base, reg, !(reg & mask),
439 timeout_us);
440}
441
442/*
443 * If the slave device content being changed by Write/Erase, need to
444 * invalidate the AHB buffer. This can be achieved by doing the reset
445 * of controller after setting MCR0[SWRESET] bit.
446 */
447static inline void nxp_fspi_invalid(struct nxp_fspi *f)
448{
449 u32 reg;
450 int ret;
451
452 reg = fspi_readl(f, f->iobase + FSPI_MCR0);
453 fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0);
454
455 /* w1c register, wait unit clear */
456 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
457 FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
458 WARN_ON(ret);
459}
460
461static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
462 const struct spi_mem_op *op)
463{
464 void __iomem *base = f->iobase;
465 u32 lutval[4] = {};
466 int lutidx = 1, i;
467
468 /* cmd */
469 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
470 op->cmd.opcode);
471
472 /* addr bytes */
473 if (op->addr.nbytes) {
474 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
475 LUT_PAD(op->addr.buswidth),
476 op->addr.nbytes * 8);
477 lutidx++;
478 }
479
480 /* dummy bytes, if needed */
481 if (op->dummy.nbytes) {
482 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
483 /*
484 * Due to FlexSPI controller limitation number of PAD for dummy
485 * buswidth needs to be programmed as equal to data buswidth.
486 */
487 LUT_PAD(op->data.buswidth),
488 op->dummy.nbytes * 8 /
489 op->dummy.buswidth);
490 lutidx++;
491 }
492
493 /* read/write data bytes */
494 if (op->data.nbytes) {
495 lutval[lutidx / 2] |= LUT_DEF(lutidx,
496 op->data.dir == SPI_MEM_DATA_IN ?
497 LUT_NXP_READ : LUT_NXP_WRITE,
498 LUT_PAD(op->data.buswidth),
499 0);
500 lutidx++;
501 }
502
503 /* stop condition. */
504 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
505
506 /* unlock LUT */
507 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
508 fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR);
509
510 /* fill LUT */
511 for (i = 0; i < ARRAY_SIZE(lutval); i++)
512 fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i));
513
514 dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
515 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
516
517 /* lock LUT */
518 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
519 fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR);
520}
521
522#if CONFIG_IS_ENABLED(CONFIG_CLK)
523static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f)
524{
525 int ret;
526
527 ret = clk_enable(&f->clk_en);
528 if (ret)
529 return ret;
530
531 ret = clk_enable(&f->clk);
532 if (ret) {
533 clk_disable(&f->clk_en);
534 return ret;
535 }
536
537 return 0;
538}
539
540static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
541{
542 clk_disable(&f->clk);
543 clk_disable(&f->clk_en);
544}
545#endif
546
547/*
548 * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
549 * register and start base address of the slave device.
550 *
551 * (Higher address)
552 * -------- <-- FLSHB2CR0
553 * | B2 |
554 * | |
555 * B2 start address --> -------- <-- FLSHB1CR0
556 * | B1 |
557 * | |
558 * B1 start address --> -------- <-- FLSHA2CR0
559 * | A2 |
560 * | |
561 * A2 start address --> -------- <-- FLSHA1CR0
562 * | A1 |
563 * | |
564 * A1 start address --> -------- (Lower address)
565 *
566 *
567 * Start base address defines the starting address range for given CS and
568 * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS.
569 *
570 * But, different targets are having different combinations of number of CS,
571 * some targets only have single CS or two CS covering controller's full
572 * memory mapped space area.
573 * Thus, implementation is being done as independent of the size and number
574 * of the connected slave device.
575 * Assign controller memory mapped space size as the size to the connected
576 * slave device.
577 * Mark FLSHxxCR0 as zero initially and then assign value only to the selected
578 * chip-select Flash configuration register.
579 *
580 * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the
581 * memory mapped size of the controller.
582 * Value for rest of the CS FLSHxxCR0 register would be zero.
583 *
584 */
585static void nxp_fspi_select_mem(struct nxp_fspi *f, int chip_select)
586{
587 u64 size_kb;
588
589 /* Reset FLSHxxCR0 registers */
590 fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0);
591 fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0);
592 fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0);
593 fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0);
594
595 /* Assign controller memory mapped space as size, KBytes, of flash. */
596 size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);
597
598 fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
599 4 * chip_select);
600
601 dev_dbg(f->dev, "Slave device [CS:%x] selected\n", chip_select);
602}
603
604static void nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
605{
606 u32 len = op->data.nbytes;
607
608 /* Read out the data directly from the AHB buffer. */
609 memcpy_fromio(op->data.buf.in, (f->ahb_addr + op->addr.val), len);
610}
611
612static void nxp_fspi_fill_txfifo(struct nxp_fspi *f,
613 const struct spi_mem_op *op)
614{
615 void __iomem *base = f->iobase;
616 int i, ret;
617 u8 *buf = (u8 *)op->data.buf.out;
618
619 /* clear the TX FIFO. */
620 fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR);
621
622 /*
623 * Default value of water mark level is 8 bytes, hence in single
624 * write request controller can write max 8 bytes of data.
625 */
626
627 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) {
628 /* Wait for TXFIFO empty */
629 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
630 FSPI_INTR_IPTXWE, 0,
631 POLL_TOUT, true);
632 WARN_ON(ret);
633
634 fspi_writel(f, *(u32 *)(buf + i), base + FSPI_TFDR);
635 fspi_writel(f, *(u32 *)(buf + i + 4), base + FSPI_TFDR + 4);
636 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
637 }
638
639 if (i < op->data.nbytes) {
640 u32 data = 0;
641 int j;
642 /* Wait for TXFIFO empty */
643 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
644 FSPI_INTR_IPTXWE, 0,
645 POLL_TOUT, true);
646 WARN_ON(ret);
647
648 for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) {
649 memcpy(&data, buf + i + j, 4);
650 fspi_writel(f, data, base + FSPI_TFDR + j);
651 }
652 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
653 }
654}
655
656static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
657 const struct spi_mem_op *op)
658{
659 void __iomem *base = f->iobase;
660 int i, ret;
661 int len = op->data.nbytes;
662 u8 *buf = (u8 *)op->data.buf.in;
663
664 /*
665 * Default value of water mark level is 8 bytes, hence in single
666 * read request controller can read max 8 bytes of data.
667 */
668 for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) {
669 /* Wait for RXFIFO available */
670 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
671 FSPI_INTR_IPRXWA, 0,
672 POLL_TOUT, true);
673 WARN_ON(ret);
674
675 *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR);
676 *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4);
677 /* move the FIFO pointer */
678 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
679 }
680
681 if (i < len) {
682 u32 tmp;
683 int size, j;
684
685 buf = op->data.buf.in + i;
686 /* Wait for RXFIFO available */
687 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
688 FSPI_INTR_IPRXWA, 0,
689 POLL_TOUT, true);
690 WARN_ON(ret);
691
692 len = op->data.nbytes - i;
693 for (j = 0; j < op->data.nbytes - i; j += 4) {
694 tmp = fspi_readl(f, base + FSPI_RFDR + j);
695 size = min(len, 4);
696 memcpy(buf + j, &tmp, size);
697 len -= size;
698 }
699 }
700
701 /* invalid the RXFIFO */
702 fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR);
703 /* move the FIFO pointer */
704 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
705}
706
707static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
708{
709 void __iomem *base = f->iobase;
710 int seqnum = 0;
711 int err = 0;
712 u32 reg;
713
714 reg = fspi_readl(f, base + FSPI_IPRXFCR);
715 /* invalid RXFIFO first */
716 reg &= ~FSPI_IPRXFCR_DMA_EN;
717 reg = reg | FSPI_IPRXFCR_CLR;
718 fspi_writel(f, reg, base + FSPI_IPRXFCR);
719
720 fspi_writel(f, op->addr.val, base + FSPI_IPCR0);
721 /*
722 * Always start the sequence at the same index since we update
723 * the LUT at each exec_op() call. And also specify the DATA
724 * length, since it's has not been specified in the LUT.
725 */
726 fspi_writel(f, op->data.nbytes |
727 (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
728 (seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
729 base + FSPI_IPCR1);
730
731 /* Trigger the LUT now. */
732 fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD);
733
734 /* Wait for the completion. */
735 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
736 FSPI_STS0_ARB_IDLE, 1, 1000 * 1000, true);
737
738 /* Invoke IP data read, if request is of data read. */
739 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
740 nxp_fspi_read_rxfifo(f, op);
741
742 return err;
743}
744
745static int nxp_fspi_exec_op(struct spi_slave *slave,
746 const struct spi_mem_op *op)
747{
748 struct nxp_fspi *f;
749 struct udevice *bus;
750 int err = 0;
751
752 bus = slave->dev->parent;
753 f = dev_get_priv(bus);
754
755 /* Wait for controller being ready. */
756 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
757 FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
758 WARN_ON(err);
759
760 nxp_fspi_prepare_lut(f, op);
761 /*
762 * If we have large chunks of data, we read them through the AHB bus
763 * by accessing the mapped memory. In all other cases we use
764 * IP commands to access the flash.
765 */
766 if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
767 op->data.dir == SPI_MEM_DATA_IN) {
768 nxp_fspi_read_ahb(f, op);
769 } else {
770 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
771 nxp_fspi_fill_txfifo(f, op);
772
773 err = nxp_fspi_do_op(f, op);
774 }
775
776 /* Invalidate the data in the AHB buffer. */
777 nxp_fspi_invalid(f);
778
779 return err;
780}
781
782static int nxp_fspi_adjust_op_size(struct spi_slave *slave,
783 struct spi_mem_op *op)
784{
785 struct nxp_fspi *f;
786 struct udevice *bus;
787
788 bus = slave->dev->parent;
789 f = dev_get_priv(bus);
790
791 if (op->data.dir == SPI_MEM_DATA_OUT) {
792 if (op->data.nbytes > f->devtype_data->txfifo)
793 op->data.nbytes = f->devtype_data->txfifo;
794 } else {
795 if (op->data.nbytes > f->devtype_data->ahb_buf_size)
796 op->data.nbytes = f->devtype_data->ahb_buf_size;
797 else if (op->data.nbytes > (f->devtype_data->rxfifo - 4))
798 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
799 }
800
801 return 0;
802}
803
804static int nxp_fspi_default_setup(struct nxp_fspi *f)
805{
806 void __iomem *base = f->iobase;
807 int ret, i;
808 u32 reg;
809
810#if CONFIG_IS_ENABLED(CONFIG_CLK)
811 /* disable and unprepare clock to avoid glitch pass to controller */
812 nxp_fspi_clk_disable_unprep(f);
813
814 /* the default frequency, we will change it later if necessary. */
815 ret = clk_set_rate(&f->clk, 20000000);
816 if (ret)
817 return ret;
818
819 ret = nxp_fspi_clk_prep_enable(f);
820 if (ret)
821 return ret;
822#endif
823
824 /* Reset the module */
825 /* w1c register, wait unit clear */
826 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
827 FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
828 WARN_ON(ret);
829
830 /* Disable the module */
831 fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
832
833 /* Reset the DLL register to default value */
834 fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
835 fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
836
837 /* enable module */
838 fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | FSPI_MCR0_IP_TIMEOUT(0xFF),
839 base + FSPI_MCR0);
840
841 /*
842 * Disable same device enable bit and configure all slave devices
843 * independently.
844 */
845 reg = fspi_readl(f, f->iobase + FSPI_MCR2);
846 reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);
847 fspi_writel(f, reg, base + FSPI_MCR2);
848
849 /* AHB configuration for access buffer 0~7. */
850 for (i = 0; i < 7; i++)
851 fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i);
852
853 /*
854 * Set ADATSZ with the maximum AHB buffer size to improve the read
855 * performance.
856 */
857 fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 |
858 FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0);
859
860 /* prefetch and no start address alignment limitation */
861 fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
862 base + FSPI_AHBCR);
863
864 /* AHB Read - Set lut sequence ID for all CS. */
865 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
866 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);
867 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2);
868 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2);
869
870 return 0;
871}
872
873static int nxp_fspi_probe(struct udevice *bus)
874{
875 struct nxp_fspi *f = dev_get_priv(bus);
876
877 f->devtype_data =
878 (struct nxp_fspi_devtype_data *)dev_get_driver_data(bus);
879 nxp_fspi_default_setup(f);
880
881 return 0;
882}
883
884static int nxp_fspi_claim_bus(struct udevice *dev)
885{
886 struct nxp_fspi *f;
887 struct udevice *bus;
888 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
889
890 bus = dev->parent;
891 f = dev_get_priv(bus);
892
893 nxp_fspi_select_mem(f, slave_plat->cs);
894
895 return 0;
896}
897
898static int nxp_fspi_set_speed(struct udevice *bus, uint speed)
899{
900#if CONFIG_IS_ENABLED(CONFIG_CLK)
901 struct nxp_fspi *f = dev_get_priv(bus);
902 int ret;
903
904 nxp_fspi_clk_disable_unprep(f);
905
906 ret = clk_set_rate(&f->clk, speed);
907 if (ret)
908 return ret;
909
910 ret = nxp_fspi_clk_prep_enable(f);
911 if (ret)
912 return ret;
913#endif
914 return 0;
915}
916
917static int nxp_fspi_set_mode(struct udevice *bus, uint mode)
918{
919 /* Nothing to do */
920 return 0;
921}
922
923static int nxp_fspi_ofdata_to_platdata(struct udevice *bus)
924{
925 struct nxp_fspi *f = dev_get_priv(bus);
926#if CONFIG_IS_ENABLED(CONFIG_CLK)
927 int ret;
928#endif
929
930 fdt_addr_t iobase;
931 fdt_addr_t iobase_size;
932 fdt_addr_t ahb_addr;
933 fdt_addr_t ahb_size;
934
935 f->dev = bus;
936
937 iobase = devfdt_get_addr_size_name(bus, "fspi_base", &iobase_size);
938 if (iobase == FDT_ADDR_T_NONE) {
939 dev_err(bus, "fspi_base regs missing\n");
940 return -ENODEV;
941 }
942 f->iobase = map_physmem(iobase, iobase_size, MAP_NOCACHE);
943
944 ahb_addr = devfdt_get_addr_size_name(bus, "fspi_mmap", &ahb_size);
945 if (ahb_addr == FDT_ADDR_T_NONE) {
946 dev_err(bus, "fspi_mmap regs missing\n");
947 return -ENODEV;
948 }
949 f->ahb_addr = map_physmem(ahb_addr, ahb_size, MAP_NOCACHE);
950 f->memmap_phy_size = ahb_size;
951
952#if CONFIG_IS_ENABLED(CONFIG_CLK)
953 ret = clk_get_by_name(bus, "fspi_en", &f->clk_en);
954 if (ret) {
955 dev_err(bus, "failed to get fspi_en clock\n");
956 return ret;
957 }
958
959 ret = clk_get_by_name(bus, "fspi", &f->clk);
960 if (ret) {
961 dev_err(bus, "failed to get fspi clock\n");
962 return ret;
963 }
964#endif
965
966 dev_dbg(bus, "iobase=<0x%llx>, ahb_addr=<0x%llx>\n", iobase, ahb_addr);
967
968 return 0;
969}
970
971static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
972 .adjust_op_size = nxp_fspi_adjust_op_size,
973 .supports_op = nxp_fspi_supports_op,
974 .exec_op = nxp_fspi_exec_op,
975};
976
977static const struct dm_spi_ops nxp_fspi_ops = {
978 .claim_bus = nxp_fspi_claim_bus,
979 .set_speed = nxp_fspi_set_speed,
980 .set_mode = nxp_fspi_set_mode,
981 .mem_ops = &nxp_fspi_mem_ops,
982};
983
984static const struct udevice_id nxp_fspi_ids[] = {
985 { .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, },
986 { }
987};
988
989U_BOOT_DRIVER(nxp_fspi) = {
990 .name = "nxp_fspi",
991 .id = UCLASS_SPI,
992 .of_match = nxp_fspi_ids,
993 .ops = &nxp_fspi_ops,
994 .ofdata_to_platdata = nxp_fspi_ofdata_to_platdata,
995 .priv_auto_alloc_size = sizeof(struct nxp_fspi),
996 .probe = nxp_fspi_probe,
997};