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wdenkf8cac652002-08-26 22:36:39 +00001/*
2 * (C) Copyright 2001
3 * Paul Geerinckx
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <mpc8xx.h>
26#include "atm.h"
27#include <i2c.h>
28
29/* ------------------------------------------------------------------------- */
30
31static long int dram_size (long int, long int *, long int);
32
33/* ------------------------------------------------------------------------- */
34
35/* used PLD registers */
36# define PLD_GCR1_REG (unsigned char *) (0x10000000 + 0)
37# define PLD_EXT_RES (unsigned char *) (0x10000000 + 10)
38# define PLD_EXT_FETH (unsigned char *) (0x10000000 + 11)
39# define PLD_EXT_LED (unsigned char *) (0x10000000 + 12)
40# define PLD_EXT_X21 (unsigned char *) (0x10000000 + 13)
41
42#define _NOT_USED_ 0xFFFFFFFF
43
wdenkc83bf6a2004-01-06 22:38:14 +000044const uint sdram_table[] = {
wdenkf8cac652002-08-26 22:36:39 +000045 /*
46 * Single Read. (Offset 0 in UPMA RAM)
47 */
wdenkc83bf6a2004-01-06 22:38:14 +000048 0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47, /* last */
wdenkf8cac652002-08-26 22:36:39 +000049 _NOT_USED_,
50 /*
51 * SDRAM Initialization (offset 5 in UPMA RAM)
52 *
53 * This is no UPM entry point. The following definition uses
54 * the remaining space to establish an initialization
55 * sequence, which is executed by a RUN command.
56 *
57 */
wdenkc83bf6a2004-01-06 22:38:14 +000058 0xFFFAF834, 0xFFE5B435, /* last */
59 _NOT_USED_,
wdenkf8cac652002-08-26 22:36:39 +000060 /*
61 * Burst Read. (Offset 8 in UPMA RAM)
62 */
63 0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00,
wdenkc83bf6a2004-01-06 22:38:14 +000064 0xF0AFFC00, 0xF0AAF800, 0xF1A5E447, /* last */
65 _NOT_USED_,
wdenkf8cac652002-08-26 22:36:39 +000066 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
67 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
68 /*
69 * Single Write. (Offset 18 in UPMA RAM)
70 */
wdenkc83bf6a2004-01-06 22:38:14 +000071 0xFE29B300, 0xF1A27304, 0xFFA5F747, /* last */
72 _NOT_USED_,
wdenkf8cac652002-08-26 22:36:39 +000073 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
74 /*
75 * Burst Write. (Offset 20 in UPMA RAM)
76 */
77 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
wdenkc83bf6a2004-01-06 22:38:14 +000078 0xF1AAF804, 0xFFA5F447, /* last */
79 _NOT_USED_, _NOT_USED_,
wdenkf8cac652002-08-26 22:36:39 +000080 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
81 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
82 /*
83 * Refresh (Offset 30 in UPMA RAM)
84 */
85 0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84,
wdenkc83bf6a2004-01-06 22:38:14 +000086 0xFFAFFC07, /* last */
87 _NOT_USED_, _NOT_USED_, _NOT_USED_,
wdenkf8cac652002-08-26 22:36:39 +000088 /*
89 * MRS sequence (Offset 38 in UPMA RAM)
90 */
wdenkc83bf6a2004-01-06 22:38:14 +000091 0xFFAAB834, 0xFFA57434, 0xFFAFFC05, /* last */
92 _NOT_USED_,
wdenkf8cac652002-08-26 22:36:39 +000093 /*
94 * Exception. (Offset 3c in UPMA RAM)
95 */
wdenkc83bf6a2004-01-06 22:38:14 +000096 0xFFAFFC04, 0xFFAFFC05, /* last */
97 _NOT_USED_, _NOT_USED_,
wdenkf8cac652002-08-26 22:36:39 +000098};
99
100/* ------------------------------------------------------------------------- */
101
102
Becky Bruce9973e3c2008-06-09 16:03:40 -0500103phys_size_t initdram (int board_type)
wdenkf8cac652002-08-26 22:36:39 +0000104{
wdenkc83bf6a2004-01-06 22:38:14 +0000105 volatile immap_t *immap = (immap_t *) CFG_IMMR;
106 volatile memctl8xx_t *memctl = &immap->im_memctl;
107 volatile iop8xx_t *iop = &immap->im_ioport;
108 volatile fec_t *fecp = &immap->im_cpm.cp_fec;
109 long int size;
wdenkf8cac652002-08-26 22:36:39 +0000110
wdenkc83bf6a2004-01-06 22:38:14 +0000111 upmconfig (UPMA, (uint *) sdram_table,
112 sizeof (sdram_table) / sizeof (uint));
wdenkf8cac652002-08-26 22:36:39 +0000113
wdenkc83bf6a2004-01-06 22:38:14 +0000114 /*
115 * Preliminary prescaler for refresh (depends on number of
116 * banks): This value is selected for four cycles every 62.4 us
117 * with two SDRAM banks or four cycles every 31.2 us with one
118 * bank. It will be adjusted after memory sizing.
119 */
120 memctl->memc_mptpr = CFG_MPTPR;
wdenkf8cac652002-08-26 22:36:39 +0000121
wdenkc83bf6a2004-01-06 22:38:14 +0000122 memctl->memc_mar = 0x00000088;
wdenkf8cac652002-08-26 22:36:39 +0000123
wdenkc83bf6a2004-01-06 22:38:14 +0000124 /*
125 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
126 * preliminary addresses - these have to be modified after the
127 * SDRAM size has been determined.
128 */
129 memctl->memc_or2 = CFG_OR2_PRELIM;
130 memctl->memc_br2 = CFG_BR2_PRELIM;
wdenkf8cac652002-08-26 22:36:39 +0000131
wdenkc83bf6a2004-01-06 22:38:14 +0000132 memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
wdenkf8cac652002-08-26 22:36:39 +0000133
wdenkc83bf6a2004-01-06 22:38:14 +0000134 udelay (200);
wdenkf8cac652002-08-26 22:36:39 +0000135
wdenkc83bf6a2004-01-06 22:38:14 +0000136 /* perform SDRAM initializsation sequence */
wdenkf8cac652002-08-26 22:36:39 +0000137
wdenkc83bf6a2004-01-06 22:38:14 +0000138 memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
139 udelay (1);
140 memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
141 udelay (1);
wdenkf8cac652002-08-26 22:36:39 +0000142
wdenkc83bf6a2004-01-06 22:38:14 +0000143 memctl->memc_mcr = 0x80004105; /* SDRAM precharge */
144 udelay (1);
145 memctl->memc_mcr = 0x80004030; /* SDRAM 16x autorefresh */
146 udelay (1);
147 memctl->memc_mcr = 0x80004138; /* SDRAM upload parameters */
148 udelay (1);
wdenkf8cac652002-08-26 22:36:39 +0000149
wdenkc83bf6a2004-01-06 22:38:14 +0000150 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
wdenkf8cac652002-08-26 22:36:39 +0000151
wdenkc83bf6a2004-01-06 22:38:14 +0000152 udelay (1000);
wdenkf8cac652002-08-26 22:36:39 +0000153
wdenkc83bf6a2004-01-06 22:38:14 +0000154 /*
155 * Check Bank 0 Memory Size for re-configuration
156 *
157 */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200158 size = dram_size (CFG_MAMR, (long *) SDRAM_BASE_PRELIM,
wdenkc83bf6a2004-01-06 22:38:14 +0000159 SDRAM_MAX_SIZE);
wdenkf8cac652002-08-26 22:36:39 +0000160
wdenkc83bf6a2004-01-06 22:38:14 +0000161 udelay (1000);
wdenkf8cac652002-08-26 22:36:39 +0000162
163
wdenkc83bf6a2004-01-06 22:38:14 +0000164 memctl->memc_mamr = CFG_MAMR;
165 udelay (1000);
wdenkf8cac652002-08-26 22:36:39 +0000166
wdenkc83bf6a2004-01-06 22:38:14 +0000167 /*
168 * Final mapping
169 */
170 memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM;
171 memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
wdenkf8cac652002-08-26 22:36:39 +0000172
wdenkc83bf6a2004-01-06 22:38:14 +0000173 udelay (10000);
wdenkf8cac652002-08-26 22:36:39 +0000174
wdenkc83bf6a2004-01-06 22:38:14 +0000175 /* prepare pin multiplexing for fast ethernet */
wdenkf8cac652002-08-26 22:36:39 +0000176
wdenkc83bf6a2004-01-06 22:38:14 +0000177 atmLoad ();
178 fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
179 iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
wdenkf8cac652002-08-26 22:36:39 +0000180
181
wdenkc83bf6a2004-01-06 22:38:14 +0000182 return (size);
wdenkf8cac652002-08-26 22:36:39 +0000183}
184
185/* ------------------------------------------------------------------------- */
186
187/*
188 * Check memory range for valid RAM. A simple memory test determines
189 * the actually available RAM size between addresses `base' and
190 * `base + maxsize'. Some (not all) hardware errors are detected:
191 * - short between address lines
192 * - short between data lines
193 */
194
wdenkc83bf6a2004-01-06 22:38:14 +0000195static long int dram_size (long int mamr_value, long int *base,
196 long int maxsize)
wdenkf8cac652002-08-26 22:36:39 +0000197{
wdenkc83bf6a2004-01-06 22:38:14 +0000198 volatile immap_t *immap = (immap_t *) CFG_IMMR;
199 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenkf8cac652002-08-26 22:36:39 +0000200
wdenkc83bf6a2004-01-06 22:38:14 +0000201 memctl->memc_mamr = mamr_value;
wdenkf8cac652002-08-26 22:36:39 +0000202
wdenkc83bf6a2004-01-06 22:38:14 +0000203 return (get_ram_size (base, maxsize));
wdenkf8cac652002-08-26 22:36:39 +0000204}
205
206/*
207 * Check Board Identity:
208 */
209
210int checkboard (void)
211{
wdenkc83bf6a2004-01-06 22:38:14 +0000212 return (0);
wdenkf8cac652002-08-26 22:36:39 +0000213}
214
wdenkc83bf6a2004-01-06 22:38:14 +0000215void board_serial_init (void)
wdenkf8cac652002-08-26 22:36:39 +0000216{
wdenkc83bf6a2004-01-06 22:38:14 +0000217 ; /* nothing to do here */
wdenkf8cac652002-08-26 22:36:39 +0000218}
219
wdenkc83bf6a2004-01-06 22:38:14 +0000220void board_ether_init (void)
wdenkf8cac652002-08-26 22:36:39 +0000221{
wdenkc83bf6a2004-01-06 22:38:14 +0000222 volatile immap_t *immap = (immap_t *) CFG_IMMR;
223 volatile iop8xx_t *iop = &immap->im_ioport;
224 volatile fec_t *fecp = &immap->im_cpm.cp_fec;
wdenkf8cac652002-08-26 22:36:39 +0000225
wdenkc83bf6a2004-01-06 22:38:14 +0000226 atmLoad ();
227 fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
228 iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
wdenkf8cac652002-08-26 22:36:39 +0000229}
230
wdenkc837dcb2004-01-20 23:12:12 +0000231int board_early_init_f (void)
wdenkf8cac652002-08-26 22:36:39 +0000232{
wdenkc83bf6a2004-01-06 22:38:14 +0000233 volatile immap_t *immap = (immap_t *) CFG_IMMR;
234 volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
235 volatile memctl8xx_t *memctl = &immap->im_memctl;
236 volatile iop8xx_t *iop = &immap->im_ioport;
wdenkf8cac652002-08-26 22:36:39 +0000237
wdenkc83bf6a2004-01-06 22:38:14 +0000238 /* configure the LED timing output pins - port A pin 4 */
239 iop->iop_papar = 0x0800;
240 iop->iop_padir = 0x0800;
wdenkf8cac652002-08-26 22:36:39 +0000241
wdenkc83bf6a2004-01-06 22:38:14 +0000242 /* start timer 2 for the 4hz LED blink rate */
243 timers->cpmt_tmr2 = 0xff2c; /* 4hz for 64mhz */
244 timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */
245 timers->cpmt_tgcr = 0x00000810; /* run timer 2 */
wdenkf8cac652002-08-26 22:36:39 +0000246
wdenkc83bf6a2004-01-06 22:38:14 +0000247 /* chip select for PLD access */
248 memctl->memc_br6 = 0x10000401;
249 memctl->memc_or6 = 0xFC000908;
wdenkf8cac652002-08-26 22:36:39 +0000250
wdenkc83bf6a2004-01-06 22:38:14 +0000251 /* PLD initial values ( set LEDs, remove reset on LXT) */
wdenkf8cac652002-08-26 22:36:39 +0000252
wdenkc83bf6a2004-01-06 22:38:14 +0000253 *PLD_GCR1_REG = 0x06;
254 *PLD_EXT_RES = 0xC0;
255 *PLD_EXT_FETH = 0x40;
256 *PLD_EXT_LED = 0xFF;
257 *PLD_EXT_X21 = 0x04;
258 return 0;
wdenkf8cac652002-08-26 22:36:39 +0000259}
260
wdenkc83bf6a2004-01-06 22:38:14 +0000261void board_get_enetaddr (uchar * addr)
wdenkf8cac652002-08-26 22:36:39 +0000262{
wdenkc83bf6a2004-01-06 22:38:14 +0000263 int i;
264 volatile immap_t *immap = (immap_t *) CFG_IMMR;
265 volatile cpm8xx_t *cpm = &immap->im_cpm;
266 unsigned int rccrtmp;
wdenkf8cac652002-08-26 22:36:39 +0000267
wdenkc83bf6a2004-01-06 22:38:14 +0000268 char default_mac_addr[] = { 0x00, 0x08, 0x01, 0x02, 0x03, 0x04 };
wdenkf8cac652002-08-26 22:36:39 +0000269
wdenkc83bf6a2004-01-06 22:38:14 +0000270 for (i = 0; i < 6; i++)
271 addr[i] = default_mac_addr[i];
wdenkf8cac652002-08-26 22:36:39 +0000272
wdenkc83bf6a2004-01-06 22:38:14 +0000273 printf ("There is an error in the i2c driver .. /n");
274 printf ("You need to fix it first....../n");
wdenkf8cac652002-08-26 22:36:39 +0000275
wdenkc83bf6a2004-01-06 22:38:14 +0000276 rccrtmp = cpm->cp_rccr;
277 cpm->cp_rccr |= 0x0020;
wdenkf8cac652002-08-26 22:36:39 +0000278
wdenkc83bf6a2004-01-06 22:38:14 +0000279 i2c_reg_read (0xa0, 0);
280 printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
281 i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
282 i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
283 i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0));
wdenkf8cac652002-08-26 22:36:39 +0000284
wdenkc83bf6a2004-01-06 22:38:14 +0000285 cpm->cp_rccr = rccrtmp;
wdenkf8cac652002-08-26 22:36:39 +0000286}