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wdenk5c952cf2004-10-10 21:27:30 +00001/*
2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*------------------------------------------------------------------------
28 * BOARD/CPU
29 *----------------------------------------------------------------------*/
30#define CONFIG_PK1C20 1 /* PK1C20 board */
31#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
32
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */
34#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
35#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */
wdenk5c952cf2004-10-10 21:27:30 +000036#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
37
38/*------------------------------------------------------------------------
39 * CACHE -- the following will support II/s and II/f. The II/s does not
40 * have dcache, so the cache instructions will behave as NOPs.
41 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */
43#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */
44#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
45#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
wdenk5c952cf2004-10-10 21:27:30 +000046
47/*------------------------------------------------------------------------
48 * MEMORY BASE ADDRESSES
49 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */
51#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
52#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */
53#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */
54#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */
55#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/
wdenk5c952cf2004-10-10 21:27:30 +000056
57/*------------------------------------------------------------------------
58 * MEMORY ORGANIZATION
59 * -Monitor at top.
60 * -The heap is placed below the monitor.
61 * -Global data is placed below the heap.
62 * -The stack is placed below global data (&grows down).
63 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 128k */
65#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/
66#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenk5c952cf2004-10-10 21:27:30 +000067
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
69#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
70#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
71#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
wdenk5c952cf2004-10-10 21:27:30 +000072
73/*------------------------------------------------------------------------
74 * FLASH (AM29LV065D)
75 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */
77#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */
78#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
79#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
80#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */
wdenk5c952cf2004-10-10 21:27:30 +000081
82/*------------------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083 * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
84 * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
wdenk5c952cf2004-10-10 21:27:30 +000085 * reset address, no? This will keep the environment in user region
86 * of flash. NOTE: the monitor length must be multiple of sector size
87 * (which is common practice).
88 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020089#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020090#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
wdenk5c952cf2004-10-10 21:27:30 +000091#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
wdenk5c952cf2004-10-10 21:27:30 +000093
94/*------------------------------------------------------------------------
95 * CONSOLE
96 *----------------------------------------------------------------------*/
Scott McNuttc9d4f462010-03-19 19:03:28 -040097#define CONFIG_ALTERA_UART 1 /* Use altera uart */
98#if defined(CONFIG_ALTERA_JTAG_UART)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
wdenk5c952cf2004-10-10 21:27:30 +0000100#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
wdenk5c952cf2004-10-10 21:27:30 +0000102#endif
103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
wdenk5c952cf2004-10-10 21:27:30 +0000105#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
wdenk5c952cf2004-10-10 21:27:30 +0000107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
wdenk5c952cf2004-10-10 21:27:30 +0000109
110/*------------------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111 * EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for
wdenk0c1c117c2005-03-30 23:28:18 +0000112 * epcs device access is enabled. The base address is the epcs
113 * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
Scott McNutt3d22d0b2006-06-08 12:03:21 -0400114 * The register base is currently at offset 0x600 from the memory base.
wdenk0c1c117c2005-03-30 23:28:18 +0000115 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_NIOS_EPCSBASE 0x02100200 /* EPCS register base */
wdenk0c1c117c2005-03-30 23:28:18 +0000117
118/*------------------------------------------------------------------------
wdenk5c952cf2004-10-10 21:27:30 +0000119 * DEBUG
120 *----------------------------------------------------------------------*/
121#undef CONFIG_ROM_STUBS /* Stubs not in ROM */
122
123/*------------------------------------------------------------------------
124 * TIMEBASE --
125 *
126 * The high res timer defaults to 1 msec. Since it includes the period
Scott McNutt3a89a912010-03-30 20:23:04 -0400127 * registers, the interrupt frequency can be reduced using TMRCNT.
128 * If the default period is acceptable, TMRCNT can be left undefined.
129 * TMRMS represents the desired mecs per tick (msecs per interrupt).
wdenk5c952cf2004-10-10 21:27:30 +0000130 *----------------------------------------------------------------------*/
Scott McNutt3a89a912010-03-30 20:23:04 -0400131#define CONFIG_SYS_HZ 1000 /* Always 1000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
Scott McNutt3a89a912010-03-30 20:23:04 -0400133#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
134#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period */
135#define CONFIG_SYS_NIOS_TMRCNT \
136 (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
wdenk5c952cf2004-10-10 21:27:30 +0000137
138/*------------------------------------------------------------------------
139 * STATUS LED -- Provides a simple blinking led. For Nios2 each board
140 * must implement its own led routines -- leds are, after all,
141 * board-specific, no?
142 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
wdenk5c952cf2004-10-10 21:27:30 +0000144#define CONFIG_STATUS_LED /* Enable status driver */
145
146#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
147#define STATUS_LED_STATE 1 /* Blinking */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */
wdenk5c952cf2004-10-10 21:27:30 +0000149
150/*------------------------------------------------------------------------
151 * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
152 * and really doesn't need any additional clutter. So I choose the lazy
153 * way out to avoid changes there -- define the base address to ensure
154 * cache bypass so there's no need to monkey with inx/outx macros.
155 *----------------------------------------------------------------------*/
Scott McNutt3d22d0b2006-06-08 12:03:21 -0400156#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
Ben Warren7194ab82009-10-04 22:37:03 -0700157#define CONFIG_NET_MULTI
158#define CONFIG_SMC91111 /* Using SMC91c111 */
wdenk5c952cf2004-10-10 21:27:30 +0000159#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
160#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
161
162#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
163#define CONFIG_NETMASK 255.255.255.0
164#define CONFIG_IPADDR 192.168.2.21
165#define CONFIG_SERVERIP 192.168.2.16
166
Jon Loeligeracf02692007-07-08 14:49:44 -0500167
168/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500169 * BOOTP options
170 */
171#define CONFIG_BOOTP_BOOTFILESIZE
172#define CONFIG_BOOTP_BOOTPATH
173#define CONFIG_BOOTP_GATEWAY
174#define CONFIG_BOOTP_HOSTNAME
175
176
177/*
Jon Loeligeracf02692007-07-08 14:49:44 -0500178 * Command line configuration.
179 */
180
181#define CONFIG_CMD_BDI
182#define CONFIG_CMD_DHCP
183#define CONFIG_CMD_ECHO
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500184#define CONFIG_CMD_SAVEENV
Jon Loeligeracf02692007-07-08 14:49:44 -0500185#define CONFIG_CMD_FLASH
186#define CONFIG_CMD_IMI
187#define CONFIG_CMD_IRQ
188#define CONFIG_CMD_LOADS
189#define CONFIG_CMD_LOADB
190#define CONFIG_CMD_MEMORY
191#define CONFIG_CMD_MISC
192#define CONFIG_CMD_NET
193#define CONFIG_CMD_PING
194#define CONFIG_CMD_RUN
195#define CONFIG_CMD_SAVES
196
wdenk5c952cf2004-10-10 21:27:30 +0000197
198/*------------------------------------------------------------------------
wdenk0c1c117c2005-03-30 23:28:18 +0000199 * COMPACT FLASH
200 *----------------------------------------------------------------------*/
Jon Loeligeracf02692007-07-08 14:49:44 -0500201#if defined(CONFIG_CMD_IDE)
wdenk0c1c117c2005-03-30 23:28:18 +0000202#define CONFIG_IDE_PREINIT /* Implement id_preinit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */
204#define CONFIG_SYS_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */
wdenk0c1c117c2005-03-30 23:28:18 +0000205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_ATA_BASE_ADDR 0x00900800 /* ATA base addr */
207#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */
208#define CONFIG_SYS_ATA_DATA_OFFSET 0x0040 /* Data IO offset */
209#define CONFIG_SYS_ATA_REG_OFFSET 0x0040 /* Register offset */
210#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */
211#define CONFIG_SYS_ATA_STRIDE 4 /* Width betwix addrs */
wdenk0c1c117c2005-03-30 23:28:18 +0000212#define CONFIG_DOS_PARTITION
213
214/* Board-specific cf regs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_CF_PRESENT 0x00900880 /* CF Present PIO base */
216#define CONFIG_SYS_CF_POWER 0x00900890 /* CF Power FET PIO base*/
217#define CONFIG_SYS_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */
wdenk0c1c117c2005-03-30 23:28:18 +0000218
Jon Loeligeracf02692007-07-08 14:49:44 -0500219#endif
wdenk0c1c117c2005-03-30 23:28:18 +0000220
221/*------------------------------------------------------------------------
222 * JFFS2
223 *----------------------------------------------------------------------*/
Jon Loeligeracf02692007-07-08 14:49:44 -0500224#if defined(CONFIG_CMD_JFFS2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_JFFS_CUSTOM_PART /* board defined part */
wdenk0c1c117c2005-03-30 23:28:18 +0000226#endif
227
228/*------------------------------------------------------------------------
wdenk5c952cf2004-10-10 21:27:30 +0000229 * MISC
230 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_LONGHELP /* Provide extended help*/
232#define CONFIG_SYS_PROMPT "==> " /* Command prompt */
233#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
234#define CONFIG_SYS_MAXARGS 16 /* Max command args */
235#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */
236#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
237#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */
238#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */
239#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000
wdenk5c952cf2004-10-10 21:27:30 +0000240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_HUSH_PARSER
242#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk0c1c117c2005-03-30 23:28:18 +0000243
wdenk5c952cf2004-10-10 21:27:30 +0000244#endif /* __CONFIG_H */