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Ilko Ilievf0a2c7b2009-04-16 21:30:48 +02001/*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
6 *
7 * Configuation settings for the RONETIX PM9263 board.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/* ARM asynchronous clock */
Jean-Christophe PLAGNIOL-VILLARDb2403582009-05-31 14:53:18 +020032#define CONFIG_DISPLAY_CPUINFO
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020033#define CONFIG_DISPLAY_BOARDINFO
34
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020035#define MASTER_PLL_DIV 6
36#define MASTER_PLL_MUL 65
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020037#define MAIN_PLL_DIV 2 /* 2 or 4 */
Achim Ehrlich7c966a82010-02-24 10:29:16 +010038#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020039
Jean-Christophe PLAGNIOL-VILLARD6ebff362009-04-16 21:30:48 +020040#define CONFIG_SYS_HZ 1000
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020041
42#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
43#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
44#define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
45#define CONFIG_ARCH_CPU_INIT
46#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
47
48/* clocks */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020049#define CONFIG_SYS_MOR_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030050 (AT91_PMC_MOR_MOSCEN | \
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020051 (255 << 8)) /* Main Oscillator Start-up Time */
52#define CONFIG_SYS_PLLAR_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030053 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
54 AT91_PMC_PLLXR_OUT(3) | \
55 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020056 (2 << 28) | /* PLL Clock Frequency Range */ \
57 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020058
59#if (MAIN_PLL_DIV == 2)
60/* PCK/2 = MCK Master Clock from PLLA */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020061#define CONFIG_SYS_MCKR1_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030062 (AT91_PMC_MCKR_CSS_SLOW | \
63 AT91_PMC_MCKR_PRES_1 | \
64 AT91_PMC_MCKR_MDIV_2)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020065/* PCK/2 = MCK Master Clock from PLLA */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020066#define CONFIG_SYS_MCKR2_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030067 (AT91_PMC_MCKR_CSS_PLLA | \
68 AT91_PMC_MCKR_PRES_1 | \
69 AT91_PMC_MCKR_MDIV_2)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020070#else
71/* PCK/4 = MCK Master Clock from PLLA */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020072#define CONFIG_SYS_MCKR1_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030073 (AT91_PMC_MCKR_CSS_SLOW | \
74 AT91_PMC_MCKR_PRES_1 | \
75 AT91_PMC_MCKR_MDIV_4)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020076/* PCK/4 = MCK Master Clock from PLLA */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020077#define CONFIG_SYS_MCKR2_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030078 (AT91_PMC_MCKR_CSS_PLLA | \
79 AT91_PMC_MCKR_PRES_1 | \
80 AT91_PMC_MCKR_MDIV_4)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020081#endif
82/* define PDC[31:16] as DATA[31:16] */
83#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
84/* no pull-up for D[31:16] */
85#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
86/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020087#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030088 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
89 AT91_MATRIX_CSA_EBI_CS1A)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020090
91/* SDRAM */
92/* SDRAMC_MR Mode register */
93#define CONFIG_SYS_SDRC_MR_VAL1 0
94/* SDRAMC_TR - Refresh Timer register */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020095#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
96/* SDRAMC_CR - Configuration register*/
97#define CONFIG_SYS_SDRC_CR_VAL \
98 (AT91_SDRAMC_NC_9 | \
99 AT91_SDRAMC_NR_13 | \
100 AT91_SDRAMC_NB_4 | \
101 AT91_SDRAMC_CAS_2 | \
102 AT91_SDRAMC_DBW_32 | \
103 (2 << 8) | /* tWR - Write Recovery Delay */ \
104 (7 << 12) | /* tRC - Row Cycle Delay */ \
105 (2 << 16) | /* tRP - Row Precharge Delay */ \
106 (2 << 20) | /* tRCD - Row to Column Delay */ \
107 (5 << 24) | /* tRAS - Active to Precharge Delay */ \
108 (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
109
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200110/* Memory Device Register -> SDRAM */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200111#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
112#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200113#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200114#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200115#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
116#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
117#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
118#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
119#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
120#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
121#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
122#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200123#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200124#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200125#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200126#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
127#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
128#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
129
130/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200131#define CONFIG_SYS_SMC0_SETUP0_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +0300132 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
133 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200134#define CONFIG_SYS_SMC0_PULSE0_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +0300135 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
136 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200137#define CONFIG_SYS_SMC0_CYCLE0_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +0300138 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200139#define CONFIG_SYS_SMC0_MODE0_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +0300140 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
141 AT91_SMC_MODE_DBW_16 | \
142 AT91_SMC_MODE_TDF | \
143 AT91_SMC_MODE_TDF_CYCLE(6))
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200144
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200145/* user reset enable */
146#define CONFIG_SYS_RSTC_RMR_VAL \
147 (AT91_RSTC_KEY | \
Asen Dimov20d98c22010-04-19 14:18:43 +0300148 AT91_RSTC_CR_PROCRST | \
149 AT91_RSTC_MR_ERSTL(1) | \
150 AT91_RSTC_MR_ERSTL(2))
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200151
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200152/* Disable Watchdog */
153#define CONFIG_SYS_WDTC_WDMR_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +0300154 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
155 AT91_WDT_MR_WDV(0xfff) | \
156 AT91_WDT_MR_WDDIS | \
157 AT91_WDT_MR_WDD(0xfff))
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200158
159#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
160#define CONFIG_SETUP_MEMORY_TAGS 1
161#define CONFIG_INITRD_TAG 1
162
163#undef CONFIG_SKIP_LOWLEVEL_INIT
164#undef CONFIG_SKIP_RELOCATE_UBOOT
165#define CONFIG_USER_LOWLEVEL_INIT 1
166
167/*
168 * Hardware drivers
169 */
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100170#define CONFIG_AT91_GPIO 1
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200171#define CONFIG_ATMEL_USART 1
172#undef CONFIG_USART0
173#undef CONFIG_USART1
174#undef CONFIG_USART2
175#define CONFIG_USART3 1 /* USART 3 is DBGU */
176
177/* LCD */
178#define CONFIG_LCD 1
179#define LCD_BPP LCD_COLOR8
180#define CONFIG_LCD_LOGO 1
181#undef LCD_TEST_PATTERN
182#define CONFIG_LCD_INFO 1
183#define CONFIG_LCD_INFO_BELOW_LOGO 1
184#define CONFIG_SYS_WHITE_ON_BLACK 1
185#define CONFIG_ATMEL_LCD 1
186#define CONFIG_ATMEL_LCD_BGR555 1
187#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
188
189#define CONFIG_LCD_IN_PSRAM 1
190
191/* LED */
192#define CONFIG_AT91_LED
Asen Dimov20d98c22010-04-19 14:18:43 +0300193#define CONFIG_RED_LED AT91_PIO_PORTB, 7 /* this is the power led */
194#define CONFIG_GREEN_LED AT91_PIO_PORTB, 8 /* this is the user1 led */
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200195
196#define CONFIG_BOOTDELAY 3
197
198/*
199 * BOOTP options
200 */
201#define CONFIG_BOOTP_BOOTFILESIZE 1
202#define CONFIG_BOOTP_BOOTPATH 1
203#define CONFIG_BOOTP_GATEWAY 1
204#define CONFIG_BOOTP_HOSTNAME 1
205
206/*
207 * Command line configuration.
208 */
209#include <config_cmd_default.h>
210#undef CONFIG_CMD_BDI
211#undef CONFIG_CMD_IMI
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200212#undef CONFIG_CMD_FPGA
213#undef CONFIG_CMD_LOADS
214#undef CONFIG_CMD_IMLS
215
216#define CONFIG_CMD_PING 1
217#define CONFIG_CMD_DHCP 1
218#define CONFIG_CMD_NAND 1
219#define CONFIG_CMD_USB 1
220
221/* SDRAM */
222#define CONFIG_NR_DRAM_BANKS 1
223#define PHYS_SDRAM 0x20000000
224#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
225
226/* DataFlash */
227#define CONFIG_ATMEL_DATAFLASH_SPI
228#define CONFIG_HAS_DATAFLASH 1
229#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
230#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
231#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
232#define AT91_SPI_CLK 15000000
233#define DATAFLASH_TCSS (0x1a << 16)
234#define DATAFLASH_TCHS (0x1 << 24)
235
236/* NOR flash, if populated */
237#define CONFIG_SYS_FLASH_CFI 1
238#define CONFIG_FLASH_CFI_DRIVER 1
239#define PHYS_FLASH_1 0x10000000
240#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
241#define CONFIG_SYS_MAX_FLASH_SECT 256
242#define CONFIG_SYS_MAX_FLASH_BANKS 1
243
244/* NAND flash */
245#ifdef CONFIG_CMD_NAND
246#define CONFIG_NAND_ATMEL
247#define CONFIG_SYS_NAND_MAX_CHIPS 1
248#define CONFIG_SYS_MAX_NAND_DEVICE 1
249#define CONFIG_SYS_NAND_BASE 0x40000000
250#define CONFIG_SYS_NAND_DBW_8 1
251/* our ALE is AD21 */
252#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
253/* our CLE is AD22 */
254#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Asen Dimov20d98c22010-04-19 14:18:43 +0300255#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
256#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 30
Wolfgang Denk2eb99ca2009-07-18 21:52:24 +0200257
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200258#endif
259
260#define CONFIG_CMD_JFFS2 1
261#define CONFIG_JFFS2_CMDLINE 1
262#define CONFIG_JFFS2_NAND 1
263#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
264#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
265#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
266
267/* PSRAM */
268#define PHYS_PSRAM 0x70000000
269#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
Asen Dimov20d98c22010-04-19 14:18:43 +0300270/* Slave EBI1, PSRAM connected */
271#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \
272 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \
273 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \
274 AT91_MATRIX_SCFG_SLOT_CYCLE(255))
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200275
276/* Ethernet */
277#define CONFIG_MACB 1
278#define CONFIG_RMII 1
279#define CONFIG_NET_MULTI 1
280#define CONFIG_NET_RETRY_COUNT 20
281#define CONFIG_RESET_PHY_R 1
282
283/* USB */
284#define CONFIG_USB_ATMEL
285#define CONFIG_USB_OHCI_NEW 1
286#define CONFIG_DOS_PARTITION 1
287#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
288#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
289#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
290#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
291#define CONFIG_USB_STORAGE 1
292
293#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
294
295#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
296#define CONFIG_SYS_MEMTEST_END 0x23e00000
297
298#define CONFIG_SYS_USE_FLASH 1
299#undef CONFIG_SYS_USE_DATAFLASH
300#undef CONFIG_SYS_USE_NANDFLASH
301
302#ifdef CONFIG_SYS_USE_DATAFLASH
303
304/* bootstrap + u-boot + env + linux in dataflash on CS0 */
305#define CONFIG_ENV_IS_IN_DATAFLASH
306#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
307#define CONFIG_ENV_OFFSET 0x4200
308#define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
309#define CONFIG_ENV_SIZE 0x4200
310#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
311#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
312 "root=/dev/mtdblock0 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200313 "mtdparts=atmel_nand:-(root) "\
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200314 "rw rootfstype=jffs2"
315
316#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
317
318/* bootstrap + u-boot + env + linux in nandflash */
319#define CONFIG_ENV_IS_IN_NAND
320#define CONFIG_ENV_OFFSET 0x60000
321#define CONFIG_ENV_OFFSET_REDUND 0x80000
322#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
323#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
324#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
325 "root=/dev/mtdblock5 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200326 "mtdparts=atmel_nand:" \
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200327 "128k(bootstrap)ro," \
328 "256k(uboot)ro," \
329 "128k(env1)ro," \
330 "128k(env2)ro," \
331 "2M(linux)," \
332 "-(root) " \
333 "rw rootfstype=jffs2"
334
335#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
336
337#define CONFIG_ENV_IS_IN_FLASH 1
338#define CONFIG_ENV_OFFSET 0x40000
339#define CONFIG_ENV_SECT_SIZE 0x10000
340#define CONFIG_ENV_SIZE 0x10000
341#define CONFIG_ENV_OVERWRITE 1
342
343/* JFFS Partition offset set */
344#define CONFIG_SYS_JFFS2_FIRST_BANK 0
345#define CONFIG_SYS_JFFS2_NUM_BANKS 1
346
347/* 512k reserved for u-boot */
348#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
349
350#define CONFIG_BOOTCOMMAND "run flashboot"
351#define CONFIG_ROOTPATH /ronetix/rootfs
352#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
353
354#define CONFIG_CON_ROT "fbcon=rotate:3 "
355#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\
356 CONFIG_CON_ROT
357
358#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
359#define MTDPARTS_DEFAULT \
360 "mtdparts=physmap-flash.0:" \
361 "256k(u-boot)ro," \
362 "64k(u-boot-env)ro," \
363 "1408k(kernel)," \
364 "-(rootfs);" \
365 "nand:-(nand)"
366
367#define CONFIG_EXTRA_ENV_SETTINGS \
368 "mtdids=" MTDIDS_DEFAULT "\0" \
369 "mtdparts=" MTDPARTS_DEFAULT "\0" \
370 "partition=nand0,0\0" \
371 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
372 "nfsargs=setenv bootargs root=/dev/nfs rw " \
373 CONFIG_CON_ROT \
374 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
375 "addip=setenv bootargs $(bootargs) " \
376 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
377 ":$(hostname):eth0:off\0" \
378 "ramboot=tftpboot 0x22000000 vmImage;" \
379 "run ramargs;run addip;bootm 22000000\0" \
380 "nfsboot=tftpboot 0x22000000 vmImage;" \
381 "run nfsargs;run addip;bootm 22000000\0" \
382 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
383 ""
384
385#else
386#error "Undefined memory device"
387#endif
388
389#define CONFIG_BAUDRATE 115200
390#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
391
392#define CONFIG_SYS_PROMPT "u-boot-pm9263> "
393#define CONFIG_SYS_CBSIZE 256
394#define CONFIG_SYS_MAXARGS 16
395#define CONFIG_SYS_PBSIZE \
396 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
397#define CONFIG_SYS_LONGHELP 1
398#define CONFIG_CMDLINE_EDITING 1
399
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200400/*
401 * Size of malloc() pool
402 */
403#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
404#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
405
406#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
407
408#ifdef CONFIG_USE_IRQ
409#error CONFIG_USE_IRQ not supported
410#endif
411
412#endif