blob: bcd4c4d9c1bd25efa20b0798ff13882da511296e [file] [log] [blame]
Simon Glass51e9dad2015-03-02 12:40:54 -07001/dts-v1/;
2
3/include/ "skeleton.dtsi"
4/include/ "serial.dtsi"
Bin Mengb37b7b22018-07-19 03:07:33 -07005/include/ "reset.dtsi"
Bin Meng93f8a312015-07-15 16:23:39 +08006/include/ "rtc.dtsi"
Bin Meng80af3982015-11-13 00:11:22 -08007/include/ "tsc_timer.dtsi"
Simon Glass51e9dad2015-03-02 12:40:54 -07008
9/ {
10 model = "Google Panther";
11 compatible = "google,panther", "intel,haswell";
12
13 aliases {
Bin Meng81aaa3d2016-01-27 00:56:34 -080014 spi0 = &spi;
Simon Glass51e9dad2015-03-02 12:40:54 -070015 };
16
17 config {
18 silent-console = <0>;
19 no-keyboard;
20 };
21
Simon Glass51e9dad2015-03-02 12:40:54 -070022 chosen {
23 stdout-path = "/serial";
24 };
25
Simon Glass548fb872015-08-27 19:54:48 -060026 pci {
27 compatible = "pci-x86";
28 #address-cells = <3>;
29 #size-cells = <2>;
30 u-boot,dm-pre-reloc;
31 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
32 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
33 0x01000000 0x0 0x1000 0x1000 0 0xf000>;
Simon Glass548fb872015-08-27 19:54:48 -060034
Simon Glassf2b85ab2016-01-18 20:19:21 -070035 pch@1f,0 {
36 reg = <0x0000f800 0 0 0 0>;
37 compatible = "intel,pch9";
Bin Meng3ddc1c72016-02-01 01:40:47 -080038 #address-cells = <1>;
39 #size-cells = <1>;
Simon Glassf2b85ab2016-01-18 20:19:21 -070040
Bin Meng81aaa3d2016-01-27 00:56:34 -080041 spi: spi {
Simon Glassf2b85ab2016-01-18 20:19:21 -070042 #address-cells = <1>;
43 #size-cells = <0>;
Bin Meng1f9eb592016-02-01 01:40:37 -080044 compatible = "intel,ich9-spi";
Simon Glassf2b85ab2016-01-18 20:19:21 -070045 spi-flash@0 {
46 #size-cells = <1>;
47 #address-cells = <1>;
48 reg = <0>;
49 compatible = "winbond,w25q64",
Neil Armstrong51e4e3e2019-02-10 10:16:21 +000050 "jedec,spi-nor";
Simon Glassf2b85ab2016-01-18 20:19:21 -070051 memory-map = <0xff800000 0x00800000>;
52 rw-mrc-cache {
53 label = "rw-mrc-cache";
54 reg = <0x003e0000 0x00010000>;
55 };
56 };
Simon Glass51e9dad2015-03-02 12:40:54 -070057 };
Bin Meng3ddc1c72016-02-01 01:40:47 -080058
59 gpioa {
60 compatible = "intel,ich6-gpio";
61 u-boot,dm-pre-reloc;
62 reg = <0 0x10>;
63 bank-name = "A";
64 };
65
66 gpiob {
67 compatible = "intel,ich6-gpio";
68 u-boot,dm-pre-reloc;
69 reg = <0x30 0x10>;
70 bank-name = "B";
71 };
72
73 gpioc {
74 compatible = "intel,ich6-gpio";
75 u-boot,dm-pre-reloc;
76 reg = <0x40 0x10>;
77 bank-name = "C";
78 };
Simon Glass51e9dad2015-03-02 12:40:54 -070079 };
80 };
81
Simon Glass6e474ea2015-08-22 18:31:37 -060082 tpm {
83 reg = <0xfed40000 0x5000>;
84 compatible = "infineon,slb9635lpc";
85 };
86
Simon Glass51e9dad2015-03-02 12:40:54 -070087};