blob: 43255e538f7d59b57f949a5c7f97939ebb437408 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk42d1f032003-10-15 23:53:47 +00002/*
3 * tsec.h
4 *
5 * Driver for the Motorola Triple Speed Ethernet Controller
6 *
Claudiu Manoilaec84bf2013-09-30 12:44:42 +03007 * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
wdenk42d1f032003-10-15 23:53:47 +00008 * (C) Copyright 2003, Motorola, Inc.
9 * maintained by Xianghua Xiao (x.xiao@motorola.com)
10 * author Andy Fleming
wdenk42d1f032003-10-15 23:53:47 +000011 */
12
13#ifndef __TSEC_H
14#define __TSEC_H
15
16#include <net.h>
Eran Libertyf046ccd2005-07-28 10:08:46 -050017#include <config.h>
Andy Fleming063c1262011-04-08 02:10:54 -050018#include <phy.h>
wdenk42d1f032003-10-15 23:53:47 +000019
Vladimir Olteanbca686a2019-07-19 00:29:54 +030020#define TSEC_MDIO_REGS_OFFSET 0x520
21
Bin Meng9a1d6af2016-01-11 22:41:24 -080022#ifndef CONFIG_DM_ETH
23
York Sun73fb5832017-03-27 11:41:03 -070024#ifdef CONFIG_ARCH_LS1021A
Alison Wang52d00a82014-09-05 13:52:38 +080025#define TSEC_SIZE 0x40000
26#define TSEC_MDIO_OFFSET 0x40000
27#else
Sandeep Gopalpetb9e186f2009-10-31 00:35:04 +053028#define TSEC_SIZE 0x01000
29#define TSEC_MDIO_OFFSET 0x01000
Alison Wang52d00a82014-09-05 13:52:38 +080030#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -050031
Vladimir Olteanbca686a2019-07-19 00:29:54 +030032#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + TSEC_MDIO_REGS_OFFSET)
Andy Fleming063c1262011-04-08 02:10:54 -050033
Claudiu Manoilaec84bf2013-09-30 12:44:42 +030034#define TSEC_GET_REGS(num, offset) \
35 (struct tsec __iomem *)\
36 (TSEC_BASE_ADDR + (((num) - 1) * (offset)))
37
38#define TSEC_GET_REGS_BASE(num) \
39 TSEC_GET_REGS((num), TSEC_SIZE)
40
41#define TSEC_GET_MDIO_REGS(num, offset) \
42 (struct tsec_mii_mng __iomem *)\
43 (CONFIG_SYS_MDIO_BASE_ADDR + ((num) - 1) * (offset))
44
45#define TSEC_GET_MDIO_REGS_BASE(num) \
46 TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET)
47
Andy Fleming063c1262011-04-08 02:10:54 -050048#define DEFAULT_MII_NAME "FSL_MDIO"
49
Andy Fleming75b9d4a2008-08-31 16:33:26 -050050#define STD_TSEC_INFO(num) \
51{ \
Claudiu Manoilaec84bf2013-09-30 12:44:42 +030052 .regs = TSEC_GET_REGS_BASE(num), \
53 .miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \
Andy Fleming75b9d4a2008-08-31 16:33:26 -050054 .devname = CONFIG_TSEC##num##_NAME, \
55 .phyaddr = TSEC##num##_PHY_ADDR, \
Andy Fleming063c1262011-04-08 02:10:54 -050056 .flags = TSEC##num##_FLAGS, \
57 .mii_devname = DEFAULT_MII_NAME \
Andy Fleming75b9d4a2008-08-31 16:33:26 -050058}
59
60#define SET_STD_TSEC_INFO(x, num) \
61{ \
Claudiu Manoilaec84bf2013-09-30 12:44:42 +030062 x.regs = TSEC_GET_REGS_BASE(num); \
63 x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \
Andy Fleming75b9d4a2008-08-31 16:33:26 -050064 x.devname = CONFIG_TSEC##num##_NAME; \
65 x.phyaddr = TSEC##num##_PHY_ADDR; \
66 x.flags = TSEC##num##_FLAGS;\
Andy Fleming063c1262011-04-08 02:10:54 -050067 x.mii_devname = DEFAULT_MII_NAME;\
Andy Fleming75b9d4a2008-08-31 16:33:26 -050068}
69
Bin Meng9a1d6af2016-01-11 22:41:24 -080070#endif /* CONFIG_DM_ETH */
71
Bin Meng9872b732016-01-11 22:41:18 -080072#define MAC_ADDR_LEN 6
wdenk42d1f032003-10-15 23:53:47 +000073
Wolfgang Denk53677ef2008-05-20 16:00:29 +020074/* #define TSEC_TIMEOUT 1000000 */
Bin Meng9872b732016-01-11 22:41:18 -080075#define TSEC_TIMEOUT 1000
76#define TOUT_LOOP 1000000
wdenk42d1f032003-10-15 23:53:47 +000077
Andy Fleming2abe3612008-08-31 16:33:27 -050078/* TBI register addresses */
79#define TBI_CR 0x00
80#define TBI_SR 0x01
81#define TBI_ANA 0x04
82#define TBI_ANLPBPA 0x05
83#define TBI_ANEX 0x06
84#define TBI_TBICON 0x11
85
86/* TBI MDIO register bit fields*/
87#define TBICON_CLK_SELECT 0x0020
Bin Meng9872b732016-01-11 22:41:18 -080088#define TBIANA_ASYMMETRIC_PAUSE 0x0100
89#define TBIANA_SYMMETRIC_PAUSE 0x0080
Andy Fleming2abe3612008-08-31 16:33:27 -050090#define TBIANA_HALF_DUPLEX 0x0040
91#define TBIANA_FULL_DUPLEX 0x0020
92#define TBICR_PHY_RESET 0x8000
93#define TBICR_ANEG_ENABLE 0x1000
94#define TBICR_RESTART_ANEG 0x0200
95#define TBICR_FULL_DUPLEX 0x0100
96#define TBICR_SPEED1_SET 0x0040
97
wdenk42d1f032003-10-15 23:53:47 +000098/* MAC register bits */
99#define MACCFG1_SOFT_RESET 0x80000000
100#define MACCFG1_RESET_RX_MC 0x00080000
101#define MACCFG1_RESET_TX_MC 0x00040000
102#define MACCFG1_RESET_RX_FUN 0x00020000
Bin Meng9872b732016-01-11 22:41:18 -0800103#define MACCFG1_RESET_TX_FUN 0x00010000
wdenk42d1f032003-10-15 23:53:47 +0000104#define MACCFG1_LOOPBACK 0x00000100
105#define MACCFG1_RX_FLOW 0x00000020
106#define MACCFG1_TX_FLOW 0x00000010
107#define MACCFG1_SYNCD_RX_EN 0x00000008
108#define MACCFG1_RX_EN 0x00000004
109#define MACCFG1_SYNCD_TX_EN 0x00000002
110#define MACCFG1_TX_EN 0x00000001
111
112#define MACCFG2_INIT_SETTINGS 0x00007205
113#define MACCFG2_FULL_DUPLEX 0x00000001
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200114#define MACCFG2_IF 0x00000300
wdenk97d80fc2004-06-09 00:34:46 +0000115#define MACCFG2_GMII 0x00000200
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200116#define MACCFG2_MII 0x00000100
wdenk42d1f032003-10-15 23:53:47 +0000117
118#define ECNTRL_INIT_SETTINGS 0x00001000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200119#define ECNTRL_TBI_MODE 0x00000020
Andy Fleming063c1262011-04-08 02:10:54 -0500120#define ECNTRL_REDUCED_MODE 0x00000010
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500121#define ECNTRL_R100 0x00000008
Andy Fleming063c1262011-04-08 02:10:54 -0500122#define ECNTRL_REDUCED_MII_MODE 0x00000004
Andy Fleming81f481c2007-04-23 02:24:28 -0500123#define ECNTRL_SGMII_MODE 0x00000002
wdenk42d1f032003-10-15 23:53:47 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#ifndef CONFIG_SYS_TBIPA_VALUE
Bin Meng9872b732016-01-11 22:41:18 -0800126# define CONFIG_SYS_TBIPA_VALUE 0x1f
Joe Hammandcb84b72007-08-09 09:08:18 -0500127#endif
wdenk42d1f032003-10-15 23:53:47 +0000128
129#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
130
131#define MINFLR_INIT_SETTINGS 0x00000040
132
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200133#define DMACTRL_INIT_SETTINGS 0x000000c3
134#define DMACTRL_GRS 0x00000010
135#define DMACTRL_GTS 0x00000008
Alison Wang52d00a82014-09-05 13:52:38 +0800136#define DMACTRL_LE 0x00008000
wdenk42d1f032003-10-15 23:53:47 +0000137
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200138#define TSTAT_CLEAR_THALT 0x80000000
139#define RSTAT_CLEAR_RHALT 0x00800000
wdenk42d1f032003-10-15 23:53:47 +0000140
wdenk42d1f032003-10-15 23:53:47 +0000141#define IEVENT_INIT_CLEAR 0xffffffff
142#define IEVENT_BABR 0x80000000
143#define IEVENT_RXC 0x40000000
144#define IEVENT_BSY 0x20000000
145#define IEVENT_EBERR 0x10000000
146#define IEVENT_MSRO 0x04000000
147#define IEVENT_GTSC 0x02000000
148#define IEVENT_BABT 0x01000000
149#define IEVENT_TXC 0x00800000
150#define IEVENT_TXE 0x00400000
151#define IEVENT_TXB 0x00200000
152#define IEVENT_TXF 0x00100000
153#define IEVENT_IE 0x00080000
154#define IEVENT_LC 0x00040000
155#define IEVENT_CRL 0x00020000
156#define IEVENT_XFUN 0x00010000
157#define IEVENT_RXB0 0x00008000
158#define IEVENT_GRSC 0x00000100
159#define IEVENT_RXF0 0x00000080
160
161#define IMASK_INIT_CLEAR 0x00000000
162#define IMASK_TXEEN 0x00400000
163#define IMASK_TXBEN 0x00200000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200164#define IMASK_TXFEN 0x00100000
wdenk42d1f032003-10-15 23:53:47 +0000165#define IMASK_RXFEN0 0x00000080
166
wdenk42d1f032003-10-15 23:53:47 +0000167/* Default Attribute fields */
Bin Meng9872b732016-01-11 22:41:18 -0800168#define ATTR_INIT_SETTINGS 0x000000c0
169#define ATTRELI_INIT_SETTINGS 0x00000000
wdenk42d1f032003-10-15 23:53:47 +0000170
171/* TxBD status field bits */
172#define TXBD_READY 0x8000
173#define TXBD_PADCRC 0x4000
174#define TXBD_WRAP 0x2000
175#define TXBD_INTERRUPT 0x1000
176#define TXBD_LAST 0x0800
177#define TXBD_CRC 0x0400
178#define TXBD_DEF 0x0200
179#define TXBD_HUGEFRAME 0x0080
180#define TXBD_LATECOLLISION 0x0080
181#define TXBD_RETRYLIMIT 0x0040
Bin Meng9872b732016-01-11 22:41:18 -0800182#define TXBD_RETRYCOUNTMASK 0x003c
wdenk42d1f032003-10-15 23:53:47 +0000183#define TXBD_UNDERRUN 0x0002
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200184#define TXBD_STATS 0x03ff
wdenk42d1f032003-10-15 23:53:47 +0000185
186/* RxBD status field bits */
187#define RXBD_EMPTY 0x8000
188#define RXBD_RO1 0x4000
189#define RXBD_WRAP 0x2000
190#define RXBD_INTERRUPT 0x1000
191#define RXBD_LAST 0x0800
192#define RXBD_FIRST 0x0400
193#define RXBD_MISS 0x0100
194#define RXBD_BROADCAST 0x0080
195#define RXBD_MULTICAST 0x0040
196#define RXBD_LARGE 0x0020
197#define RXBD_NONOCTET 0x0010
198#define RXBD_SHORT 0x0008
199#define RXBD_CRCERR 0x0004
200#define RXBD_OVERRUN 0x0002
201#define RXBD_TRUNCATED 0x0001
202#define RXBD_STATS 0x003f
203
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300204struct txbd8 {
Bin Meng9872b732016-01-11 22:41:18 -0800205 uint16_t status; /* Status Fields */
206 uint16_t length; /* Buffer length */
207 uint32_t bufptr; /* Buffer Pointer */
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300208};
wdenk42d1f032003-10-15 23:53:47 +0000209
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300210struct rxbd8 {
Bin Meng9872b732016-01-11 22:41:18 -0800211 uint16_t status; /* Status Fields */
212 uint16_t length; /* Buffer Length */
213 uint32_t bufptr; /* Buffer Pointer */
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300214};
wdenk42d1f032003-10-15 23:53:47 +0000215
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300216struct tsec_rmon_mib {
wdenk42d1f032003-10-15 23:53:47 +0000217 /* Transmit and Receive Counters */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300218 u32 tr64; /* Tx/Rx 64-byte Frame Counter */
219 u32 tr127; /* Tx/Rx 65-127 byte Frame Counter */
220 u32 tr255; /* Tx/Rx 128-255 byte Frame Counter */
221 u32 tr511; /* Tx/Rx 256-511 byte Frame Counter */
222 u32 tr1k; /* Tx/Rx 512-1023 byte Frame Counter */
223 u32 trmax; /* Tx/Rx 1024-1518 byte Frame Counter */
224 u32 trmgv; /* Tx/Rx 1519-1522 byte Good VLAN Frame */
wdenk42d1f032003-10-15 23:53:47 +0000225 /* Receive Counters */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300226 u32 rbyt; /* Receive Byte Counter */
227 u32 rpkt; /* Receive Packet Counter */
228 u32 rfcs; /* Receive FCS Error Counter */
229 u32 rmca; /* Receive Multicast Packet (Counter) */
230 u32 rbca; /* Receive Broadcast Packet */
231 u32 rxcf; /* Receive Control Frame Packet */
232 u32 rxpf; /* Receive Pause Frame Packet */
233 u32 rxuo; /* Receive Unknown OP Code */
234 u32 raln; /* Receive Alignment Error */
235 u32 rflr; /* Receive Frame Length Error */
236 u32 rcde; /* Receive Code Error */
237 u32 rcse; /* Receive Carrier Sense Error */
238 u32 rund; /* Receive Undersize Packet */
239 u32 rovr; /* Receive Oversize Packet */
240 u32 rfrg; /* Receive Fragments */
241 u32 rjbr; /* Receive Jabber */
242 u32 rdrp; /* Receive Drop */
wdenk42d1f032003-10-15 23:53:47 +0000243 /* Transmit Counters */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300244 u32 tbyt; /* Transmit Byte Counter */
245 u32 tpkt; /* Transmit Packet */
246 u32 tmca; /* Transmit Multicast Packet */
247 u32 tbca; /* Transmit Broadcast Packet */
248 u32 txpf; /* Transmit Pause Control Frame */
249 u32 tdfr; /* Transmit Deferral Packet */
250 u32 tedf; /* Transmit Excessive Deferral Packet */
251 u32 tscl; /* Transmit Single Collision Packet */
wdenk42d1f032003-10-15 23:53:47 +0000252 /* (0x2_n700) */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300253 u32 tmcl; /* Transmit Multiple Collision Packet */
254 u32 tlcl; /* Transmit Late Collision Packet */
255 u32 txcl; /* Transmit Excessive Collision Packet */
256 u32 tncl; /* Transmit Total Collision */
wdenk42d1f032003-10-15 23:53:47 +0000257
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300258 u32 res2;
wdenk42d1f032003-10-15 23:53:47 +0000259
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300260 u32 tdrp; /* Transmit Drop Frame */
261 u32 tjbr; /* Transmit Jabber Frame */
262 u32 tfcs; /* Transmit FCS Error */
263 u32 txcf; /* Transmit Control Frame */
264 u32 tovr; /* Transmit Oversize Frame */
265 u32 tund; /* Transmit Undersize Frame */
266 u32 tfrg; /* Transmit Fragments Frame */
wdenk42d1f032003-10-15 23:53:47 +0000267 /* General Registers */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300268 u32 car1; /* Carry Register One */
269 u32 car2; /* Carry Register Two */
270 u32 cam1; /* Carry Register One Mask */
271 u32 cam2; /* Carry Register Two Mask */
272};
wdenk42d1f032003-10-15 23:53:47 +0000273
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300274struct tsec_hash_regs {
275 u32 iaddr0; /* Individual Address Register 0 */
276 u32 iaddr1; /* Individual Address Register 1 */
277 u32 iaddr2; /* Individual Address Register 2 */
278 u32 iaddr3; /* Individual Address Register 3 */
279 u32 iaddr4; /* Individual Address Register 4 */
280 u32 iaddr5; /* Individual Address Register 5 */
281 u32 iaddr6; /* Individual Address Register 6 */
282 u32 iaddr7; /* Individual Address Register 7 */
283 u32 res1[24];
284 u32 gaddr0; /* Group Address Register 0 */
285 u32 gaddr1; /* Group Address Register 1 */
286 u32 gaddr2; /* Group Address Register 2 */
287 u32 gaddr3; /* Group Address Register 3 */
288 u32 gaddr4; /* Group Address Register 4 */
289 u32 gaddr5; /* Group Address Register 5 */
290 u32 gaddr6; /* Group Address Register 6 */
291 u32 gaddr7; /* Group Address Register 7 */
292 u32 res2[24];
293};
wdenk42d1f032003-10-15 23:53:47 +0000294
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300295struct tsec {
wdenk42d1f032003-10-15 23:53:47 +0000296 /* General Control and Status Registers (0x2_n000) */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300297 u32 res000[4];
wdenk42d1f032003-10-15 23:53:47 +0000298
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300299 u32 ievent; /* Interrupt Event */
300 u32 imask; /* Interrupt Mask */
301 u32 edis; /* Error Disabled */
302 u32 res01c;
303 u32 ecntrl; /* Ethernet Control */
304 u32 minflr; /* Minimum Frame Length */
305 u32 ptv; /* Pause Time Value */
306 u32 dmactrl; /* DMA Control */
307 u32 tbipa; /* TBI PHY Address */
wdenk42d1f032003-10-15 23:53:47 +0000308
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300309 u32 res034[3];
310 u32 res040[48];
wdenk42d1f032003-10-15 23:53:47 +0000311
312 /* Transmit Control and Status Registers (0x2_n100) */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300313 u32 tctrl; /* Transmit Control */
314 u32 tstat; /* Transmit Status */
315 u32 res108;
316 u32 tbdlen; /* Tx BD Data Length */
317 u32 res110[5];
318 u32 ctbptr; /* Current TxBD Pointer */
319 u32 res128[23];
320 u32 tbptr; /* TxBD Pointer */
321 u32 res188[30];
wdenk42d1f032003-10-15 23:53:47 +0000322 /* (0x2_n200) */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300323 u32 res200;
324 u32 tbase; /* TxBD Base Address */
325 u32 res208[42];
326 u32 ostbd; /* Out of Sequence TxBD */
327 u32 ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
328 u32 res2b8[18];
wdenk42d1f032003-10-15 23:53:47 +0000329
330 /* Receive Control and Status Registers (0x2_n300) */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300331 u32 rctrl; /* Receive Control */
332 u32 rstat; /* Receive Status */
333 u32 res308;
334 u32 rbdlen; /* RxBD Data Length */
335 u32 res310[4];
336 u32 res320;
Bin Meng9872b732016-01-11 22:41:18 -0800337 u32 crbptr; /* Current Receive Buffer Pointer */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300338 u32 res328[6];
Bin Meng9872b732016-01-11 22:41:18 -0800339 u32 mrblr; /* Maximum Receive Buffer Length */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300340 u32 res344[16];
Bin Meng9872b732016-01-11 22:41:18 -0800341 u32 rbptr; /* RxBD Pointer */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300342 u32 res388[30];
wdenk42d1f032003-10-15 23:53:47 +0000343 /* (0x2_n400) */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300344 u32 res400;
Bin Meng9872b732016-01-11 22:41:18 -0800345 u32 rbase; /* RxBD Base Address */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300346 u32 res408[62];
wdenk42d1f032003-10-15 23:53:47 +0000347
348 /* MAC Registers (0x2_n500) */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300349 u32 maccfg1; /* MAC Configuration #1 */
350 u32 maccfg2; /* MAC Configuration #2 */
351 u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
352 u32 hafdup; /* Half-duplex */
353 u32 maxfrm; /* Maximum Frame */
354 u32 res514;
355 u32 res518;
wdenk42d1f032003-10-15 23:53:47 +0000356
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300357 u32 res51c;
wdenk42d1f032003-10-15 23:53:47 +0000358
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300359 u32 resmdio[6];
wdenk42d1f032003-10-15 23:53:47 +0000360
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300361 u32 res538;
wdenk42d1f032003-10-15 23:53:47 +0000362
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300363 u32 ifstat; /* Interface Status */
364 u32 macstnaddr1; /* Station Address, part 1 */
365 u32 macstnaddr2; /* Station Address, part 2 */
366 u32 res548[46];
wdenk42d1f032003-10-15 23:53:47 +0000367
368 /* (0x2_n600) */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300369 u32 res600[32];
wdenk42d1f032003-10-15 23:53:47 +0000370
371 /* RMON MIB Registers (0x2_n680-0x2_n73c) */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300372 struct tsec_rmon_mib rmon;
373 u32 res740[48];
wdenk42d1f032003-10-15 23:53:47 +0000374
375 /* Hash Function Registers (0x2_n800) */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300376 struct tsec_hash_regs hash;
wdenk42d1f032003-10-15 23:53:47 +0000377
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300378 u32 res900[128];
wdenk42d1f032003-10-15 23:53:47 +0000379
380 /* Pattern Registers (0x2_nb00) */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300381 u32 resb00[62];
382 u32 attr; /* Default Attribute Register */
383 u32 attreli; /* Default Attribute Extract Length and Index */
wdenk42d1f032003-10-15 23:53:47 +0000384
385 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300386 u32 resc00[256];
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300387};
wdenk42d1f032003-10-15 23:53:47 +0000388
Bin Meng9872b732016-01-11 22:41:18 -0800389#define TSEC_GIGABIT (1 << 0)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500390
Andy Fleming063c1262011-04-08 02:10:54 -0500391/* These flags currently only have meaning if we're using the eTSEC */
Peter Tyser5f6b1442009-11-09 13:09:48 -0600392#define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */
393#define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500394
Bin Menge677da92016-01-11 22:41:20 -0800395#define TX_BUF_CNT 2
396
wdenk97d80fc2004-06-09 00:34:46 +0000397struct tsec_private {
Bin Menge677da92016-01-11 22:41:20 -0800398 struct txbd8 __iomem txbd[TX_BUF_CNT];
399 struct rxbd8 __iomem rxbd[PKTBUFSRX];
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300400 struct tsec __iomem *regs;
401 struct tsec_mii_mng __iomem *phyregs_sgmii;
Andy Fleming063c1262011-04-08 02:10:54 -0500402 struct phy_device *phydev;
403 phy_interface_t interface;
404 struct mii_dev *bus;
wdenk97d80fc2004-06-09 00:34:46 +0000405 uint phyaddr;
Bin Menga1c76c12016-01-11 22:41:25 -0800406 uint tbiaddr;
Andy Fleming063c1262011-04-08 02:10:54 -0500407 char mii_devname[16];
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500408 u32 flags;
Bin Meng362b1232016-01-11 22:41:19 -0800409 uint rx_idx; /* index of the current RX buffer */
410 uint tx_idx; /* index of the current TX buffer */
Bin Meng9a1d6af2016-01-11 22:41:24 -0800411#ifndef CONFIG_DM_ETH
Bin Meng56a27a12016-01-11 22:41:22 -0800412 struct eth_device *dev;
Bin Meng9a1d6af2016-01-11 22:41:24 -0800413#else
414 struct udevice *dev;
415#endif
wdenk97d80fc2004-06-09 00:34:46 +0000416};
417
Andy Flemingdd3d1f52008-08-31 16:33:25 -0500418struct tsec_info_struct {
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300419 struct tsec __iomem *regs;
420 struct tsec_mii_mng __iomem *miiregs_sgmii;
Andy Fleming75b9d4a2008-08-31 16:33:26 -0500421 char *devname;
Andy Fleming063c1262011-04-08 02:10:54 -0500422 char *mii_devname;
423 phy_interface_t interface;
Andy Flemingdd3d1f52008-08-31 16:33:25 -0500424 unsigned int phyaddr;
425 u32 flags;
Andy Flemingdd3d1f52008-08-31 16:33:25 -0500426};
427
Bin Meng9a1d6af2016-01-11 22:41:24 -0800428#ifndef CONFIG_DM_ETH
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900429int tsec_standard_init(struct bd_info *bis);
430int tsec_eth_init(struct bd_info *bis, struct tsec_info_struct *tsec_info,
431 int num);
Bin Meng9a1d6af2016-01-11 22:41:24 -0800432#endif
Andy Fleming75b9d4a2008-08-31 16:33:26 -0500433
wdenk42d1f032003-10-15 23:53:47 +0000434#endif /* __TSEC_H */