blob: dd65b5234380a9871d0efb602ddd0d86c54555b8 [file] [log] [blame]
Michal Simekdea4d2f2017-11-02 10:54:48 +01001/*
2 * (C) Copyright 2013 - 2017 Xilinx.
3 *
4 * Configuration settings for the Xilinx Zynq CSE board.
5 * See zynq-common.h for Zynq common configs
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_ZYNQ_CSE_H
11#define __CONFIG_ZYNQ_CSE_H
12
13#define CONFIG_SKIP_LOWLEVEL_INIT
14#define CONFIG_SYS_DCACHE_OFF
15#define CONFIG_SYS_ICACHE_OFF
16
17#include <configs/zynq-common.h>
18
19/* Undef unneeded configs */
20#undef CONFIG_EXTRA_ENV_SETTINGS
21#undef CONFIG_BOARD_LATE_INIT
22#undef CONFIG_BOOTCOMMAND
23#undef CONFIG_ENV_SIZE
24#undef CONFIG_CMDLINE_EDITING
25#undef CONFIG_AUTO_COMPLETE
26#undef CONFIG_ZLIB
27#undef CONFIG_GZIP
28
29#undef CONFIG_SYS_LONGHELP
30
31#undef CONFIG_SYS_CBSIZE
32#undef CONFIG_BOOTM_VXWORKS
33#undef CONFIG_BOOTM_LINUX
34
35#define CONFIG_SYS_CBSIZE 1024
36
37#define CONFIG_ENV_SIZE 400
38#undef CONFIG_SYS_INIT_RAM_ADDR
39#undef CONFIG_SYS_INIT_RAM_SIZE
40#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000
41#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
42#undef CONFIG_SPL_BSS_START_ADDR
43#undef CONFIG_SPL_BSS_MAX_SIZE
44#define CONFIG_SPL_BSS_START_ADDR 0x20000
45#define CONFIG_SPL_BSS_MAX_SIZE 0x8000
46
47#undef CONFIG_SYS_MALLOC_LEN
48#define CONFIG_SYS_MALLOC_LEN 0x1000
49
50#define CONFIG_SYS_SDRAM_BASE 0xfffc0000
51#define CONFIG_SYS_SDRAM_SIZE 0x40000
52
53#endif /* __CONFIG_ZYNQ_CSE_H */