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wdenk717b5aa2002-04-27 11:09:31 +00001/*
2 * NS16550 Serial Port
Stefan Roesea47a12b2010-04-15 16:07:28 +02003 * originally from linux source (arch/powerpc/boot/ns16550.h)
Detlev Zundel200779e2009-04-03 11:53:01 +02004 *
5 * Cleanup and unification
6 * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
7 *
wdenk717b5aa2002-04-27 11:09:31 +00008 * modified slightly to
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02009 * have addresses as offsets from CONFIG_SYS_ISA_BASE
wdenk717b5aa2002-04-27 11:09:31 +000010 * added a few more definitions
11 * added prototypes for ns16550.c
12 * reduced no of com ports to 2
13 * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020014 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +020015 * added support for port on 64-bit bus
16 * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
wdenk717b5aa2002-04-27 11:09:31 +000017 */
18
Detlev Zundel453c0d72009-04-03 16:45:46 +020019/*
20 * Note that the following macro magic uses the fact that the compiler
21 * will not allocate storage for arrays of size 0
22 */
23
Dave Aldridge79df1202011-09-01 22:47:14 +000024#include <linux/types.h>
25
Simon Glass12e431b2014-09-04 16:27:34 -060026#ifdef CONFIG_DM_SERIAL
27/*
28 * For driver model we always use one byte per register, and sort out the
29 * differences in the driver
30 */
31#define CONFIG_SYS_NS16550_REG_SIZE (-1)
32#endif
33
Detlev Zundel453c0d72009-04-03 16:45:46 +020034#if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0)
wdenk717b5aa2002-04-27 11:09:31 +000035#error "Please define NS16550 registers size."
Simon Glass90914002015-05-12 14:55:02 -060036#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL)
Dave Aldridge79df1202011-09-01 22:47:14 +000037#define UART_REG(x) u32 x
Detlev Zundel453c0d72009-04-03 16:45:46 +020038#elif (CONFIG_SYS_NS16550_REG_SIZE > 0)
39#define UART_REG(x) \
40 unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
41 unsigned char x;
42#elif (CONFIG_SYS_NS16550_REG_SIZE < 0)
43#define UART_REG(x) \
44 unsigned char x; \
45 unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
wdenk717b5aa2002-04-27 11:09:31 +000046#endif
47
Simon Glass12e431b2014-09-04 16:27:34 -060048/**
49 * struct ns16550_platdata - information about a NS16550 port
50 *
51 * @base: Base register address
52 * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...)
53 * @clock: UART base clock speed in Hz
Stefan Roese6822cf32017-07-14 17:25:54 +020054 *
55 * @buf: Pointer to the RX interrupt buffer
56 * @rd_ptr: Read pointer in the RX interrupt buffer
57 * @wr_ptr: Write pointer in the RX interrupt buffer
Simon Glass12e431b2014-09-04 16:27:34 -060058 */
59struct ns16550_platdata {
Simon Glass167efe02014-10-22 21:37:04 -060060 unsigned long base;
Simon Glass12e431b2014-09-04 16:27:34 -060061 int reg_shift;
62 int clock;
Michal Simek59b35dd2016-02-16 16:17:49 +010063 int reg_offset;
Marek Vasut65f83802016-12-01 02:06:29 +010064 u32 fcr;
Stefan Roese6822cf32017-07-14 17:25:54 +020065
66 int irq;
67
68 char *buf;
69 int rd_ptr;
70 int wr_ptr;
Simon Glass12e431b2014-09-04 16:27:34 -060071};
72
73struct udevice;
74
Detlev Zundel453c0d72009-04-03 16:45:46 +020075struct NS16550 {
76 UART_REG(rbr); /* 0 */
77 UART_REG(ier); /* 1 */
78 UART_REG(fcr); /* 2 */
79 UART_REG(lcr); /* 3 */
80 UART_REG(mcr); /* 4 */
81 UART_REG(lsr); /* 5 */
82 UART_REG(msr); /* 6 */
83 UART_REG(spr); /* 7 */
Mikhail Kshevetskiy99b603e2012-07-09 08:52:43 +000084#ifdef CONFIG_SOC_DA8XX
85 UART_REG(reg8); /* 8 */
86 UART_REG(reg9); /* 9 */
87 UART_REG(revid1); /* A */
88 UART_REG(revid2); /* B */
89 UART_REG(pwr_mgmt); /* C */
90 UART_REG(mdr1); /* D */
91#else
Detlev Zundel453c0d72009-04-03 16:45:46 +020092 UART_REG(mdr1); /* 8 */
93 UART_REG(reg9); /* 9 */
94 UART_REG(regA); /* A */
95 UART_REG(regB); /* B */
96 UART_REG(regC); /* C */
97 UART_REG(regD); /* D */
98 UART_REG(regE); /* E */
99 UART_REG(uasr); /* F */
100 UART_REG(scr); /* 10*/
101 UART_REG(ssr); /* 11*/
Mikhail Kshevetskiy99b603e2012-07-09 08:52:43 +0000102#endif
Simon Glass12e431b2014-09-04 16:27:34 -0600103#ifdef CONFIG_DM_SERIAL
104 struct ns16550_platdata *plat;
105#endif
Detlev Zundel453c0d72009-04-03 16:45:46 +0200106};
107
wdenk717b5aa2002-04-27 11:09:31 +0000108#define thr rbr
109#define iir fcr
110#define dll rbr
111#define dlm ier
112
Simon Glassf8df9d02011-10-15 19:14:09 +0000113typedef struct NS16550 *NS16550_t;
wdenk717b5aa2002-04-27 11:09:31 +0000114
Detlev Zundel200779e2009-04-03 11:53:01 +0200115/*
116 * These are the definitions for the FIFO Control Register
117 */
Simon Glassf8df9d02011-10-15 19:14:09 +0000118#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
Detlev Zundel200779e2009-04-03 11:53:01 +0200119#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
120#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
121#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
122#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
123#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
124#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
125#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
126#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
wdenk717b5aa2002-04-27 11:09:31 +0000127
Detlev Zundel200779e2009-04-03 11:53:01 +0200128#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
129#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
wdenk717b5aa2002-04-27 11:09:31 +0000130
Marek Vasut0b060ee2016-12-01 02:06:31 +0100131/* Ingenic JZ47xx specific UART-enable bit. */
132#define UART_FCR_UME 0x10
133
Heiko Schocher17fa0322017-01-18 08:05:49 +0100134/* Clear & enable FIFOs */
135#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \
136 UART_FCR_RXSR | \
137 UART_FCR_TXSR)
138
Detlev Zundel200779e2009-04-03 11:53:01 +0200139/*
140 * These are the definitions for the Modem Control Register
141 */
142#define UART_MCR_DTR 0x01 /* DTR */
143#define UART_MCR_RTS 0x02 /* RTS */
144#define UART_MCR_OUT1 0x04 /* Out 1 */
145#define UART_MCR_OUT2 0x08 /* Out 2 */
146#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
Karicheri, Muralidharand57dee52014-04-09 15:38:46 -0400147#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
wdenk717b5aa2002-04-27 11:09:31 +0000148
Detlev Zundel200779e2009-04-03 11:53:01 +0200149#define UART_MCR_DMA_EN 0x04
150#define UART_MCR_TX_DFR 0x08
wdenk717b5aa2002-04-27 11:09:31 +0000151
Detlev Zundel200779e2009-04-03 11:53:01 +0200152/*
153 * These are the definitions for the Line Control Register
154 *
155 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
156 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
157 */
158#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
159#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
160#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
161#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
162#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
Simon Glassf8df9d02011-10-15 19:14:09 +0000163#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
Detlev Zundel200779e2009-04-03 11:53:01 +0200164#define UART_LCR_PEN 0x08 /* Parity eneble */
165#define UART_LCR_EPS 0x10 /* Even Parity Select */
166#define UART_LCR_STKP 0x20 /* Stick Parity */
167#define UART_LCR_SBRK 0x40 /* Set Break */
168#define UART_LCR_BKSE 0x80 /* Bank select enable */
169#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
170
171/*
172 * These are the definitions for the Line Status Register
173 */
174#define UART_LSR_DR 0x01 /* Data ready */
175#define UART_LSR_OE 0x02 /* Overrun */
176#define UART_LSR_PE 0x04 /* Parity error */
177#define UART_LSR_FE 0x08 /* Framing error */
178#define UART_LSR_BI 0x10 /* Break */
179#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
180#define UART_LSR_TEMT 0x40 /* Xmitter empty */
181#define UART_LSR_ERR 0x80 /* Error */
182
183#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
184#define UART_MSR_RI 0x40 /* Ring Indicator */
185#define UART_MSR_DSR 0x20 /* Data Set Ready */
186#define UART_MSR_CTS 0x10 /* Clear to Send */
187#define UART_MSR_DDCD 0x08 /* Delta DCD */
188#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
189#define UART_MSR_DDSR 0x02 /* Delta DSR */
190#define UART_MSR_DCTS 0x01 /* Delta CTS */
191
192/*
193 * These are the definitions for the Interrupt Identification Register
194 */
195#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
196#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
197
198#define UART_IIR_MSI 0x00 /* Modem status interrupt */
199#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
200#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
201#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
202
203/*
204 * These are the definitions for the Interrupt Enable Register
205 */
206#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
207#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
208#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
209#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
210
wdenk717b5aa2002-04-27 11:09:31 +0000211/* useful defaults for LCR */
Detlev Zundel200779e2009-04-03 11:53:01 +0200212#define UART_LCR_8N1 0x03
wdenk717b5aa2002-04-27 11:09:31 +0000213
Simon Glassf8df9d02011-10-15 19:14:09 +0000214void NS16550_init(NS16550_t com_port, int baud_divisor);
215void NS16550_putc(NS16550_t com_port, char c);
216char NS16550_getc(NS16550_t com_port);
217int NS16550_tstc(NS16550_t com_port);
218void NS16550_reinit(NS16550_t com_port, int baud_divisor);
Simon Glassfa54eb12014-09-04 16:27:32 -0600219
220/**
221 * ns16550_calc_divisor() - calculate the divisor given clock and baud rate
222 *
223 * Given the UART input clock and required baudrate, calculate the divisor
224 * that should be used.
225 *
226 * @port: UART port
227 * @clock: UART input clock speed in Hz
228 * @baudrate: Required baud rate
229 * @return baud rate divisor that should be used
230 */
231int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate);
Simon Glass12e431b2014-09-04 16:27:34 -0600232
233/**
234 * ns16550_serial_ofdata_to_platdata() - convert DT to platform data
235 *
236 * Decode a device tree node for an ns16550 device. This includes the
237 * register base address and register shift properties. The caller must set
238 * up the clock frequency.
239 *
240 * @dev: dev to decode platform data for
241 * @return: 0 if OK, -EINVAL on error
242 */
243int ns16550_serial_ofdata_to_platdata(struct udevice *dev);
244
245/**
246 * ns16550_serial_probe() - probe a serial port
247 *
248 * This sets up the serial port ready for use, except for the baud rate
249 * @return 0, or -ve on error
250 */
251int ns16550_serial_probe(struct udevice *dev);
252
253/**
254 * struct ns16550_serial_ops - ns16550 serial operations
255 *
256 * These should be used by the client driver for the driver's 'ops' member
257 */
258extern const struct dm_serial_ops ns16550_serial_ops;