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Mike Frysingere5483212008-10-12 21:45:05 -04001/*
2 * U-boot - Configuration file for CM-BF561 board
3 */
4
5#ifndef __CONFIG_CM_BF561_H__
6#define __CONFIG_CM_BF561_H__
7
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingere5483212008-10-12 21:45:05 -04009
10
11/*
12 * Processor Settings
13 */
Mike Frysingere5483212008-10-12 21:45:05 -040014#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
15
16
17/*
18 * Clock Settings
19 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
20 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
21 */
22/* CONFIG_CLKIN_HZ is any value in Hz */
23#define CONFIG_CLKIN_HZ 25000000
24/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
25/* 1 = CLKIN / 2 */
26#define CONFIG_CLKIN_HALF 0
27/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
28/* 1 = bypass PLL */
29#define CONFIG_PLL_BYPASS 0
30/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
31/* Values can range from 0-63 (where 0 means 64) */
Harald Krapfenbauerfd04a052009-10-14 08:37:32 -040032#define CONFIG_VCO_MULT 20
Mike Frysingere5483212008-10-12 21:45:05 -040033/* CCLK_DIV controls the core clock divider */
34/* Values can be 1, 2, 4, or 8 ONLY */
35#define CONFIG_CCLK_DIV 1
36/* SCLK_DIV controls the system clock divider */
37/* Values can range from 1-15 */
38#define CONFIG_SCLK_DIV 5
39
Harald Krapfenbauerfd04a052009-10-14 08:37:32 -040040/* Decrease core voltage */
41#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
42
Mike Frysingere5483212008-10-12 21:45:05 -040043
44/*
45 * Memory Settings
46 */
47#define CONFIG_MEM_ADD_WDTH 9
48#define CONFIG_MEM_SIZE 64
49
50#define CONFIG_EBIU_SDRRC_VAL ((((CONFIG_SCLK_HZ / 1000) * 64) / 4096) - (7 + 2))
51#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3)
52
53#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | B3_PEN | B2_PEN | B1_PEN | B0_PEN | AMBEN_ALL | AMCKEN)
54#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
55#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
56
57#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
58#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
59
60
61/*
62 * Network Settings
63 */
64#define ADI_CMDS_NETWORK 1
Ben Warren7194ab82009-10-04 22:37:03 -070065#define CONFIG_NET_MULTI
Harald Krapfenbauer6a0be8f2010-01-22 17:15:55 -050066#define CONFIG_SMC911X 1
67#define CONFIG_SMC911X_BASE 0x24008000 /* AMS1 */
68#define CONFIG_SMC911X_16_BIT
Mike Frysingere5483212008-10-12 21:45:05 -040069#define CONFIG_HOSTNAME cm-bf561
70/* Uncomment next line to use fixed MAC address */
71/* #define CONFIG_ETHADDR 02:80:ad:20:31:cf */
72
73
74/*
75 * Flash Settings
76 */
77#define CONFIG_FLASH_CFI_DRIVER
78#define CONFIG_SYS_FLASH_BASE 0x20000000
79#define CONFIG_SYS_FLASH_CFI
80#define CONFIG_SYS_FLASH_PROTECTION
81#define CONFIG_SYS_MAX_FLASH_BANKS 1
82#define CONFIG_SYS_MAX_FLASH_SECT 67
83
84
85/*
86 * Env Storage Settings
87 */
88#define CONFIG_ENV_IS_IN_FLASH 1
89#define CONFIG_ENV_OFFSET 0x20000
90#define CONFIG_ENV_SECT_SIZE 0x20000
91#define CONFIG_ENV_SIZE 0x10000
Harald Krapfenbauer6a0be8f2010-01-22 17:15:55 -050092#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysingere5483212008-10-12 21:45:05 -040093
94
95/*
96 * Misc Settings
97 */
98#define CONFIG_BAUDRATE 115200
99#define CONFIG_UART_CONSOLE 0
Harald Krapfenbauerfd04a052009-10-14 08:37:32 -0400100#define CONFIG_BOOTCOMMAND "run flashboot"
101#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
Mike Frysingere5483212008-10-12 21:45:05 -0400102
103
104/*
105 * Pull in common ADI header for remaining command/environment setup
106 */
107#include <configs/bfin_adi_common.h>
108
Mike Frysingere5483212008-10-12 21:45:05 -0400109#endif