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Wolfgang Denkeece1592005-08-10 11:03:05 +02001/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004-2005
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 * (easy to change)
33 */
34
35#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
37#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
38#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
39#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
40#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
41
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
Wolfgang Denkeece1592005-08-10 11:03:05 +020043
Becky Bruce31d82672008-05-08 19:02:12 -050044#define CONFIG_HIGH_BATS 1 /* High BATs supported */
45
Wolfgang Denkeece1592005-08-10 11:03:05 +020046/*
47 * Serial console configuration
48 */
49#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */
50#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Wolfgang Denkeece1592005-08-10 11:03:05 +020052
53#ifdef CONFIG_STK52XX
54#undef CONFIG_PS2KBD /* AT-PS/2 Keyboard */
55#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
56#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
Wolfgang Denkeece1592005-08-10 11:03:05 +020058#define CONFIG_BOARD_EARLY_INIT_R
59#endif /* CONFIG_STK52XX */
60
61/*
62 * PCI Mapping:
63 * 0x40000000 - 0x4fffffff - PCI Memory
64 * 0x50000000 - 0x50ffffff - PCI IO Space
65 */
66#ifdef CONFIG_STK52XX
67#define CONFIG_PCI 1
68#define CONFIG_PCI_PNP 1
69/* #define CONFIG_PCI_SCAN_SHOW 1 */
70
71#define CONFIG_PCI_MEM_BUS 0x40000000
72#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
73#define CONFIG_PCI_MEM_SIZE 0x10000000
74
75#define CONFIG_PCI_IO_BUS 0x50000000
76#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
77#define CONFIG_PCI_IO_SIZE 0x01000000
78
79#define CONFIG_NET_MULTI 1
80#define CONFIG_EEPRO100 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
Wolfgang Denkeece1592005-08-10 11:03:05 +020082#define CONFIG_NS8382X 1
83#endif /* CONFIG_STK52XX */
84
Wolfgang Denkeece1592005-08-10 11:03:05 +020085/*
86 * Video console
87 */
88#if 1
89#define CONFIG_VIDEO
90#define CONFIG_VIDEO_SM501
91#define CONFIG_VIDEO_SM501_32BPP
92#define CONFIG_CFB_CONSOLE
93#define CONFIG_VIDEO_LOGO
94#define CONFIG_VGA_AS_SINGLE_DEVICE
95#define CONFIG_CONSOLE_EXTRA_INFO
96#define CONFIG_VIDEO_SW_CURSOR
97#define CONFIG_SPLASH_SCREEN
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Wolfgang Denkeece1592005-08-10 11:03:05 +020099#endif
100
Wolfgang Denkeece1592005-08-10 11:03:05 +0200101/* Partitions */
102#define CONFIG_MAC_PARTITION
103#define CONFIG_DOS_PARTITION
104#define CONFIG_ISO_PARTITION
105
106/* USB */
107#ifdef CONFIG_STK52XX
108#define CONFIG_USB_OHCI
Wolfgang Denkeece1592005-08-10 11:03:05 +0200109#define CONFIG_USB_STORAGE
Wolfgang Denkeece1592005-08-10 11:03:05 +0200110#endif
111
112/* POST support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
114 CONFIG_SYS_POST_CPU | \
115 CONFIG_SYS_POST_I2C)
Wolfgang Denkeece1592005-08-10 11:03:05 +0200116
117#ifdef CONFIG_POST
Wolfgang Denkeece1592005-08-10 11:03:05 +0200118/* preserve space for the post_word at end of on-chip SRAM */
119#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
Wolfgang Denkeece1592005-08-10 11:03:05 +0200120#endif
121
Wolfgang Denkeece1592005-08-10 11:03:05 +0200122
123/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500124 * BOOTP options
125 */
126#define CONFIG_BOOTP_BOOTFILESIZE
127#define CONFIG_BOOTP_BOOTPATH
128#define CONFIG_BOOTP_GATEWAY
129#define CONFIG_BOOTP_HOSTNAME
130
131
132/*
Jon Loeliger46da1e92007-07-04 22:33:30 -0500133 * Command line configuration.
Wolfgang Denkeece1592005-08-10 11:03:05 +0200134 */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500135#include <config_cmd_default.h>
Wolfgang Denkeece1592005-08-10 11:03:05 +0200136
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500137#define CONFIG_CMD_ASKENV
138#define CONFIG_CMD_DATE
139#define CONFIG_CMD_DHCP
140#define CONFIG_CMD_ECHO
141#define CONFIG_CMD_EEPROM
142#define CONFIG_CMD_I2C
143#define CONFIG_CMD_MII
144#define CONFIG_CMD_NFS
145#define CONFIG_CMD_PING
146#define CONFIG_CMD_REGINFO
147#define CONFIG_CMD_SNTP
148
Jon Loeliger46da1e92007-07-04 22:33:30 -0500149#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
150 #define CONFIG_CMD_IDE
151 #define CONFIG_CMD_FAT
152 #define CONFIG_CMD_EXT2
153#endif
154
155#ifdef CONFIG_STK52XX
156 #define CONFIG_CMD_USB
157 #define CONFIG_CMD_FAT
158#endif
159
160#ifdef CONFIG_VIDEO
161 #define CONFIG_CMD_BMP
162#endif
163
164#ifdef CONFIG_PCI
165 #define CONFIG_CMD_PCI
TsiChung Liewf33fca22008-03-30 01:19:06 -0500166 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
Jon Loeliger46da1e92007-07-04 22:33:30 -0500167#endif
168
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500169#ifdef CONFIG_POST
170#define CONFIG_CMD_DIAG
171#endif
Jon Loeliger46da1e92007-07-04 22:33:30 -0500172
Wolfgang Denkeece1592005-08-10 11:03:05 +0200173
174#define CONFIG_TIMESTAMP /* display image timestamps */
175
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200176#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177# define CONFIG_SYS_LOWBOOT 1
Wolfgang Denkeece1592005-08-10 11:03:05 +0200178#endif
179
180/*
181 * Autobooting
182 */
183#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
184
185#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100186 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200187 "echo"
188
189#undef CONFIG_BOOTARGS
190
Wolfgang Denkeece1592005-08-10 11:03:05 +0200191#define CONFIG_EXTRA_ENV_SETTINGS \
192 "netdev=eth0\0" \
193 "rootpath=/opt/eldk/ppc_6xx\0" \
194 "ramargs=setenv bootargs root=/dev/ram rw\0" \
195 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100196 "nfsroot=${serverip}:${rootpath}\0" \
197 "addip=setenv bootargs ${bootargs} " \
198 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
199 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200200 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100201 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200202 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100203 "bootm ${kernel_addr}\0" \
204 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200205 "bootfile=/tftpboot/tqm5200/uImage\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100206 "load=tftp 200000 ${u-boot}\0" \
Wolfgang Denkcd65a3d2006-06-16 16:11:34 +0200207 "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200208 "update=protect off FC000000 FC05FFFF;" \
209 "erase FC000000 FC05FFFF;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100210 "cp.b 200000 FC000000 ${filesize};" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200211 "protect on FC000000 FC05FFFF\0" \
212 ""
213
214#define CONFIG_BOOTCOMMAND "run net_nfs"
215
216/*
217 * IPB Bus clocking configuration.
218 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
Wolfgang Denkeece1592005-08-10 11:03:05 +0200222/*
223 * PCI Bus clocking configuration
224 *
225 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200227 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
Wolfgang Denkeece1592005-08-10 11:03:05 +0200228 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200230#endif
231
232/*
233 * I2C configuration
234 */
235#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
236#ifdef CONFIG_TQM5200_REV100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200238#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200240#endif
241
242/*
243 * I2C clock frequency
244 *
245 * Please notice, that the resulting clock frequency could differ from the
246 * configured value. This is because the I2C clock is derived from system
247 * clock over a frequency divider with only a few divider values. U-boot
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
Wolfgang Denkeece1592005-08-10 11:03:05 +0200249 * approximation allways lies below the configured value, never above.
250 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
252#define CONFIG_SYS_I2C_SLAVE 0x7F
Wolfgang Denkeece1592005-08-10 11:03:05 +0200253
254/*
255 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
256 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
257 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
258 * same configuration could be used.
259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
261#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
262#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
263#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
Wolfgang Denkeece1592005-08-10 11:03:05 +0200264
265/*
266 * HW-Monitor configuration on Mini-FAP
267 */
268#if defined (CONFIG_MINIFAP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C
Wolfgang Denkeece1592005-08-10 11:03:05 +0200270#endif
271
272/* List of I2C addresses to be verified by POST */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200273#if defined (CONFIG_MINIFAP)
Peter Tyser60aaaa02010-10-22 00:20:30 -0500274#undef CONFIG_SYS_POST_I2C_ADDRS
275#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
276 CONFIG_SYS_I2C_HWMON_ADDR, \
277 CONFIG_SYS_I2C_SLAVE}
Wolfgang Denkeece1592005-08-10 11:03:05 +0200278#endif
279
280/*
281 * Flash configuration
282 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200283#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200284
285/* use CFI flash driver if no module variant is spezified */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200287#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
289#define CONFIG_SYS_FLASH_EMPTY_INFO
290#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
291#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
292#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200293
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#if !defined(CONFIG_SYS_LOWBOOT)
295#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
296#else /* CONFIG_SYS_LOWBOOT */
297#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
298#endif /* CONFIG_SYS_LOWBOOT */
299#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
Wolfgang Denkeece1592005-08-10 11:03:05 +0200300 (= chip selects) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
302#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200303
304
305/*
306 * Environment settings
307 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200308#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200309#define CONFIG_ENV_SIZE 0x10000
310#define CONFIG_ENV_SECT_SIZE 0x20000
311#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
312#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Wolfgang Denkeece1592005-08-10 11:03:05 +0200313
314/*
315 * Memory map
316 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_MBAR 0xF0000000
318#define CONFIG_SYS_SDRAM_BASE 0x00000000
319#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Wolfgang Denkeece1592005-08-10 11:03:05 +0200320
321/* Use ON-Chip SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denkeece1592005-08-10 11:03:05 +0200323#ifdef CONFIG_POST
324/* preserve space for the post_word at end of on-chip SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
Wolfgang Denkeece1592005-08-10 11:03:05 +0200326#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
Wolfgang Denkeece1592005-08-10 11:03:05 +0200328#endif
329
330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
332#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
333#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Wolfgang Denkeece1592005-08-10 11:03:05 +0200334
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200335#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
337# define CONFIG_SYS_RAMBOOT 1
Wolfgang Denkeece1592005-08-10 11:03:05 +0200338#endif
339
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
341#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
342#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200343
344/*
345 * Ethernet configuration
346 */
347#define CONFIG_MPC5xxx_FEC 1
348/*
349 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
350 */
351/* #define CONFIG_FEC_10MBIT 1 */
352#define CONFIG_PHY_ADDR 0x00
353
354/*
355 * GPIO configuration
356 *
357 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
358 * Bit 0 (mask: 0x80000000): 1
359 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
360 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
361 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
362 * Use for REV200 STK52XX boards. Do not use with REV100 modules
363 * (because, there I2C1 is used as I2C bus)
364 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
365 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
366 * 000 -> All PSC2 pins are GIOPs
367 * 001 -> CAN1/2 on PSC2 pins
368 * Use for REV100 STK52xx boards
369 * use PSC6:
370 * on STK52xx:
371 * use as UART. Pins PSC6_0 to PSC6_3 are used.
372 * Bits 9:11 (mask: 0x00700000):
373 * 101 -> PSC6 : Extended POST test is not available
374 * on MINI-FAP and TQM5200_IB:
375 * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
376 * 000 -> PSC6 could not be used as UART, CODEC or IrDA
377 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
378 * tests.
379 */
380#if defined (CONFIG_MINIFAP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
Wolfgang Denkeece1592005-08-10 11:03:05 +0200382#elif defined (CONFIG_STK52XX)
383# if defined (CONFIG_STK52XX_REV100)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
Wolfgang Denkeece1592005-08-10 11:03:05 +0200385# else /* STK52xx REV200 and above */
386# if defined (CONFIG_TQM5200_REV100)
387# error TQM5200 REV100 not supported on STK52XX REV200 or above
388# else/* TQM5200 REV200 and above */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500004
Wolfgang Denkeece1592005-08-10 11:03:05 +0200390# endif
391# endif
392#else /* TMQ5200 Inbetriebnahme-Board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
Wolfgang Denkeece1592005-08-10 11:03:05 +0200394#endif
395
396/*
397 * RTC configuration
398 */
399#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
400
401/*
402 * Miscellaneous configurable options
403 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_LONGHELP /* undef to save memory */
405#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500406#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200408#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200410#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
412#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
413#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200414
415/* Enable an alternate, more extensive memory test */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_ALT_MEMTEST
Wolfgang Denkeece1592005-08-10 11:03:05 +0200417
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
419#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200420
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200422
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200424
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500426#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500428#endif
429
Wolfgang Denkeece1592005-08-10 11:03:05 +0200430/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500431 * Enable loopw command.
Wolfgang Denkeece1592005-08-10 11:03:05 +0200432 */
433#define CONFIG_LOOPW
434
435/*
436 * Various low-level settings
437 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
439#define CONFIG_SYS_HID0_FINAL HID0_ICE
Wolfgang Denkeece1592005-08-10 11:03:05 +0200440
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
442#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
443#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
444#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200445#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200447#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
449#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Wolfgang Denkeece1592005-08-10 11:03:05 +0200450
Wolfgang Denkeece1592005-08-10 11:03:05 +0200451#define CONFIG_LAST_STAGE_INIT
Wolfgang Denkeece1592005-08-10 11:03:05 +0200452
453/*
454 * SRAM - Do not map below 2 GB in address space, because this area is used
455 * for SDRAM autosizing.
456 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_CS2_START 0xE5000000
458#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
459#define CONFIG_SYS_CS2_CFG 0x0004D930
Wolfgang Denkeece1592005-08-10 11:03:05 +0200460
461/*
462 * Grafic controller - Do not map below 2 GB in address space, because this
463 * area is used for SDRAM autosizing.
464 */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200465#define SM501_FB_BASE 0xE0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
467#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
468#define CONFIG_SYS_CS1_CFG 0x8F48FF70
469#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
Wolfgang Denkeece1592005-08-10 11:03:05 +0200470
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471#define CONFIG_SYS_CS_BURST 0x00000000
472#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200473
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Wolfgang Denkeece1592005-08-10 11:03:05 +0200475
476/*-----------------------------------------------------------------------
477 * USB stuff
478 *-----------------------------------------------------------------------
479 */
480#define CONFIG_USB_CLOCK 0x0001BBBB
481#define CONFIG_USB_CONFIG 0x00001000
482
483/*-----------------------------------------------------------------------
484 * IDE/ATA stuff Supports IDE harddisk
485 *-----------------------------------------------------------------------
486 */
487
488#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
489
490#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
491#undef CONFIG_IDE_LED /* LED for ide not supported */
492
493#define CONFIG_IDE_RESET /* reset for ide supported */
494#define CONFIG_IDE_PREINIT
495
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200496#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
497#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200498
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Wolfgang Denkeece1592005-08-10 11:03:05 +0200500
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200501#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
Wolfgang Denkeece1592005-08-10 11:03:05 +0200502
503/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
Wolfgang Denkeece1592005-08-10 11:03:05 +0200505
506/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200507#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
Wolfgang Denkeece1592005-08-10 11:03:05 +0200508
509/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
Wolfgang Denkeece1592005-08-10 11:03:05 +0200511
512/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200513#define CONFIG_SYS_ATA_STRIDE 4
Wolfgang Denkeece1592005-08-10 11:03:05 +0200514
515#endif /* __CONFIG_H */