blob: 5ab7d5f0e8c4c3cc322cd0d7c69687b45f9a6e00 [file] [log] [blame]
Dave Liu24c3aca2006-12-07 21:13:15 +08001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Dave Liu24c3aca2006-12-07 21:13:15 +08005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Kim Phillipsfdfaa292015-03-17 12:00:45 -050010#define CONFIG_DISPLAY_BOARDINFO
11
Dave Liu24c3aca2006-12-07 21:13:15 +080012/*
13 * High Level Configuration Options
14 */
15#define CONFIG_E300 1 /* E300 family */
16#define CONFIG_QE 1 /* Has QE */
Peter Tyser2c7920a2009-05-22 17:23:25 -050017#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
Dave Liu24c3aca2006-12-07 21:13:15 +080018#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020019
20#define CONFIG_SYS_TEXT_BASE 0xFE000000
Dave Liu24c3aca2006-12-07 21:13:15 +080021
22/*
23 * System Clock Setup
24 */
25#ifdef CONFIG_PCISLAVE
26#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
27#else
28#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
29#endif
30
31#ifndef CONFIG_SYS_CLK_FREQ
32#define CONFIG_SYS_CLK_FREQ 66000000
33#endif
34
35/*
36 * Hardware Reset Configuration Word
37 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#define CONFIG_SYS_HRCW_LOW (\
Dave Liu24c3aca2006-12-07 21:13:15 +080039 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
40 HRCWL_DDR_TO_SCB_CLK_2X1 |\
41 HRCWL_VCO_1X2 |\
42 HRCWL_CSB_TO_CLKIN_2X1 |\
43 HRCWL_CORE_TO_CSB_2X1 |\
44 HRCWL_CE_PLL_VCO_DIV_2 |\
45 HRCWL_CE_PLL_DIV_1X1 |\
46 HRCWL_CE_TO_PLL_1X3)
47
48#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu24c3aca2006-12-07 21:13:15 +080050 HRCWH_PCI_AGENT |\
51 HRCWH_PCI1_ARBITER_DISABLE |\
52 HRCWH_CORE_ENABLE |\
53 HRCWH_FROM_0XFFF00100 |\
54 HRCWH_BOOTSEQ_DISABLE |\
55 HRCWH_SW_WATCHDOG_DISABLE |\
56 HRCWH_ROM_LOC_LOCAL_16BIT |\
57 HRCWH_BIG_ENDIAN |\
58 HRCWH_LALE_NORMAL)
59#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu24c3aca2006-12-07 21:13:15 +080061 HRCWH_PCI_HOST |\
62 HRCWH_PCI1_ARBITER_ENABLE |\
63 HRCWH_CORE_ENABLE |\
64 HRCWH_FROM_0X00000100 |\
65 HRCWH_BOOTSEQ_DISABLE |\
66 HRCWH_SW_WATCHDOG_DISABLE |\
67 HRCWH_ROM_LOC_LOCAL_16BIT |\
68 HRCWH_BIG_ENDIAN |\
69 HRCWH_LALE_NORMAL)
70#endif
71
72/*
73 * System IO Config
74 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_SICRL 0x00000000
Dave Liu24c3aca2006-12-07 21:13:15 +080076
77#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
Tony Li14778582007-08-17 10:35:59 +080078#define CONFIG_BOARD_EARLY_INIT_R
Dave Liu24c3aca2006-12-07 21:13:15 +080079
80/*
81 * IMMR new address
82 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_IMMR 0xE0000000
Dave Liu24c3aca2006-12-07 21:13:15 +080084
85/*
86 * DDR Setup
87 */
Joe Hershberger989091a2011-10-11 23:57:13 -050088#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
89#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Joe Hershberger989091a2011-10-11 23:57:13 -050091#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
Dave Liu24c3aca2006-12-07 21:13:15 +080092
93#undef CONFIG_SPD_EEPROM
94#if defined(CONFIG_SPD_EEPROM)
95/* Determine DDR configuration from I2C interface
96 */
97#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
98#else
99/* Manually set up DDR parameters
100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_DDR_SIZE 128 /* MB */
Joe Hershberger2fef4022011-10-11 23:57:29 -0500102#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
103 | CSCONFIG_AP \
104 | CSCONFIG_ODT_WR_CFG \
105 | CSCONFIG_ROW_BIT_13 \
106 | CSCONFIG_COL_BIT_10)
107 /* 0x80840102 */
108#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
109 | (0 << TIMING_CFG0_WRT_SHIFT) \
110 | (0 << TIMING_CFG0_RRT_SHIFT) \
111 | (0 << TIMING_CFG0_WWT_SHIFT) \
112 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
113 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
114 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
115 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
116 /* 0x00220802 */
117#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
118 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
119 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
120 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
121 | (13 << TIMING_CFG1_REFREC_SHIFT) \
122 | (3 << TIMING_CFG1_WRREC_SHIFT) \
123 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
124 | (2 << TIMING_CFG1_WRTORD_SHIFT))
125 /* 0x3935D322 */
126#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
127 | (31 << TIMING_CFG2_CPO_SHIFT) \
128 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
129 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
130 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
131 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
132 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
133 /* 0x0F9048CA */
Joe Hershberger989091a2011-10-11 23:57:13 -0500134#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershberger2fef4022011-10-11 23:57:29 -0500135#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
136 /* 0x02000000 */
137#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
138 | (0x0232 << SDRAM_MODE_SD_SHIFT))
139 /* 0x44400232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_DDR_MODE2 0x8000c000
Joe Hershberger2fef4022011-10-11 23:57:29 -0500141#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
142 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
143 /* 0x03200064 */
Joe Hershberger989091a2011-10-11 23:57:13 -0500144#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
Joe Hershberger2fef4022011-10-11 23:57:29 -0500145#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
146 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
147 | SDRAM_CFG_32_BE)
148 /* 0x43080000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
Dave Liu24c3aca2006-12-07 21:13:15 +0800150#endif
151
152/*
153 * Memory test
154 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
156#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
157#define CONFIG_SYS_MEMTEST_END 0x00100000
Dave Liu24c3aca2006-12-07 21:13:15 +0800158
159/*
160 * The reserved memory
161 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200162#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Dave Liu24c3aca2006-12-07 21:13:15 +0800163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
165#define CONFIG_SYS_RAMBOOT
Dave Liu24c3aca2006-12-07 21:13:15 +0800166#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#undef CONFIG_SYS_RAMBOOT
Dave Liu24c3aca2006-12-07 21:13:15 +0800168#endif
169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Joe Hershberger989091a2011-10-11 23:57:13 -0500171#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Timur Tabi3b6b2562012-03-17 17:44:00 -0500172#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Dave Liu24c3aca2006-12-07 21:13:15 +0800173
174/*
175 * Initial RAM Base Address Setup
176 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershberger989091a2011-10-11 23:57:13 -0500178#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
179#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
180#define CONFIG_SYS_GBL_DATA_OFFSET \
181 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dave Liu24c3aca2006-12-07 21:13:15 +0800182
183/*
184 * Local Bus Configuration & Clock Setup
185 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500186#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
187#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_LBC_LBCR 0x00000000
Dave Liu24c3aca2006-12-07 21:13:15 +0800189
190/*
191 * FLASH on the Local Bus
192 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Joe Hershberger989091a2011-10-11 23:57:13 -0500194#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
195#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
196#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
197#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Dave Liu24c3aca2006-12-07 21:13:15 +0800198
Joe Hershberger989091a2011-10-11 23:57:13 -0500199 /* Window base at flash base */
200#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500201#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Dave Liu24c3aca2006-12-07 21:13:15 +0800202
Joe Hershberger989091a2011-10-11 23:57:13 -0500203#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500204 | BR_PS_16 /* 16 bit port */ \
205 | BR_MS_GPCM /* MSEL = GPCM */ \
206 | BR_V) /* valid */
207#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
208 | OR_GPCM_XAM \
209 | OR_GPCM_CSNT \
210 | OR_GPCM_ACS_DIV2 \
211 | OR_GPCM_XACS \
212 | OR_GPCM_SCY_15 \
213 | OR_GPCM_TRLX_SET \
214 | OR_GPCM_EHTR_SET \
215 | OR_GPCM_EAD)
216 /* 0xfe006ff7 */
Dave Liu24c3aca2006-12-07 21:13:15 +0800217
Joe Hershberger989091a2011-10-11 23:57:13 -0500218#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
219#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
Dave Liu24c3aca2006-12-07 21:13:15 +0800220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#undef CONFIG_SYS_FLASH_CHECKSUM
Dave Liu24c3aca2006-12-07 21:13:15 +0800222
223/*
224 * BCSR on the Local Bus
225 */
Joe Hershberger989091a2011-10-11 23:57:13 -0500226#define CONFIG_SYS_BCSR 0xF8000000
227 /* Access window base at BCSR base */
228#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500229#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Dave Liu24c3aca2006-12-07 21:13:15 +0800230
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500231#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
232 | BR_PS_8 \
233 | BR_MS_GPCM \
234 | BR_V)
235#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
236 | OR_GPCM_XAM \
237 | OR_GPCM_CSNT \
238 | OR_GPCM_XACS \
239 | OR_GPCM_SCY_15 \
240 | OR_GPCM_TRLX_SET \
241 | OR_GPCM_EHTR_SET \
242 | OR_GPCM_EAD)
243 /* 0xFFFFE9F7 */
Dave Liu24c3aca2006-12-07 21:13:15 +0800244
245/*
246 * Windows to access PIB via local bus
247 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500248 /* PIB window base 0xF8008000 */
249#define CONFIG_SYS_PIB_BASE 0xF8008000
250#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
251#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE
252#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
Dave Liu24c3aca2006-12-07 21:13:15 +0800253
254/*
255 * CS2 on Local Bus, to PIB
256 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500257#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
258 | BR_PS_8 \
259 | BR_MS_GPCM \
260 | BR_V)
261 /* 0xF8008801 */
262#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
263 | OR_GPCM_XAM \
264 | OR_GPCM_CSNT \
265 | OR_GPCM_XACS \
266 | OR_GPCM_SCY_15 \
267 | OR_GPCM_TRLX_SET \
268 | OR_GPCM_EHTR_SET \
269 | OR_GPCM_EAD)
270 /* 0xffffe9f7 */
Dave Liu24c3aca2006-12-07 21:13:15 +0800271
272/*
273 * CS3 on Local Bus, to PIB
274 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500275#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
276 CONFIG_SYS_PIB_WINDOW_SIZE) \
277 | BR_PS_8 \
278 | BR_MS_GPCM \
279 | BR_V)
280 /* 0xF8010801 */
281#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
282 | OR_GPCM_XAM \
283 | OR_GPCM_CSNT \
284 | OR_GPCM_XACS \
285 | OR_GPCM_SCY_15 \
286 | OR_GPCM_TRLX_SET \
287 | OR_GPCM_EHTR_SET \
288 | OR_GPCM_EAD)
289 /* 0xffffe9f7 */
Dave Liu24c3aca2006-12-07 21:13:15 +0800290
291/*
292 * Serial Port
293 */
294#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_NS16550
296#define CONFIG_SYS_NS16550_SERIAL
297#define CONFIG_SYS_NS16550_REG_SIZE 1
298#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Dave Liu24c3aca2006-12-07 21:13:15 +0800299
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger989091a2011-10-11 23:57:13 -0500301 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Dave Liu24c3aca2006-12-07 21:13:15 +0800302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
304#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Dave Liu24c3aca2006-12-07 21:13:15 +0800305
Kim Phillips22d71a72007-02-27 18:41:08 -0600306#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500307#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Dave Liu24c3aca2006-12-07 21:13:15 +0800308/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_HUSH_PARSER
Dave Liu24c3aca2006-12-07 21:13:15 +0800310
311/* pass open firmware flat tree */
Kim Phillips35cc4e42007-08-15 22:30:39 -0500312#define CONFIG_OF_LIBFDT 1
Dave Liu24c3aca2006-12-07 21:13:15 +0800313#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600314#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Dave Liu24c3aca2006-12-07 21:13:15 +0800315
316/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200317#define CONFIG_SYS_I2C
318#define CONFIG_SYS_I2C_FSL
319#define CONFIG_SYS_FSL_I2C_SPEED 400000
320#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
321#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
322#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
Dave Liu24c3aca2006-12-07 21:13:15 +0800323
324/*
325 * Config on-board RTC
326 */
327#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Dave Liu24c3aca2006-12-07 21:13:15 +0800329
330/*
331 * General PCI
332 * Addresses are mapped 1-1.
333 */
Kim Phillips9993e192009-07-18 18:42:13 -0500334#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
335#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
336#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
337#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
338#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
339#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
340#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
341#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
342#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
Dave Liu24c3aca2006-12-07 21:13:15 +0800343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
345#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
346#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Dave Liu24c3aca2006-12-07 21:13:15 +0800347
348
349#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000350#define CONFIG_PCI_INDIRECT_BRIDGE
Dave Liu24c3aca2006-12-07 21:13:15 +0800351
Dave Liu24c3aca2006-12-07 21:13:15 +0800352#define CONFIG_PCI_PNP /* do pci plug-and-play */
Kim Phillips9993e192009-07-18 18:42:13 -0500353#define CONFIG_83XX_PCI_STREAMING
Dave Liu24c3aca2006-12-07 21:13:15 +0800354
355#undef CONFIG_EEPRO100
356#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liu24c3aca2006-12-07 21:13:15 +0800358
359#endif /* CONFIG_PCI */
360
Dave Liu24c3aca2006-12-07 21:13:15 +0800361/*
362 * QE UEC ethernet configuration
363 */
364#define CONFIG_UEC_ETH
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500365#define CONFIG_ETHPRIME "UEC0"
Dave Liu24c3aca2006-12-07 21:13:15 +0800366
367#define CONFIG_UEC_ETH1 /* ETH3 */
368
369#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
371#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
372#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
373#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
374#define CONFIG_SYS_UEC1_PHY_ADDR 3
Andy Fleming865ff852011-04-13 00:37:12 -0500375#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100376#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
Dave Liu24c3aca2006-12-07 21:13:15 +0800377#endif
378
379#define CONFIG_UEC_ETH2 /* ETH4 */
380
381#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
383#define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
384#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
385#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
386#define CONFIG_SYS_UEC2_PHY_ADDR 4
Andy Fleming865ff852011-04-13 00:37:12 -0500387#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100388#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
Dave Liu24c3aca2006-12-07 21:13:15 +0800389#endif
390
391/*
392 * Environment
393 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200395 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger989091a2011-10-11 23:57:13 -0500396 #define CONFIG_ENV_ADDR \
397 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200398 #define CONFIG_ENV_SECT_SIZE 0x20000
399 #define CONFIG_ENV_SIZE 0x2000
Dave Liu24c3aca2006-12-07 21:13:15 +0800400#else
Joe Hershberger989091a2011-10-11 23:57:13 -0500401 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200402 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200404 #define CONFIG_ENV_SIZE 0x2000
Dave Liu24c3aca2006-12-07 21:13:15 +0800405#endif
406
407#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dave Liu24c3aca2006-12-07 21:13:15 +0800409
Jon Loeliger8ea54992007-07-04 22:30:06 -0500410/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500411 * BOOTP options
412 */
413#define CONFIG_BOOTP_BOOTFILESIZE
414#define CONFIG_BOOTP_BOOTPATH
415#define CONFIG_BOOTP_GATEWAY
416#define CONFIG_BOOTP_HOSTNAME
417
418
419/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500420 * Command line configuration.
421 */
Jon Loeliger8ea54992007-07-04 22:30:06 -0500422#define CONFIG_CMD_PING
423#define CONFIG_CMD_I2C
424#define CONFIG_CMD_ASKENV
425
Dave Liu24c3aca2006-12-07 21:13:15 +0800426#if defined(CONFIG_PCI)
Jon Loeliger8ea54992007-07-04 22:30:06 -0500427 #define CONFIG_CMD_PCI
Dave Liu24c3aca2006-12-07 21:13:15 +0800428#endif
429
Dave Liu24c3aca2006-12-07 21:13:15 +0800430#undef CONFIG_WATCHDOG /* watchdog disabled */
431
432/*
433 * Miscellaneous configurable options
434 */
Joe Hershberger989091a2011-10-11 23:57:13 -0500435#define CONFIG_SYS_LONGHELP /* undef to save memory */
436#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Dave Liu24c3aca2006-12-07 21:13:15 +0800437
Jon Loeliger8ea54992007-07-04 22:30:06 -0500438#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dave Liu24c3aca2006-12-07 21:13:15 +0800440#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dave Liu24c3aca2006-12-07 21:13:15 +0800442#endif
443
Joe Hershberger989091a2011-10-11 23:57:13 -0500444 /* Print Buffer Size */
445#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
446#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
447 /* Boot Argument Buffer Size */
448#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Dave Liu24c3aca2006-12-07 21:13:15 +0800449
450/*
451 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700452 * have to be in the first 256 MB of memory, since this is
Dave Liu24c3aca2006-12-07 21:13:15 +0800453 * the maximum mapped by the Linux kernel during initialization.
454 */
Joe Hershberger989091a2011-10-11 23:57:13 -0500455 /* Initial Memory map for Linux */
456#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Dave Liu24c3aca2006-12-07 21:13:15 +0800457
458/*
459 * Core HID Setup
460 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500461#define CONFIG_SYS_HID0_INIT 0x000000000
462#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
463 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464#define CONFIG_SYS_HID2 HID2_HBE
Dave Liu24c3aca2006-12-07 21:13:15 +0800465
466/*
Dave Liu24c3aca2006-12-07 21:13:15 +0800467 * MMU Setup
468 */
469
Becky Bruce31d82672008-05-08 19:02:12 -0500470#define CONFIG_HIGH_BATS 1 /* High BATs supported */
471
Dave Liu24c3aca2006-12-07 21:13:15 +0800472/* DDR: cache cacheable */
Joe Hershberger989091a2011-10-11 23:57:13 -0500473#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500474 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500475 | BATL_MEMCOHERENCE)
476#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
477 | BATU_BL_256M \
478 | BATU_VS \
479 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
481#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Dave Liu24c3aca2006-12-07 21:13:15 +0800482
483/* IMMRBAR & PCI IO: cache-inhibit and guarded */
Joe Hershberger989091a2011-10-11 23:57:13 -0500484#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500485 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500486 | BATL_CACHEINHIBIT \
487 | BATL_GUARDEDSTORAGE)
488#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
489 | BATU_BL_4M \
490 | BATU_VS \
491 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200492#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
493#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Dave Liu24c3aca2006-12-07 21:13:15 +0800494
495/* BCSR: cache-inhibit and guarded */
Joe Hershberger989091a2011-10-11 23:57:13 -0500496#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500497 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500498 | BATL_CACHEINHIBIT \
499 | BATL_GUARDEDSTORAGE)
500#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
501 | BATU_BL_128K \
502 | BATU_VS \
503 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
505#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Dave Liu24c3aca2006-12-07 21:13:15 +0800506
507/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger989091a2011-10-11 23:57:13 -0500508#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500509 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500510 | BATL_MEMCOHERENCE)
511#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
512 | BATU_BL_32M \
513 | BATU_VS \
514 | BATU_VP)
515#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500516 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500517 | BATL_CACHEINHIBIT \
518 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200519#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Dave Liu24c3aca2006-12-07 21:13:15 +0800520
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200521#define CONFIG_SYS_IBAT4L (0)
522#define CONFIG_SYS_IBAT4U (0)
523#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
524#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Dave Liu24c3aca2006-12-07 21:13:15 +0800525
526/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500527#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger989091a2011-10-11 23:57:13 -0500528#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
529 | BATU_BL_128K \
530 | BATU_VS \
531 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200532#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
533#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Dave Liu24c3aca2006-12-07 21:13:15 +0800534
535#ifdef CONFIG_PCI
536/* PCI MEM space: cacheable */
Joe Hershberger989091a2011-10-11 23:57:13 -0500537#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500538 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500539 | BATL_MEMCOHERENCE)
540#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
541 | BATU_BL_256M \
542 | BATU_VS \
543 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200544#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
545#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Dave Liu24c3aca2006-12-07 21:13:15 +0800546/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger989091a2011-10-11 23:57:13 -0500547#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500548 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500549 | BATL_CACHEINHIBIT \
550 | BATL_GUARDEDSTORAGE)
551#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
552 | BATU_BL_256M \
553 | BATU_VS \
554 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200555#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
556#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu24c3aca2006-12-07 21:13:15 +0800557#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200558#define CONFIG_SYS_IBAT6L (0)
559#define CONFIG_SYS_IBAT6U (0)
560#define CONFIG_SYS_IBAT7L (0)
561#define CONFIG_SYS_IBAT7U (0)
562#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
563#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
564#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
565#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu24c3aca2006-12-07 21:13:15 +0800566#endif
567
Jon Loeliger8ea54992007-07-04 22:30:06 -0500568#if defined(CONFIG_CMD_KGDB)
Dave Liu24c3aca2006-12-07 21:13:15 +0800569#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Dave Liu24c3aca2006-12-07 21:13:15 +0800570#endif
571
572/*
573 * Environment Configuration
Kim Phillips9993e192009-07-18 18:42:13 -0500574 */ #define CONFIG_ENV_OVERWRITE
Dave Liu24c3aca2006-12-07 21:13:15 +0800575
576#if defined(CONFIG_UEC_ETH)
Kim Phillips977b5752008-01-09 15:24:06 -0600577#define CONFIG_HAS_ETH0
Dave Liu24c3aca2006-12-07 21:13:15 +0800578#define CONFIG_HAS_ETH1
Dave Liu24c3aca2006-12-07 21:13:15 +0800579#endif
580
581#define CONFIG_BAUDRATE 115200
582
Kim Phillips79f516b2009-08-21 16:34:38 -0500583#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Dave Liu24c3aca2006-12-07 21:13:15 +0800584
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200585#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
Dave Liu24c3aca2006-12-07 21:13:15 +0800586#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
587
588#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger989091a2011-10-11 23:57:13 -0500589 "netdev=eth0\0" \
590 "consoledev=ttyS0\0" \
591 "ramdiskaddr=1000000\0" \
592 "ramdiskfile=ramfs.83xx\0" \
593 "fdtaddr=780000\0" \
594 "fdtfile=mpc832x_mds.dtb\0" \
595 ""
Dave Liu24c3aca2006-12-07 21:13:15 +0800596
597#define CONFIG_NFSBOOTCOMMAND \
Joe Hershberger989091a2011-10-11 23:57:13 -0500598 "setenv bootargs root=/dev/nfs rw " \
599 "nfsroot=$serverip:$rootpath " \
600 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
601 "$netdev:off " \
602 "console=$consoledev,$baudrate $othbootargs;" \
603 "tftp $loadaddr $bootfile;" \
604 "tftp $fdtaddr $fdtfile;" \
605 "bootm $loadaddr - $fdtaddr"
Dave Liu24c3aca2006-12-07 21:13:15 +0800606
607#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger989091a2011-10-11 23:57:13 -0500608 "setenv bootargs root=/dev/ram rw " \
609 "console=$consoledev,$baudrate $othbootargs;" \
610 "tftp $ramdiskaddr $ramdiskfile;" \
611 "tftp $loadaddr $bootfile;" \
612 "tftp $fdtaddr $fdtfile;" \
613 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Dave Liu24c3aca2006-12-07 21:13:15 +0800614
615
616#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
617
618#endif /* __CONFIG_H */