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wdenk56f94be2002-11-05 16:35:14 +00001/*
Heiko Schochere604e402010-07-19 23:46:48 +02002 * (C) Copyright 2000-2010
wdenk56f94be2002-11-05 16:35:14 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk0608e042004-03-25 19:29:38 +000016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk56f94be2002-11-05 16:35:14 +000017 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * board/config.h - configuration options, board specific
27 * Derived from ../tqm8xx/tqm8xx.c
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
39#define CONFIG_KUP4K 1 /* ...on a KUP4K module */
40
Wolfgang Denk2ae18242010-10-06 09:05:45 +020041#define CONFIG_SYS_TEXT_BASE 0x40000000
42
wdenk0608e042004-03-25 19:29:38 +000043#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
wdenk56f94be2002-11-05 16:35:14 +000044#undef CONFIG_8xx_CONS_SMC2
45#undef CONFIG_8xx_CONS_NONE
wdenk682011f2003-06-03 23:54:09 +000046#define CONFIG_BAUDRATE 115200 /* console baudrate */
wdenk682011f2003-06-03 23:54:09 +000047#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
wdenk56f94be2002-11-05 16:35:14 +000048
wdenk56f94be2002-11-05 16:35:14 +000049#define CONFIG_BOARD_TYPES 1 /* support board types */
50
wdenk56f94be2002-11-05 16:35:14 +000051#undef CONFIG_BOOTARGS
52
wdenk0608e042004-03-25 19:29:38 +000053#define CONFIG_EXTRA_ENV_SETTINGS \
Heiko Schochere604e402010-07-19 23:46:48 +020054"slot_a_boot=setenv bootargs root=/dev/sda2 ip=off;" \
Wolfgang Denk2d941de2010-09-10 00:16:19 +020055 "run addhw; mw.b 400000 00 80; diskboot 400000 0:1; bootm 400000\0" \
Heiko Schochere604e402010-07-19 23:46:48 +020056"slot_b_boot=setenv bootargs root=/dev/sda2 ip=off;" \
Wolfgang Denk2d941de2010-09-10 00:16:19 +020057 "run addhw; mw.b 400000 00 80; diskboot 400000 2:1; bootm 400000\0" \
Heiko Schochere604e402010-07-19 23:46:48 +020058"nfs_boot=mw.b 400000 00 80; dhcp; run nfsargs addip addhw; bootm 400000\0" \
59"fat_boot=mw.b 400000 00 80; fatload ide 2:1 400000 st.bin; run addhw; \
60 bootm 400000 \0" \
wdenk0608e042004-03-25 19:29:38 +000061"panic_boot=echo No Bootdevice !!! reset\0" \
Heiko Schochere604e402010-07-19 23:46:48 +020062"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}\0" \
wdenk0608e042004-03-25 19:29:38 +000063"ramargs=setenv bootargs root=/dev/ram rw\0" \
Heiko Schochere604e402010-07-19 23:46:48 +020064"addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010065 ":${netmask}:${hostname}:${netdev}:off\0" \
Heiko Schochere604e402010-07-19 23:46:48 +020066"addhw=setenv bootargs ${bootargs} ${mtdparts} console=${console} ${debug} \
67 hw=${hw} key1=${key1} panic=1 mem=${mem}\0" \
68"console=ttyCPM0,115200\0" \
wdenk0608e042004-03-25 19:29:38 +000069"netdev=eth0\0" \
Heiko Schochere604e402010-07-19 23:46:48 +020070"contrast=20\0" \
wdenk0608e042004-03-25 19:29:38 +000071"silent=1\0" \
Heiko Schochere604e402010-07-19 23:46:48 +020072"mtdparts=" MTDPARTS_DEFAULT "\0" \
wdenk0608e042004-03-25 19:29:38 +000073"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \
Heiko Schochere604e402010-07-19 23:46:48 +020074"update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};" \
wdenk02b11f82004-05-12 22:54:36 +000075 "cp.b 200000 40050000 14000\0"
wdenk56f94be2002-11-05 16:35:14 +000076
wdenk682011f2003-06-03 23:54:09 +000077#define CONFIG_BOOTCOMMAND \
Heiko Schochere604e402010-07-19 23:46:48 +020078 "run fat_boot;run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot"
wdenk682011f2003-06-03 23:54:09 +000079
Heiko Schochere604e402010-07-19 23:46:48 +020080#define CONFIG_PREBOOT "setenv preboot; saveenv"
wdenk56f94be2002-11-05 16:35:14 +000081
wdenk0608e042004-03-25 19:29:38 +000082#define CONFIG_MISC_INIT_R 1
83#define CONFIG_MISC_INIT_F 1
wdenk56f94be2002-11-05 16:35:14 +000084
85#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Heiko Schochere604e402010-07-19 23:46:48 +020086#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk56f94be2002-11-05 16:35:14 +000087
wdenk02b11f82004-05-12 22:54:36 +000088#define CONFIG_WATCHDOG 1 /* watchdog enabled */
wdenk56f94be2002-11-05 16:35:14 +000089
wdenk0608e042004-03-25 19:29:38 +000090#define CONFIG_STATUS_LED 1 /* Status LED enabled */
wdenk56f94be2002-11-05 16:35:14 +000091
92#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
93
Jon Loeliger7be044e2007-07-09 21:24:19 -050094/*
95 * BOOTP options
96 */
97#define CONFIG_BOOTP_SUBNETMASK
98#define CONFIG_BOOTP_GATEWAY
99#define CONFIG_BOOTP_HOSTNAME
100#define CONFIG_BOOTP_BOOTPATH
101#define CONFIG_BOOTP_BOOTFILESIZE
102
wdenk56f94be2002-11-05 16:35:14 +0000103#define CONFIG_MAC_PARTITION
104#define CONFIG_DOS_PARTITION
105
wdenk02b11f82004-05-12 22:54:36 +0000106/*
107 * enable I2C and select the hardware/software driver
108 */
Heiko Schochere604e402010-07-19 23:46:48 +0200109#undef CONFIG_HARD_I2C /* I2C with hardware support */
Wolfgang Denk2d941de2010-09-10 00:16:19 +0200110#define CONFIG_SOFT_I2C /* I2C bit-banged */
wdenk0608e042004-03-25 19:29:38 +0000111
Heiko Schochere604e402010-07-19 23:46:48 +0200112#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
113#define CONFIG_SYS_I2C_SLAVE 0xFE
wdenk02b11f82004-05-12 22:54:36 +0000114
115#ifdef CONFIG_SOFT_I2C
116/*
117 * Software (bit-bang) I2C driver configuration
118 */
119#define PB_SCL 0x00000020 /* PB 26 */
120#define PB_SDA 0x00000010 /* PB 27 */
121
122#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
123#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
124#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
125#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
126#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
127 else immr->im_cpm.cp_pbdat &= ~PB_SDA
128#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
129 else immr->im_cpm.cp_pbdat &= ~PB_SCL
130#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
131#endif /* CONFIG_SOFT_I2C */
132
wdenk02b11f82004-05-12 22:54:36 +0000133/*-----------------------------------------------------------------------
134 * I2C Configuration
135 */
136
Heiko Schochere604e402010-07-19 23:46:48 +0200137#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
138#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
wdenk02b11f82004-05-12 22:54:36 +0000139
140/* List of I2C addresses to be verified by POST */
141
Peter Tyser60aaaa02010-10-22 00:20:30 -0500142#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \
143 CONFIG_SYS_I2C_RTC_ADDR, \
144 }
wdenk02b11f82004-05-12 22:54:36 +0000145
wdenk02b11f82004-05-12 22:54:36 +0000146#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_DISCOVER_PHY
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200149#define CONFIG_MII
wdenk02b11f82004-05-12 22:54:36 +0000150
wdenk56f94be2002-11-05 16:35:14 +0000151/* Define to allow the user to overwrite serial and ethaddr */
152#define CONFIG_ENV_OVERWRITE
wdenk56f94be2002-11-05 16:35:14 +0000153
Jon Loeliger348f2582007-07-08 13:46:18 -0500154/*
155 * Command line configuration.
156 */
157#include <config_cmd_default.h>
158
159#define CONFIG_CMD_DATE
160#define CONFIG_CMD_DHCP
161#define CONFIG_CMD_I2C
162#define CONFIG_CMD_IDE
Heiko Schochere604e402010-07-19 23:46:48 +0200163#define CONFIG_CMD_MII
Jon Loeliger348f2582007-07-08 13:46:18 -0500164#define CONFIG_CMD_NFS
Heiko Schochere604e402010-07-19 23:46:48 +0200165#define CONFIG_CMD_FAT
Jon Loeliger348f2582007-07-08 13:46:18 -0500166#define CONFIG_CMD_SNTP
167
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500168#ifdef CONFIG_POST
169 #define CONFIG_CMD_DIAG
170#endif
wdenk56f94be2002-11-05 16:35:14 +0000171
172/*
173 * Miscellaneous configurable options
174 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_LONGHELP /* undef to save memory */
176#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger348f2582007-07-08 13:46:18 -0500177#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk56f94be2002-11-05 16:35:14 +0000179#else
Heiko Schochere604e402010-07-19 23:46:48 +0200180#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
wdenk56f94be2002-11-05 16:35:14 +0000181#endif
Heiko Schochere604e402010-07-19 23:46:48 +0200182/* Print Buffer Size */
183#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
185#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk56f94be2002-11-05 16:35:14 +0000186
Heiko Schochere604e402010-07-19 23:46:48 +0200187#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */
188#define CONFIG_SYS_MEMTEST_END 0x005C00000 /* 4 ... 92 MB in DRAM */
189#define CONFIG_SYS_ALT_MEMTEST 1
190#define CONFIG_SYS_MEMTEST_SCRATCH 0x90000200 /* using latch as scratch register */
wdenk56f94be2002-11-05 16:35:14 +0000191
Heiko Schochere604e402010-07-19 23:46:48 +0200192#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
wdenk56f94be2002-11-05 16:35:14 +0000193
Heiko Schochere604e402010-07-19 23:46:48 +0200194#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk56f94be2002-11-05 16:35:14 +0000195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
wdenk56f94be2002-11-05 16:35:14 +0000197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
wdenk682011f2003-06-03 23:54:09 +0000199
wdenk56f94be2002-11-05 16:35:14 +0000200/*
201 * Low Level Configuration Settings
202 * (address mappings, register initial values, etc.)
203 * You should know what you are doing if you make changes here.
204 */
205/*-----------------------------------------------------------------------
206 * Internal Memory Mapped Register
207 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_IMMR 0xFFF00000
wdenk56f94be2002-11-05 16:35:14 +0000209
210/*-----------------------------------------------------------------------
211 * Definitions for initial stack pointer and data area (in DPRAM)
212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200214#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200215#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk56f94be2002-11-05 16:35:14 +0000217
218/*-----------------------------------------------------------------------
219 * Start addresses for the final memory configuration
220 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk56f94be2002-11-05 16:35:14 +0000222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_SDRAM_BASE 0x00000000
224#define CONFIG_SYS_FLASH_BASE 0x40000000
225#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
226#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
227#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk56f94be2002-11-05 16:35:14 +0000228
229/*
230 * For booting Linux, the board info and command line data
231 * have to be in the first 8 MB of memory, since this is
232 * the maximum mapped by the Linux kernel during initialization.
233 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk56f94be2002-11-05 16:35:14 +0000235
236/*-----------------------------------------------------------------------
237 * FLASH organization
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
240#define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
wdenk56f94be2002-11-05 16:35:14 +0000241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
243#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk56f94be2002-11-05 16:35:14 +0000244
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200245#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200246#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
247#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
248#define CONFIG_ENV_SECT_SIZE 0x10000
wdenk56f94be2002-11-05 16:35:14 +0000249
Heiko Schochere604e402010-07-19 23:46:48 +0200250/*-----------------------------------------------------------------------
251 * Dynamic MTD partition support
252 */
253#define MTDPARTS_DEFAULT "mtdparts=40000000.flash:256k(u-boot)," \
Wolfgang Denk2d941de2010-09-10 00:16:19 +0200254 "64k(env)," \
255 "128k(splash)," \
256 "512k(etc)," \
257 "64k(hw-info)"
Heiko Schochere604e402010-07-19 23:46:48 +0200258
wdenk56f94be2002-11-05 16:35:14 +0000259/*-----------------------------------------------------------------------
260 * Hardware Information Block
261 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */
263#define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */
Heiko Schochere604e402010-07-19 23:46:48 +0200264#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
265
wdenk56f94be2002-11-05 16:35:14 +0000266/*-----------------------------------------------------------------------
267 * Cache Configuration
268 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger348f2582007-07-08 13:46:18 -0500270#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk56f94be2002-11-05 16:35:14 +0000272#endif
273
274/*-----------------------------------------------------------------------
275 * SYPCR - System Protection Control 11-9
276 * SYPCR can only be written once after reset!
277 *-----------------------------------------------------------------------
278 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
279 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk56f94be2002-11-05 16:35:14 +0000281
282/*-----------------------------------------------------------------------
283 * SIUMCR - SIU Module Configuration 11-6
284 *-----------------------------------------------------------------------
285 * PCMCIA config., multi-function pin tri-state
286 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
wdenk56f94be2002-11-05 16:35:14 +0000288
289/*-----------------------------------------------------------------------
290 * TBSCR - Time Base Status and Control 11-26
291 *-----------------------------------------------------------------------
292 * Clear Reference Interrupt Status, Timebase freezing enabled
293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenk56f94be2002-11-05 16:35:14 +0000295
296/*-----------------------------------------------------------------------
297 * RTCSC - Real-Time Clock Status and Control Register 11-27
298 *-----------------------------------------------------------------------
299 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenk56f94be2002-11-05 16:35:14 +0000301
302/*-----------------------------------------------------------------------
303 * PISCR - Periodic Interrupt Status and Control 11-31
304 *-----------------------------------------------------------------------
305 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
306 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk56f94be2002-11-05 16:35:14 +0000308
309/*-----------------------------------------------------------------------
310 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
311 *-----------------------------------------------------------------------
312 * Reset PLL lock status sticky bit, timer expired status bit and timer
313 * interrupt status bit
314 *
315 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
316 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
wdenk56f94be2002-11-05 16:35:14 +0000318
319/*-----------------------------------------------------------------------
320 * SCCR - System Clock and reset Control Register 15-27
321 *-----------------------------------------------------------------------
322 * Set clock output, timebase and RTC source and divider,
323 * power management and some other internal clocks
324 */
325#define SCCR_MASK SCCR_EBDF00
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | \
wdenk56f94be2002-11-05 16:35:14 +0000327 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
328 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
329 SCCR_DFALCD00)
330
331/*-----------------------------------------------------------------------
332 * PCMCIA stuff
333 *-----------------------------------------------------------------------
334 *
335 */
336
wdenkea909b72002-11-21 23:11:29 +0000337/* KUP4K use both slots, SLOT_A as "primary". */
wdenk0608e042004-03-25 19:29:38 +0000338#define CONFIG_PCMCIA_SLOT_A 1
wdenk56f94be2002-11-05 16:35:14 +0000339
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
341#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
342#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
343#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
344#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
345#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
346#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
347#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk56f94be2002-11-05 16:35:14 +0000348
wdenkea909b72002-11-21 23:11:29 +0000349#define PCMCIA_SOCKETS_NO 2
350#define PCMCIA_MEM_WIN_NO 8
wdenk56f94be2002-11-05 16:35:14 +0000351/*-----------------------------------------------------------------------
352 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
353 *-----------------------------------------------------------------------
354 */
355
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000356#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenk0608e042004-03-25 19:29:38 +0000357#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
wdenk56f94be2002-11-05 16:35:14 +0000358
wdenk0608e042004-03-25 19:29:38 +0000359#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
360#define CONFIG_IDE_LED 1 /* LED for ide supported */
wdenk56f94be2002-11-05 16:35:14 +0000361#undef CONFIG_IDE_RESET /* reset for ide not supported */
362
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#define CONFIG_SYS_IDE_MAXBUS 2
364#define CONFIG_SYS_IDE_MAXDEVICE 4
wdenk56f94be2002-11-05 16:35:14 +0000365
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk56f94be2002-11-05 16:35:14 +0000367
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE)
wdenkea909b72002-11-21 23:11:29 +0000369
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk56f94be2002-11-05 16:35:14 +0000371
372/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk56f94be2002-11-05 16:35:14 +0000374
375/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk56f94be2002-11-05 16:35:14 +0000377
378/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenk56f94be2002-11-05 16:35:14 +0000380
wdenk56f94be2002-11-05 16:35:14 +0000381/*-----------------------------------------------------------------------
382 *
383 *-----------------------------------------------------------------------
384 *
385 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_DER 0
wdenk56f94be2002-11-05 16:35:14 +0000387
388/*
389 * Init Memory Controller:
390 *
391 * BR0/1 and OR0/1 (FLASH)
392 */
393#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
394
395/* used to re-map FLASH both when starting from SRAM or FLASH:
396 * restrict access enough to keep SRAM working (if any)
397 * but not too much to meddle with FLASH accesses
398 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
400#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenk56f94be2002-11-05 16:35:14 +0000401
402/*
403 * FLASH timing:
404 */
Heiko Schochere604e402010-07-19 23:46:48 +0200405#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_CSNT_SAM | \
406 OR_SCY_5_CLK | OR_EHTR | OR_BI)
wdenk56f94be2002-11-05 16:35:14 +0000407
Heiko Schochere604e402010-07-19 23:46:48 +0200408#define CONFIG_SYS_OR0_REMAP \
409 (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
410#define CONFIG_SYS_OR0_PRELIM \
411 (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
412#define CONFIG_SYS_BR0_PRELIM \
413 ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
wdenk56f94be2002-11-05 16:35:14 +0000414
415
wdenk56f94be2002-11-05 16:35:14 +0000416/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenk56f94be2002-11-05 16:35:14 +0000418
wdenk56f94be2002-11-05 16:35:14 +0000419/*
420 * Memory Periodic Timer Prescaler
421 *
422 * The Divider for PTA (refresh timer) configuration is based on an
423 * example SDRAM configuration (64 MBit, one bank). The adjustment to
424 * the number of chip selects (NCS) and the actually needed refresh
425 * rate is done by setting MPTPR.
426 *
427 * PTA is calculated from
428 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
429 *
430 * gclk CPU clock (not bus clock!)
431 * Trefresh Refresh cycle * 4 (four word bursts used)
432 *
wdenk0608e042004-03-25 19:29:38 +0000433 * 4096 Rows from SDRAM example configuration
434 * 1000 factor s -> ms
435 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
436 * 4 Number of refresh cycles per period
437 * 64 Refresh cycle in ms per number of rows
wdenk56f94be2002-11-05 16:35:14 +0000438 * --------------------------------------------
439 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
440 *
441 * 50 MHz => 50.000.000 / Divider = 98
442 * 66 Mhz => 66.000.000 / Divider = 129
443 * 80 Mhz => 80.000.000 / Divider = 156
444 */
445#if defined(CONFIG_80MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446#define CONFIG_SYS_MAMR_PTA 156
wdenk56f94be2002-11-05 16:35:14 +0000447#elif defined(CONFIG_66MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_MAMR_PTA 129
wdenk56f94be2002-11-05 16:35:14 +0000449#else /* 50 MHz */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_MAMR_PTA 98
wdenk56f94be2002-11-05 16:35:14 +0000451#endif /*CONFIG_??MHz */
452
453/*
454 * For 16 MBit, refresh rates could be 31.3 us
455 * (= 64 ms / 2K = 125 / quad bursts).
456 * For a simpler initialization, 15.6 us is used instead.
457 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
459 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenk56f94be2002-11-05 16:35:14 +0000460 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461#define CONFIG_SYS_MPTPR 0x400
wdenk56f94be2002-11-05 16:35:14 +0000462
463/*
464 * MAMR settings for SDRAM
465 */
Heiko Schochere604e402010-07-19 23:46:48 +0200466
467/* 8 column SDRAM */
468#define CONFIG_SYS_MAMR_8COL 0x68802114
469/* 9 column SDRAM */
470#define CONFIG_SYS_MAMR_9COL 0x68904114
471
472/*
473 * Chip Selects
474 */
475#define CONFIG_SYS_OR0
476#define CONFIG_SYS_BR0
477
478#define CONFIG_SYS_OR1_8COL 0xFF000A00
479#define CONFIG_SYS_BR1_8COL 0x00000081
480#define CONFIG_SYS_OR2_8COL 0xFE000A00
481#define CONFIG_SYS_BR2_8COL 0x01000081
482#define CONFIG_SYS_OR3_8COL 0xFC000A00
483#define CONFIG_SYS_BR3_8COL 0x02000081
484
485#define CONFIG_SYS_OR1_9COL 0xFE000A00
486#define CONFIG_SYS_BR1_9COL 0x00000081
487#define CONFIG_SYS_OR2_9COL 0xFE000A00
488#define CONFIG_SYS_BR2_9COL 0x02000081
489#define CONFIG_SYS_OR3_9COL 0xFE000A00
490#define CONFIG_SYS_BR3_9COL 0x04000081
491
492#define CONFIG_SYS_OR4 0xFFFF8926
493#define CONFIG_SYS_BR4 0x90000401
494
495#define CONFIG_SYS_OR5 0xFFC007F0 /* EPSON: 4 MB 17 WS or externel TA */
496#define CONFIG_SYS_BR5 0x80080801 /* Start at 0x80080000 */
497
498#define LATCH_ADDR 0x90000200
wdenk56f94be2002-11-05 16:35:14 +0000499
wdenk56f94be2002-11-05 16:35:14 +0000500#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
Heiko Schochere604e402010-07-19 23:46:48 +0200501#define CONFIG_AUTOBOOT_STOP_STR "."
502#define CONFIG_SILENT_CONSOLE 1
Wolfgang Denk2d941de2010-09-10 00:16:19 +0200503#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */
Heiko Schochere604e402010-07-19 23:46:48 +0200504#define CONFIG_VERSION_VARIABLE 1
wdenk56f94be2002-11-05 16:35:14 +0000505
Heiko Schocher8011ec62010-07-19 23:47:08 +0200506/* pass open firmware flat tree */
507#define CONFIG_OF_LIBFDT 1
508#define CONFIG_OF_BOARD_SETUP 1
509
wdenk56f94be2002-11-05 16:35:14 +0000510#endif /* __CONFIG_H */