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wdenk5b1d7132002-11-03 00:07:02 +00001/*
2 * (C) Copyright 2002
3 * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
4 *
5 * This file is based on similar values for other boards found in other
6 * U-Boot config files, and some that I found in the EP8260 manual.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * board/config.h - configuration options, board specific
wdenka562e1b2005-01-09 18:21:42 +000029 *
wdenk9dd611b2005-01-09 17:19:34 +000030 * "EP8260 H, V.1.1"
Wolfgang Denk53677ef2008-05-20 16:00:29 +020031 * - 64M 60x Bus SDRAM
32 * - 32M Local Bus SDRAM
33 * - 16M Flash (4 x AM29DL323DB90WDI)
34 * - 128k NVRAM with RTC
wdenk9dd611b2005-01-09 17:19:34 +000035 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036 * "EP8260 H2, V.1.3" (CONFIG_SYS_EP8260_H2)
Wolfgang Denk53677ef2008-05-20 16:00:29 +020037 * - 300MHz/133MHz/66MHz
38 * - 64M 60x Bus SDRAM
39 * - 32M Local Bus SDRAM
40 * - 32M Flash
41 * - 128k NVRAM with RTC
wdenk5b1d7132002-11-03 00:07:02 +000042 */
43
44#ifndef __CONFIG_H
45#define __CONFIG_H
46
wdenk9dd611b2005-01-09 17:19:34 +000047/* Define this to enable support the EP8260 H2 version */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_EP8260_H2 1
49/* #undef CONFIG_SYS_EP8260_H2 */
wdenk9dd611b2005-01-09 17:19:34 +000050
Wolfgang Denk2ae18242010-10-06 09:05:45 +020051#define CONFIG_SYS_TEXT_BASE 0xFFF00000
52
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050053#define CONFIG_CPM2 1 /* Has a CPM2 */
54
wdenk5b1d7132002-11-03 00:07:02 +000055/* What is the oscillator's (UX2) frequency in Hz? */
56#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
57
58/*-----------------------------------------------------------------------
59 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
60 *-----------------------------------------------------------------------
61 * What should MODCK_H be? It is dependent on the oscillator
62 * frequency, MODCK[1-3], and desired CPM and core frequencies.
63 * Here are some example values (all frequencies are in MHz):
64 *
65 * MODCK_H MODCK[1-3] Osc CPM Core
66 * ------- ---------- --- --- ----
67 * 0x2 0x2 33 133 133
68 * 0x2 0x3 33 133 166
69 * 0x2 0x4 33 133 200
70 * 0x2 0x5 33 133 233
71 * 0x2 0x6 33 133 266
72 *
73 * 0x5 0x5 66 133 133
74 * 0x5 0x6 66 133 166
75 * 0x5 0x7 66 133 200 *
76 * 0x6 0x0 66 133 233
77 * 0x6 0x1 66 133 266
78 * 0x6 0x2 66 133 300
79 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#ifdef CONFIG_SYS_EP8260_H2
81#define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110)
wdenk9dd611b2005-01-09 17:19:34 +000082#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110)
wdenk9dd611b2005-01-09 17:19:34 +000084#endif
wdenk5b1d7132002-11-03 00:07:02 +000085
86/* Define this if you want to boot from 0x00000100. If you don't define
87 * this, you will need to program the bootloader to 0xfff00000, and
88 * get the hardware reset config words at 0xfe000000. The simplest
89 * way to do that is to program the bootloader at both addresses.
90 * It is suggested that you just let U-Boot live at 0x00000000.
91 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092/* #define CONFIG_SYS_SBC_BOOT_LOW 1 */ /* only for HRCW */
93/* #undef CONFIG_SYS_SBC_BOOT_LOW */
wdenk5b1d7132002-11-03 00:07:02 +000094
95/* The reset command will not work as expected if the reset address does
96 * not point to the correct address.
97 */
98
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenk5b1d7132002-11-03 00:07:02 +0000100
101/* What should the base address of the main FLASH be and how big is
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200102 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ep8260/config.mk
wdenk5b1d7132002-11-03 00:07:02 +0000103 * The main FLASH is whichever is connected to *CS0. U-Boot expects
104 * this to be the SIMM.
105 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#ifdef CONFIG_SYS_EP8260_H2
107#define CONFIG_SYS_FLASH0_BASE 0xFE000000
108#define CONFIG_SYS_FLASH0_SIZE 32
wdenk9dd611b2005-01-09 17:19:34 +0000109#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_FLASH0_BASE 0xFF000000
111#define CONFIG_SYS_FLASH0_SIZE 16
wdenk9dd611b2005-01-09 17:19:34 +0000112#endif
wdenk5b1d7132002-11-03 00:07:02 +0000113
114/* What should the base address of the secondary FLASH be and how big
115 * is it (in Mbytes)? The secondary FLASH is whichever is connected
116 * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
117 * want it enabled, don't define these constants.
118 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_FLASH1_BASE 0
120#define CONFIG_SYS_FLASH1_SIZE 0
121#undef CONFIG_SYS_FLASH1_BASE
122#undef CONFIG_SYS_FLASH1_SIZE
wdenk5b1d7132002-11-03 00:07:02 +0000123
124/* What should be the base address of SDRAM DIMM (60x bus) and how big is
125 * it (in Mbytes)?
126*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_SDRAM0_BASE 0x00000000
128#define CONFIG_SYS_SDRAM0_SIZE 64
wdenk5b1d7132002-11-03 00:07:02 +0000129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130/* define CONFIG_SYS_LSDRAM if you want to enable the 32M SDRAM on the
wdenk5b1d7132002-11-03 00:07:02 +0000131 * local bus (8260 local bus is NOT cacheable!)
132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133/* #define CONFIG_SYS_LSDRAM */
134#undef CONFIG_SYS_LSDRAM
wdenk5b1d7132002-11-03 00:07:02 +0000135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#ifdef CONFIG_SYS_LSDRAM
wdenk5b1d7132002-11-03 00:07:02 +0000137/* What should be the base address of SDRAM DIMM (local bus) and how big is
138 * it (in Mbytes)?
139*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140 #define CONFIG_SYS_SDRAM1_BASE 0x04000000
141 #define CONFIG_SYS_SDRAM1_SIZE 32
wdenk5b1d7132002-11-03 00:07:02 +0000142#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143 #define CONFIG_SYS_SDRAM1_BASE 0
144 #define CONFIG_SYS_SDRAM1_SIZE 0
145 #undef CONFIG_SYS_SDRAM1_BASE
146 #undef CONFIG_SYS_SDRAM1_SIZE
147#endif /* CONFIG_SYS_LSDRAM */
wdenk5b1d7132002-11-03 00:07:02 +0000148
149/* What should be the base address of NVRAM and how big is
150 * it (in Bytes)
151 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA080000
153#define CONFIG_SYS_NVRAM_SIZE (128*1024)-16
wdenk5b1d7132002-11-03 00:07:02 +0000154
155/* The RTC is a Dallas DS1556
156 */
157#define CONFIG_RTC_DS1556
158
159/* What should be the base address of the LEDs and switch S0?
160 * If you don't want them enabled, don't define this.
161 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_LED_BASE 0x00000000
163#undef CONFIG_SYS_LED_BASE
wdenk5b1d7132002-11-03 00:07:02 +0000164
165/*
166 * select serial console configuration
167 *
168 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
169 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
170 * for SCC).
171 *
172 * if CONFIG_CONS_NONE is defined, then the serial console routines must
173 * defined elsewhere.
174 */
175#define CONFIG_CONS_ON_SMC /* define if console on SMC */
176#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
177#undef CONFIG_CONS_NONE /* define if console on neither */
178#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
179
180/*
181 * select ethernet configuration
182 *
183 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
184 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
185 * for FCC)
186 *
187 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500188 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk5b1d7132002-11-03 00:07:02 +0000189 */
190#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
191#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
192#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
193#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */
194
195#if ( CONFIG_ETHER_INDEX == 3 )
196
197/*
198 * - Rx-CLK is CLK15
199 * - Tx-CLK is CLK16
200 * - RAM for BD/Buffers is on the local Bus (see 28-13)
201 * - Enable Half Duplex in FSMR
202 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000203# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
204# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
wdenk5b1d7132002-11-03 00:07:02 +0000205
206/*
207 * - RAM for BD/Buffers is on the local Bus (see 28-13)
208 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#ifdef CONFIG_SYS_LSDRAM
210 #define CONFIG_SYS_CPMFCR_RAMTYPE 3
211#else /* CONFIG_SYS_LSDRAM */
212 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
213#endif /* CONFIG_SYS_LSDRAM */
wdenk5b1d7132002-11-03 00:07:02 +0000214
215/* - Enable Half Duplex in FSMR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216/* # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */
217# define CONFIG_SYS_FCC_PSMR 0
wdenk5b1d7132002-11-03 00:07:02 +0000218
219#else /* CONFIG_ETHER_INDEX */
220# error "on EP8260 ethernet must be FCC3"
221#endif /* CONFIG_ETHER_INDEX */
222
223/*
224 * select i2c support configuration
225 *
226 * Supported configurations are {none, software, hardware} drivers.
227 * If the software driver is chosen, there are some additional
228 * configuration items that the driver uses to drive the port pins.
229 */
230#undef CONFIG_HARD_I2C /* I2C with hardware support */
231#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
233#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk5b1d7132002-11-03 00:07:02 +0000234
235/*
236 * Software (bit-bang) I2C driver configuration
237 */
238#ifdef CONFIG_SOFT_I2C
239#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
240#define I2C_ACTIVE (iop->pdir |= 0x00010000)
241#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
242#define I2C_READ ((iop->pdat & 0x00010000) != 0)
243#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
244 else iop->pdat &= ~0x00010000
245#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
246 else iop->pdat &= ~0x00020000
247#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
248#endif /* CONFIG_SOFT_I2C */
249
250/* #define CONFIG_RTC_DS174x */
251
252/* Define this to reserve an entire FLASH sector (256 KB) for
253 * environment variables. Otherwise, the environment will be
254 * put in the same sector as U-Boot, and changing variables
255 * will erase U-Boot temporarily
256 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200257#define CONFIG_ENV_IN_OWN_SECT
wdenk5b1d7132002-11-03 00:07:02 +0000258
259/* Define to allow the user to overwrite serial and ethaddr */
260#define CONFIG_ENV_OVERWRITE
261
262/* What should the console's baud rate be? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#ifdef CONFIG_SYS_EP8260_H2
wdenk9dd611b2005-01-09 17:19:34 +0000264#define CONFIG_BAUDRATE 9600
265#else
wdenka562e1b2005-01-09 18:21:42 +0000266#define CONFIG_BAUDRATE 115200
wdenk9dd611b2005-01-09 17:19:34 +0000267#endif
wdenk5b1d7132002-11-03 00:07:02 +0000268
269/* Ethernet MAC address */
270#define CONFIG_ETHADDR 00:10:EC:00:30:8C
271
272#define CONFIG_IPADDR 192.168.254.130
273#define CONFIG_SERVERIP 192.168.254.49
274
275/* Set to a positive value to delay for running BOOTCOMMAND */
276#define CONFIG_BOOTDELAY -1
277
278/* undef this to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_LONGHELP
wdenk5b1d7132002-11-03 00:07:02 +0000280
281/* Monitor Command Prompt */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_PROMPT "=> "
wdenk5b1d7132002-11-03 00:07:02 +0000283
284/* Define this variable to enable the "hush" shell (from
285 Busybox) as command line interpreter, thus enabling
286 powerful command line syntax like
287 if...then...else...fi conditionals or `&&' and '||'
288 constructs ("shell scripts").
289 If undefined, you get the old, much simpler behaviour
290 with a somewhat smapper memory footprint.
291*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_HUSH_PARSER
wdenk5b1d7132002-11-03 00:07:02 +0000293
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500294
wdenk5b1d7132002-11-03 00:07:02 +0000295/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500296 * BOOTP options
297 */
298#define CONFIG_BOOTP_BOOTFILESIZE
299#define CONFIG_BOOTP_BOOTPATH
300#define CONFIG_BOOTP_GATEWAY
301#define CONFIG_BOOTP_HOSTNAME
302
303
304/*
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500305 * Command line configuration.
306 */
Jean-Christophe PLAGNIOL-VILLARD4e620412007-10-24 18:16:01 +0200307#include <config_cmd_default.h>
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500308
Jean-Christophe PLAGNIOL-VILLARD4e620412007-10-24 18:16:01 +0200309#define CONFIG_CMD_ASKENV
310#define CONFIG_CMD_BEDBUG
311#define CONFIG_CMD_CACHE
312#define CONFIG_CMD_CDP
313#define CONFIG_CMD_DATE
314#define CONFIG_CMD_DIAG
315#define CONFIG_CMD_ELF
316#define CONFIG_CMD_FAT
317#define CONFIG_CMD_I2C
318#define CONFIG_CMD_IMMAP
319#define CONFIG_CMD_IRQ
320#define CONFIG_CMD_PING
321#define CONFIG_CMD_PORTIO
322#define CONFIG_CMD_REGINFO
323#define CONFIG_CMD_SAVES
324#define CONFIG_CMD_SDRAM
325#define CONFIG_CMD_SNTP
326
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500327#undef CONFIG_CMD_XIMG
wdenk5b1d7132002-11-03 00:07:02 +0000328
329/* Where do the internal registers live? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_IMMR 0xF0000000
331#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
wdenk5b1d7132002-11-03 00:07:02 +0000332
333/* Where do the on board registers (CS4) live? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_REGS_BASE 0xFA000000
wdenk5b1d7132002-11-03 00:07:02 +0000335
336/*****************************************************************************
337 *
338 * You should not have to modify any of the following settings
339 *
340 *****************************************************************************/
341
342#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
343#define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */
344
wdenkc837dcb2004-01-20 23:12:12 +0000345#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
wdenk5b1d7132002-11-03 00:07:02 +0000346
wdenk5b1d7132002-11-03 00:07:02 +0000347/*
348 * Miscellaneous configurable options
349 */
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500350#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +0000352#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +0000354#endif
355
356/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
wdenk5b1d7132002-11-03 00:07:02 +0000358
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
wdenk5b1d7132002-11-03 00:07:02 +0000360
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +0000362
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#ifdef CONFIG_SYS_LSDRAM
364 #define CONFIG_SYS_MEMTEST_START 0x04000000 /* memtest works on */
365 #define CONFIG_SYS_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */
wdenk5b1d7132002-11-03 00:07:02 +0000366#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
368 #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0-32 MB in SDRAM */
369#endif /* CONFIG_SYS_LSDRAM */
wdenk5b1d7132002-11-03 00:07:02 +0000370
371#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
372
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
wdenk5b1d7132002-11-03 00:07:02 +0000374
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk5b1d7132002-11-03 00:07:02 +0000376
wdenk5b1d7132002-11-03 00:07:02 +0000377/*
378 * Low Level Configuration Settings
379 * (address mappings, register initial values, etc.)
380 * You should know what you are doing if you make changes here.
381 */
382
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
384#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
wdenk5b1d7132002-11-03 00:07:02 +0000385
386/*-----------------------------------------------------------------------
387 * Hard Reset Configuration Words
388 */
389
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#if defined(CONFIG_SYS_SBC_BOOT_LOW)
391# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
wdenk5b1d7132002-11-03 00:07:02 +0000392#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0x00000000)
394#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
wdenk5b1d7132002-11-03 00:07:02 +0000395
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#ifdef CONFIG_SYS_EP8260_H2
397/* get the HRCW ISB field from CONFIG_SYS_DEFAULT_IMMR */
398#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_DEFAULT_IMMR & 0x10000000) >> 10) |\
399 ((CONFIG_SYS_DEFAULT_IMMR & 0x01000000) >> 7) |\
400 ((CONFIG_SYS_DEFAULT_IMMR & 0x00100000) >> 4) )
wdenk5b1d7132002-11-03 00:07:02 +0000401
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM |\
wdenk8bde7f72003-06-27 21:31:46 +0000403 HRCW_L2CPC01 |\
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404 CONFIG_SYS_SBC_HRCW_IMMR |\
wdenk5b1d7132002-11-03 00:07:02 +0000405 HRCW_APPC10 |\
406 HRCW_CS10PC01 |\
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407 CONFIG_SYS_SBC_MODCK_H |\
408 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS)
wdenk9dd611b2005-01-09 17:19:34 +0000409#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_HRCW_MASTER 0x10400245
wdenk9dd611b2005-01-09 17:19:34 +0000411#endif
wdenk5b1d7132002-11-03 00:07:02 +0000412
413/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_HRCW_SLAVE1 0
415#define CONFIG_SYS_HRCW_SLAVE2 0
416#define CONFIG_SYS_HRCW_SLAVE3 0
417#define CONFIG_SYS_HRCW_SLAVE4 0
418#define CONFIG_SYS_HRCW_SLAVE5 0
419#define CONFIG_SYS_HRCW_SLAVE6 0
420#define CONFIG_SYS_HRCW_SLAVE7 0
wdenk5b1d7132002-11-03 00:07:02 +0000421
422/*-----------------------------------------------------------------------
423 * Definitions for initial stack pointer and data area (in DPRAM)
424 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200426#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200427#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk5b1d7132002-11-03 00:07:02 +0000429
430/*-----------------------------------------------------------------------
431 * Start addresses for the final memory configuration
432 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
434 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
wdenk5b1d7132002-11-03 00:07:02 +0000435 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200436#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenk5b1d7132002-11-03 00:07:02 +0000437
438
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
440# define CONFIG_SYS_RAMBOOT
wdenk5b1d7132002-11-03 00:07:02 +0000441#endif
442
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
444#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk5b1d7132002-11-03 00:07:02 +0000445
446/*
447 * For booting Linux, the board info and command line data
448 * have to be in the first 8 MB of memory, since this is
449 * the maximum mapped by the Linux kernel during initialization.
450 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk5b1d7132002-11-03 00:07:02 +0000452
453/*-----------------------------------------------------------------------
454 * FLASH and environment organization
455 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
457#ifdef CONFIG_SYS_EP8260_H2
458#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenk9dd611b2005-01-09 17:19:34 +0000459#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenk9dd611b2005-01-09 17:19:34 +0000461#endif
wdenk5b1d7132002-11-03 00:07:02 +0000462
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#ifdef CONFIG_SYS_EP8260_H2
464#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Timeout for Flash Erase (in ms) */
465#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Wolfgang Denkbd516262005-09-25 16:56:15 +0200466#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
468#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
Wolfgang Denkbd516262005-09-25 16:56:15 +0200469#endif
wdenk5b1d7132002-11-03 00:07:02 +0000470
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200472# define CONFIG_ENV_IS_IN_FLASH 1
wdenk5b1d7132002-11-03 00:07:02 +0000473
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200474# ifdef CONFIG_ENV_IN_OWN_SECT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200476# define CONFIG_ENV_SECT_SIZE 0x40000
wdenk5b1d7132002-11-03 00:07:02 +0000477# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200479# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
480# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
481# endif /* CONFIG_ENV_IN_OWN_SECT */
wdenk5b1d7132002-11-03 00:07:02 +0000482#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200483# define CONFIG_ENV_IS_IN_NVRAM 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200484# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200485# define CONFIG_ENV_SIZE 0x200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200486#endif /* CONFIG_SYS_RAMBOOT */
wdenk5b1d7132002-11-03 00:07:02 +0000487
488/*-----------------------------------------------------------------------
489 * Cache Configuration
490 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
wdenk5b1d7132002-11-03 00:07:02 +0000492
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500493#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200494# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk5b1d7132002-11-03 00:07:02 +0000495#endif
496
497/*-----------------------------------------------------------------------
498 * HIDx - Hardware Implementation-dependent Registers 2-11
499 *-----------------------------------------------------------------------
500 * HID0 also contains cache control - initially enable both caches and
501 * invalidate contents, then the final state leaves only the instruction
502 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
503 * but Soft reset does not.
504 *
505 * HID1 has only read-only information - nothing to set.
506 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200507#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
wdenk5b1d7132002-11-03 00:07:02 +0000508 HID0_DCE |\
509 HID0_ICFI |\
510 HID0_DCI |\
511 HID0_IFEM |\
512 HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200513#ifdef CONFIG_SYS_LSDRAM
wdenk5b1d7132002-11-03 00:07:02 +0000514/* 8260 local bus is NOT cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200515#define CONFIG_SYS_HID0_FINAL (/*HID0_ICE |*/\
wdenk5b1d7132002-11-03 00:07:02 +0000516 HID0_IFEM |\
517 HID0_ABE |\
518 HID0_EMCP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200519#else /* !CONFIG_SYS_LSDRAM */
520#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
wdenk5b1d7132002-11-03 00:07:02 +0000521 HID0_IFEM |\
522 HID0_ABE |\
523 HID0_EMCP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200524#endif /* CONFIG_SYS_LSDRAM */
wdenk5b1d7132002-11-03 00:07:02 +0000525
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200526#define CONFIG_SYS_HID2 0
wdenk5b1d7132002-11-03 00:07:02 +0000527
528/*-----------------------------------------------------------------------
529 * RMR - Reset Mode Register
530 *-----------------------------------------------------------------------
531 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200532#define CONFIG_SYS_RMR 0
wdenk5b1d7132002-11-03 00:07:02 +0000533
534/*-----------------------------------------------------------------------
535 * BCR - Bus Configuration 4-25
536 *-----------------------------------------------------------------------
537 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200538#define CONFIG_SYS_BCR (BCR_EBM |\
wdenk5b1d7132002-11-03 00:07:02 +0000539 BCR_PLDP |\
540 BCR_EAV |\
wdenk9dd611b2005-01-09 17:19:34 +0000541 BCR_NPQM0)
542
wdenk5b1d7132002-11-03 00:07:02 +0000543/*-----------------------------------------------------------------------
544 * SIUMCR - SIU Module Configuration 4-31
545 *-----------------------------------------------------------------------
546 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200547#define CONFIG_SYS_SIUMCR (SIUMCR_L2CPC01 |\
wdenk8bde7f72003-06-27 21:31:46 +0000548 SIUMCR_APPC10 |\
549 SIUMCR_CS10PC01)
wdenk5b1d7132002-11-03 00:07:02 +0000550
wdenk5b1d7132002-11-03 00:07:02 +0000551/*-----------------------------------------------------------------------
552 * SYPCR - System Protection Control 11-9
553 * SYPCR can only be written once after reset!
554 *-----------------------------------------------------------------------
555 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
556 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200557#ifdef CONFIG_SYS_EP8260_H2
wdenka562e1b2005-01-09 18:21:42 +0000558/* TBD: Find out why setting the BMT to 0xff causes the FCC to
559 * generate TX buffer underrun errors for large packets under
560 * Linux
wdenk9dd611b2005-01-09 17:19:34 +0000561 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200562#define CONFIG_SYS_SYPCR_BMT 0x00000600
wdenk9dd611b2005-01-09 17:19:34 +0000563#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200564#define CONFIG_SYS_SYPCR_BMT SYPCR_BMT
wdenk9dd611b2005-01-09 17:19:34 +0000565#endif
566
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200567#ifdef CONFIG_SYS_LSDRAM
568#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
569 CONFIG_SYS_SYPCR_BMT |\
wdenk8bde7f72003-06-27 21:31:46 +0000570 SYPCR_PBME |\
571 SYPCR_LBME |\
572 SYPCR_SWP)
wdenk5b1d7132002-11-03 00:07:02 +0000573#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200574#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
575 CONFIG_SYS_SYPCR_BMT |\
wdenk8bde7f72003-06-27 21:31:46 +0000576 SYPCR_PBME |\
577 SYPCR_SWP)
wdenk5b1d7132002-11-03 00:07:02 +0000578#endif
wdenk9dd611b2005-01-09 17:19:34 +0000579
wdenk5b1d7132002-11-03 00:07:02 +0000580/*-----------------------------------------------------------------------
581 * TMCNTSC - Time Counter Status and Control 4-40
582 *-----------------------------------------------------------------------
583 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
584 * and enable Time Counter
585 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200586#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
wdenk8bde7f72003-06-27 21:31:46 +0000587 TMCNTSC_ALR |\
588 TMCNTSC_TCF |\
589 TMCNTSC_TCE)
wdenk5b1d7132002-11-03 00:07:02 +0000590
591/*-----------------------------------------------------------------------
592 * PISCR - Periodic Interrupt Status and Control 4-42
593 *-----------------------------------------------------------------------
594 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
595 * Periodic timer
596 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200597#ifdef CONFIG_SYS_EP8260_H2
598#define CONFIG_SYS_PISCR (PISCR_PS |\
wdenk8bde7f72003-06-27 21:31:46 +0000599 PISCR_PTF |\
wdenk9dd611b2005-01-09 17:19:34 +0000600 PISCR_PTE)
601#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200602#define CONFIG_SYS_PISCR 0
wdenk9dd611b2005-01-09 17:19:34 +0000603#endif
604
wdenk5b1d7132002-11-03 00:07:02 +0000605/*-----------------------------------------------------------------------
606 * SCCR - System Clock Control 9-8
607 *-----------------------------------------------------------------------
608 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200609#ifdef CONFIG_SYS_EP8260_H2
610#define CONFIG_SYS_SCCR (SCCR_DFBRG00)
Wolfgang Denkbd516262005-09-25 16:56:15 +0200611#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200612#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
Wolfgang Denkbd516262005-09-25 16:56:15 +0200613#endif
wdenk5b1d7132002-11-03 00:07:02 +0000614
615/*-----------------------------------------------------------------------
616 * RCCR - RISC Controller Configuration 13-7
617 *-----------------------------------------------------------------------
618 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200619#define CONFIG_SYS_RCCR 0
wdenk5b1d7132002-11-03 00:07:02 +0000620
621/*-----------------------------------------------------------------------
622 * MPTPR - Memory Refresh Timer Prescale Register 10-32
623 *-----------------------------------------------------------------------
624 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200625#define CONFIG_SYS_MPTPR (0x0A00 & MPTPR_PTP_MSK)
wdenk5b1d7132002-11-03 00:07:02 +0000626
627/*
628 * Init Memory Controller:
629 *
630 * Bank Bus Machine PortSz Device
631 * ---- --- ------- ------ ------
632 * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
633 * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
634 * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
635 * 3 unused
636 * 4 60x GPCM 8 bit Board Regs, NVRTC
637 * 5 unused
638 * 6 unused
639 * 7 unused
640 * 8 PCMCIA
641 * 9 unused
642 * 10 unused
643 * 11 unused
644*/
645
646/*-----------------------------------------------------------------------
647 * BRx - Base Register
648 * Ref: Section 10.3.1 on page 10-14
649 * ORx - Option Register
650 * Ref: Section 10.3.2 on page 10-18
651 *-----------------------------------------------------------------------
652 */
653
654/* Bank 0 - FLASH
655 *
656 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200657#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000658 BRx_PS_64 |\
wdenk5b1d7132002-11-03 00:07:02 +0000659 BRx_DECC_NONE |\
wdenk8bde7f72003-06-27 21:31:46 +0000660 BRx_MS_GPCM_P |\
661 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000662
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200663#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000664 ORxG_CSNT |\
665 ORxG_ACS_DIV1 |\
wdenk9dd611b2005-01-09 17:19:34 +0000666 ORxG_SCY_8_CLK |\
wdenk8bde7f72003-06-27 21:31:46 +0000667 ORxG_EHTR)
wdenk5b1d7132002-11-03 00:07:02 +0000668
669/* Bank 1 - SDRAM
670 * PSDRAM
671 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200672#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000673 BRx_PS_64 |\
674 BRx_MS_SDRAM_P |\
675 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000676
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200677#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000678 ORxS_BPD_4 |\
679 ORxS_ROWST_PBI1_A6 |\
680 ORxS_NUMR_12)
wdenk5b1d7132002-11-03 00:07:02 +0000681
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200682#ifdef CONFIG_SYS_EP8260_H2
683#define CONFIG_SYS_PSDMR 0xC34E246E
wdenk9dd611b2005-01-09 17:19:34 +0000684#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200685#define CONFIG_SYS_PSDMR 0xC34E2462
wdenk9dd611b2005-01-09 17:19:34 +0000686#endif
wdenk5b1d7132002-11-03 00:07:02 +0000687
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200688#define CONFIG_SYS_PSRT 0x64
wdenk5b1d7132002-11-03 00:07:02 +0000689
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200690#ifdef CONFIG_SYS_LSDRAM
wdenk5b1d7132002-11-03 00:07:02 +0000691/* Bank 2 - SDRAM
692 * LSDRAM
693 */
694
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200695 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000696 BRx_PS_32 |\
697 BRx_MS_SDRAM_L |\
698 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000699
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200700 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000701 ORxS_BPD_4 |\
702 ORxS_ROWST_PBI0_A9 |\
703 ORxS_NUMR_12)
wdenk5b1d7132002-11-03 00:07:02 +0000704
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200705 #define CONFIG_SYS_LSDMR 0x416A2562
706 #define CONFIG_SYS_LSRT 0x64
wdenk5b1d7132002-11-03 00:07:02 +0000707#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200708 #define CONFIG_SYS_LSRT 0x0
709#endif /* CONFIG_SYS_LSDRAM */
wdenk5b1d7132002-11-03 00:07:02 +0000710
711/* Bank 4 - On board registers
712 * NVRTC and BCSR
713 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200714#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000715 BRx_PS_8 |\
716 BRx_MS_GPCM_P |\
717 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000718/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200719#define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\
wdenk8bde7f72003-06-27 21:31:46 +0000720 ORxG_CSNT |\
721 ORxG_ACS_DIV1 |\
722 ORxG_SCY_10_CLK |\
723 ORxG_TRLX)
wdenk5b1d7132002-11-03 00:07:02 +0000724*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200725#define CONFIG_SYS_OR4_PRELIM 0xfff00854
wdenk5b1d7132002-11-03 00:07:02 +0000726
wdenk9dd611b2005-01-09 17:19:34 +0000727#ifdef _NOT_USED_SINCE_NOT_WORKING_
wdenk5b1d7132002-11-03 00:07:02 +0000728/* Bank 8 - On board registers
729 * PCMCIA (currently not working!)
730 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200731#define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000732 BRx_PS_16 |\
733 BRx_MS_GPCM_P |\
734 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000735
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200736#define CONFIG_SYS_OR8_PRELIM (ORxG_AM_MSK |\
wdenk8bde7f72003-06-27 21:31:46 +0000737 ORxG_CSNT |\
738 ORxG_ACS_DIV1 |\
wdenk5b1d7132002-11-03 00:07:02 +0000739 ORxG_SETA |\
wdenk8bde7f72003-06-27 21:31:46 +0000740 ORxG_SCY_10_CLK)
wdenk9dd611b2005-01-09 17:19:34 +0000741#endif
wdenk5b1d7132002-11-03 00:07:02 +0000742
743/*
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200744 * JFFS2 partitions
745 *
746 */
747/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100748#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200749#define CONFIG_JFFS2_DEV "nor0"
750#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
751#define CONFIG_JFFS2_PART_OFFSET 0x00000000
752
753/* mtdparts command line support */
754/* Note: fake mtd_id used, no linux mtd map file */
755/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100756#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200757#define MTDIDS_DEFAULT ""
758#define MTDPARTS_DEFAULT ""
759*/
760
wdenk5b1d7132002-11-03 00:07:02 +0000761#endif /* __CONFIG_H */