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Gary Jennejohn73ccb342008-04-28 14:04:32 +02001/*
2 * (C) Copyright 2008
3 * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/************************************************************************
25 * quad100hd.h - configuration for Quad100hd board
26 ***********************************************************************/
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*-----------------------------------------------------------------------
31 * High Level Configuration Options
32 *----------------------------------------------------------------------*/
33#define CONFIG_QUAD100HD 1 /* Board is Quad100hd */
34#define CONFIG_4xx 1 /* ... PPC4xx family */
35#define CONFIG_405EP 1 /* Specifc 405EP support*/
36
Wolfgang Denk2ae18242010-10-06 09:05:45 +020037#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
38
Gary Jennejohn73ccb342008-04-28 14:04:32 +020039#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
40
41#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
42
43#define PLLMR0_DEFAULT PLLMR0_266_133_66 /* no PCI */
44#define PLLMR1_DEFAULT PLLMR1_266_133_66 /* no PCI */
45
Gary Jennejohn0c119352008-05-14 13:39:22 +020046/* the environment is in the EEPROM by default */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +020047#define CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020048#undef CONFIG_ENV_IS_IN_FLASH
Gary Jennejohn73ccb342008-04-28 14:04:32 +020049
Ben Warren96e21f82008-10-27 23:50:15 -070050#define CONFIG_PPC4xx_EMAC
Gary Jennejohn73ccb342008-04-28 14:04:32 +020051#define CONFIG_HAS_ETH1 1
52#define CONFIG_MII 1 /* MII PHY management */
53#define CONFIG_PHY_ADDR 0x01 /* PHY address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
Gary Jennejohn73ccb342008-04-28 14:04:32 +020055#define CONFIG_PHY_RESET 1
56#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
57
58/*
59 * Command line configuration.
60 */
61#include <config_cmd_default.h>
62
63#undef CONFIG_CMD_ASKENV
64#undef CONFIG_CMD_CACHE
65#define CONFIG_CMD_DHCP
66#undef CONFIG_CMD_DIAG
67#define CONFIG_CMD_EEPROM
68#undef CONFIG_CMD_ELF
69#define CONFIG_CMD_I2C
70#undef CONFIG_CMD_IRQ
71#define CONFIG_CMD_JFFS2
Gary Jennejohn73ccb342008-04-28 14:04:32 +020072#undef CONFIG_CMD_MII
73#define CONFIG_CMD_NAND
74#undef CONFIG_CMD_PING
75#define CONFIG_CMD_REGINFO
76
77#undef CONFIG_WATCHDOG /* watchdog disabled */
78
79/*-----------------------------------------------------------------------
80 * SDRAM
81 *----------------------------------------------------------------------*/
82/*
83 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
84 */
85#define CONFIG_SDRAM_BANK0 1
Gary Jennejohn73ccb342008-04-28 14:04:32 +020086
87/* FIX! SDRAM timings used in datasheet */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
89#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
90#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
91#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
92#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
Gary Jennejohn73ccb342008-04-28 14:04:32 +020093
94/*
95 * JFFS2
96 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_JFFS2_FIRST_BANK 0
98#ifdef CONFIG_SYS_KERNEL_IN_JFFS2
99#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0 /* JFFS starts at block 0 */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200100#else /* kernel not in JFFS */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_JFFS2_FIRST_SECTOR 8 /* block 0-7 is kernel (1MB = 8 sectors) */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200102#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_JFFS2_NUM_BANKS 1
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200104
105/*-----------------------------------------------------------------------
106 * Serial Port
107 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +0200108#define CONFIG_CONS_INDEX 1 /* Use UART0 */
109#define CONFIG_SYS_NS16550
110#define CONFIG_SYS_NS16550_SERIAL
111#define CONFIG_SYS_NS16550_REG_SIZE 1
112#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
114#define CONFIG_SYS_BASE_BAUD 691200
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200115#define CONFIG_BAUDRATE 115200
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200116
117/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_BAUDRATE_TABLE \
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200119 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
120
121/*-----------------------------------------------------------------------
122 * Miscellaneous configurable options
123 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_LONGHELP /* undef to save memory */
125#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200126#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200128#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200130#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
132#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
133#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
136#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
139#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200142
143#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200145
146#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
147#define CONFIG_LOOPW 1 /* enable loopw command */
148#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
149#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
150#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
151
152/*-----------------------------------------------------------------------
153 * I2C
154 *----------------------------------------------------------------------*/
155#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
156#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200157#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
159#define CONFIG_SYS_I2C_SLAVE 0x7F
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
162#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 8 byte write page size */
165#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
166#define CONFIG_SYS_EEPROM_SIZE 0x2000
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200167
168/*-----------------------------------------------------------------------
169 * Start addresses for the final memory configuration
170 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_SDRAM_BASE 0x00000000
174#define CONFIG_SYS_FLASH_BASE 0xFFC00000
175#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
176#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200177#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE)
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200178
179/*
180 * For booting Linux, the board info and command line data
181 * have to be in the first 8 MB of memory, since this is
182 * the maximum mapped by the Linux kernel during initialization.
183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200185
186/*-----------------------------------------------------------------------
187 * FLASH organization
188 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200190#define CONFIG_FLASH_CFI_DRIVER
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
195#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
198#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
201#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
204#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200205
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200206#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200207#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Gary Jennejohn0c119352008-05-14 13:39:22 +0200208/* the environment is located before u-boot */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200209#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE)
Gary Jennejohn0c119352008-05-14 13:39:22 +0200210
211/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200212#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
213#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200214#endif
215
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200216#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200217#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars */
218#define CONFIG_ENV_OFFSET 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_ENABLE_CRC_16 1 /* Intrinsyc formatting used crc16 */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200220#endif
221
222/* partly from PPCBoot */
223/* NAND */
224#define CONFIG_NAND
225#ifdef CONFIG_NAND
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_NAND_BASE 0x60000000
227#define CONFIG_SYS_NAND_CS 10 /* our CS is GPIO10 */
228#define CONFIG_SYS_NAND_RDY 23 /* our RDY is GPIO23 */
229#define CONFIG_SYS_NAND_CE 24 /* our CE is GPIO24 */
230#define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */
231#define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wolfgang Denk170c1972009-07-18 15:32:10 +0200233
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200234#endif
235
236/*-----------------------------------------------------------------------
237 * Definitions for initial stack pointer and data area (in data cache)
238 */
239/* use on chip memory (OCM) for temperary stack until sdram is tested */
Stefan Roesea47a12b2010-04-15 16:07:28 +0200240/* see ./arch/powerpc/cpu/ppc4xx/start.S */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_TEMP_STACK_OCM 1
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200242
243/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
245#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
246#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200247#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200248
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200249#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200251
252/*-----------------------------------------------------------------------
253 * External Bus Controller (EBC) Setup
254 * Taken from PPCBoot board/icecube/icecube.h
255 */
256
Stefan Roesea47a12b2010-04-15 16:07:28 +0200257/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_EBC_PB0AP 0x04002480
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200259/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
261#define CONFIG_SYS_EBC_PB1AP 0x04005480
262#define CONFIG_SYS_EBC_PB1CR 0x60018000
263#define CONFIG_SYS_EBC_PB2AP 0x00000000
264#define CONFIG_SYS_EBC_PB2CR 0x00000000
265#define CONFIG_SYS_EBC_PB3AP 0x00000000
266#define CONFIG_SYS_EBC_PB3CR 0x00000000
267#define CONFIG_SYS_EBC_PB4AP 0x00000000
268#define CONFIG_SYS_EBC_PB4CR 0x00000000
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200269
270/*-----------------------------------------------------------------------
271 * Definitions for GPIO setup (PPC405EP specific)
272 *
273 * Taken in part from PPCBoot board/icecube/icecube.h
274 */
Stefan Roesea47a12b2010-04-15 16:07:28 +0200275/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
Stefan Roeseafabb492010-09-12 06:21:37 +0200276#define CONFIG_SYS_GPIO0_OSRL 0x55555550
277#define CONFIG_SYS_GPIO0_OSRH 0x00000110
278#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
279#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_GPIO0_TSRL 0x00000000
Stefan Roeseafabb492010-09-12 06:21:37 +0200281#define CONFIG_SYS_GPIO0_TSRH 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_GPIO0_TCR 0xFFFF8097
283#define CONFIG_SYS_GPIO0_ODR 0x00000000
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200284
285#if defined(CONFIG_CMD_KGDB)
286#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
287#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
288#endif
289
290/* ENVIRONMENT VARS */
291
292#define CONFIG_IPADDR 192.168.1.67
293#define CONFIG_SERVERIP 192.168.1.50
294#define CONFIG_GATEWAYIP 192.168.1.1
295#define CONFIG_NETMASK 255.255.255.0
296#define CONFIG_LOADADDR 300000
297#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
298
299/* pass open firmware flat tree */
300#define CONFIG_OF_LIBFDT 1
301
302#endif /* __CONFIG_H */