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Tom Warrenf01b6312012-12-11 13:34:18 +00001/*
2 * (C) Copyright 2010-2012
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef _TEGRA30_COMMON_H_
25#define _TEGRA30_COMMON_H_
26#include "tegra-common.h"
27
28/*
Stephen Warrenc44bb3a2013-02-26 12:28:28 +000029 * Errata configuration
30 */
31#define CONFIG_ARM_ERRATA_743622
32#define CONFIG_ARM_ERRATA_751472
33
34/*
Tom Warrenf01b6312012-12-11 13:34:18 +000035 * NS16550 Configuration
36 */
37#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
38
39/*
40 * High Level Configuration Options
41 */
42#define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */
43
44/* Environment information, boards can override if required */
45#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
46
47/*
48 * Miscellaneous configurable options
49 */
50#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
51#define CONFIG_STACKBASE 0x82800000 /* 40MB */
52
53/*-----------------------------------------------------------------------
54 * Physical Memory Map
55 */
56#define CONFIG_SYS_TEXT_BASE 0x8010E000
57
58/*
59 * Memory layout for where various images get loaded by boot scripts:
60 *
61 * scriptaddr can be pretty much anywhere that doesn't conflict with something
62 * else. Put it above BOOTMAPSZ to eliminate conflicts.
63 *
64 * kernel_addr_r must be within the first 128M of RAM in order for the
65 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
66 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
67 * should not overlap that area, or the kernel will have to copy itself
68 * somewhere else before decompression. Similarly, the address of any other
69 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
70 * this up to 16M allows for a sizable kernel to be decompressed below the
71 * compressed load address.
72 *
73 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
74 * the compressed kernel to be up to 16M too.
75 *
76 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
77 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
78 */
79#define MEM_LAYOUT_ENV_SETTINGS \
80 "scriptaddr=0x90000000\0" \
81 "kernel_addr_r=0x81000000\0" \
82 "fdt_addr_r=0x82000000\0" \
83 "ramdisk_addr_r=0x82100000\0"
84
85/* Defines for SPL */
86#define CONFIG_SPL_TEXT_BASE 0x80108000
87#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
88#define CONFIG_SPL_STACK 0x800ffffc
89
90#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra30/u-boot-spl.lds"
91
Tom Warrenbb1e7cd2012-12-21 16:09:52 -070092/* Total I2C ports on Tegra30 */
93#define TEGRA_I2C_NUM_CONTROLLERS 5
94
Tom Warrenf01b6312012-12-11 13:34:18 +000095#endif /* _TEGRA30_COMMON_H_ */