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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Albert Aribaudce9c2272010-06-17 19:38:21 +05302/*
Albert ARIBAUD57b4bce2011-04-22 19:41:02 +02003 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
Albert Aribaudce9c2272010-06-17 19:38:21 +05304 *
5 * (C) Copyright 2009
6 * Marvell Semiconductor <www.marvell.com>
7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Albert Aribaudce9c2272010-06-17 19:38:21 +05308 */
9
10#include <common.h>
11#include <miiphy.h>
12#include <asm/arch/orion5x.h>
Wolfgang Denk85e04b72011-12-09 12:14:28 +010013#include "../common/common.h"
Albert ARIBAUD9608e7d2015-01-31 22:55:38 +010014#include <spl.h>
15#include <ns16550.h>
Simon Glassc62db352017-05-31 19:47:48 -060016#include <asm/mach-types.h>
Albert Aribaudce9c2272010-06-17 19:38:21 +053017
18DECLARE_GLOBAL_DATA_PTR;
19
Albert Aribaudce9c2272010-06-17 19:38:21 +053020int board_init(void)
21{
22 /* arch number of board */
23 gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2;
24
25 /* boot parameter start at 256th byte of RAM base */
26 gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
27
28 return 0;
29}
Albert Aribaudab9164d2010-07-12 22:24:30 +020030
31#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
32/* Configure and enable MV88E1116 PHY */
33void reset_phy(void)
34{
Simon Guinotc59c0852012-06-05 13:16:00 +000035 mv_phy_88e1116_init("egiga0", 8);
Albert Aribaudab9164d2010-07-12 22:24:30 +020036}
37#endif /* CONFIG_RESET_PHY_R */
Albert ARIBAUD9608e7d2015-01-31 22:55:38 +010038
39/*
40 * SPL serial setup and NOR boot device selection
41 */
42
43#ifdef CONFIG_SPL_BUILD
44
45void spl_board_init(void)
46{
47 preloader_console_init();
48}
49
50u32 spl_boot_device(void)
51{
52 return BOOT_DEVICE_NOR;
53}
54
55#endif /* CONFIG_SPL_BUILD */