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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 60f04320c0a5a5e3317a83f14b27060a3e044efa / . / arch / arm / dts / k3-j721e-main.dtsi
blob: f6c7e1614521d16f8dd99fd721b7bc46bc3aba18 [file] [log] [blame]
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J721E SoC Family Main Domain peripherals
4 *
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]6 */
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]7#include <dt-bindings/phy/phy.h>
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]8#include <dt-bindings/phy/phy-ti.h>
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]9#include <dt-bindings/mux/mux.h>
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]10
Nishanth Menon4d3803d2023-09-11 09:43:59 -0500[diff] [blame]11#include "k3-serdes.h"
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]12
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]13/ {
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
18 };
19
20 cmn_refclk1: clock-cmnrefclk1 {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <0>;
24 };
25};
26
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]27&cbass_main {
28 msmc_ram: sram@70000000 {
29 compatible = "mmio-sram";
30 reg = <0x0 0x70000000 0x0 0x800000>;
31 #address-cells = <1>;
32 #size-cells = <1>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
34
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
37 };
38 };
39
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]40 scm_conf: scm-conf@100000 {
41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
43 #address-cells = <1>;
44 #size-cells = <1>;
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
46
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]47 serdes_ln_ctrl: mux-controller@4080 {
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]48 compatible = "mmio-mux";
49 reg = <0x00004080 0x50>;
50 #mux-control-cells = <1>;
51 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
52 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
53 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
54 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
55 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
56 /* SERDES4 lane0/1/2/3 select */
57 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
58 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
59 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
60 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
61 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
62 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
63 };
64
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]65 cpsw0_phy_gmii_sel: phy@4044 {
66 compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
67 ti,qsgmii-main-ports = <2>, <2>;
68 reg = <0x4044 0x20>;
69 #phy-cells = <1>;
70 };
71
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]72 usb_serdes_mux: mux-controller@4000 {
73 compatible = "mmio-mux";
74 #mux-control-cells = <1>;
75 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
76 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]77 };
78
79 ehrpwm_tbclk: clock-controller@4140 {
80 compatible = "ti,am654-ehrpwm-tbclk";
81 reg = <0x4140 0x18>;
82 #clock-cells = <1>;
83 };
84 };
85
86 main_ehrpwm0: pwm@3000000 {
87 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
88 #pwm-cells = <3>;
89 reg = <0x00 0x3000000 0x00 0x100>;
90 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
91 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
92 clock-names = "tbclk", "fck";
93 status = "disabled";
94 };
95
96 main_ehrpwm1: pwm@3010000 {
97 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
98 #pwm-cells = <3>;
99 reg = <0x00 0x3010000 0x00 0x100>;
100 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
101 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
102 clock-names = "tbclk", "fck";
103 status = "disabled";
104 };
105
106 main_ehrpwm2: pwm@3020000 {
107 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
108 #pwm-cells = <3>;
109 reg = <0x00 0x3020000 0x00 0x100>;
110 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
111 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
112 clock-names = "tbclk", "fck";
113 status = "disabled";
114 };
115
116 main_ehrpwm3: pwm@3030000 {
117 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
118 #pwm-cells = <3>;
119 reg = <0x00 0x3030000 0x00 0x100>;
120 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
121 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
122 clock-names = "tbclk", "fck";
123 status = "disabled";
124 };
125
126 main_ehrpwm4: pwm@3040000 {
127 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
128 #pwm-cells = <3>;
129 reg = <0x00 0x3040000 0x00 0x100>;
130 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
131 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
132 clock-names = "tbclk", "fck";
133 status = "disabled";
134 };
135
136 main_ehrpwm5: pwm@3050000 {
137 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
138 #pwm-cells = <3>;
139 reg = <0x00 0x3050000 0x00 0x100>;
140 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
141 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
142 clock-names = "tbclk", "fck";
143 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]144 };
145
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]146 gic500: interrupt-controller@1800000 {
147 compatible = "arm,gic-v3";
148 #address-cells = <2>;
149 #size-cells = <2>;
150 ranges;
151 #interrupt-cells = <3>;
152 interrupt-controller;
153 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]154 <0x00 0x01900000 0x00 0x100000>, /* GICR */
155 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
156 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
157 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]158
159 /* vcpumntirq: virtual CPU interface maintenance interrupt */
160 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
161
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]162 gic_its: msi-controller@1820000 {
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]163 compatible = "arm,gic-v3-its";
164 reg = <0x00 0x01820000 0x00 0x10000>;
165 socionext,synquacer-pre-its = <0x1000000 0x400000>;
166 msi-controller;
167 #msi-cells = <1>;
168 };
169 };
170
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]171 main_gpio_intr: interrupt-controller@a00000 {
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]172 compatible = "ti,sci-intr";
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]173 reg = <0x00 0x00a00000 0x00 0x800>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]174 ti,intr-trigger-type = <1>;
175 interrupt-controller;
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]176 interrupt-parent = <&gic500>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]177 #interrupt-cells = <1>;
178 ti,sci = <&dmsc>;
179 ti,sci-dev-id = <131>;
180 ti,interrupt-ranges = <8 392 56>;
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]181 };
182
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]183 main_navss: bus@30000000 {
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]184 compatible = "simple-mfd";
185 #address-cells = <2>;
186 #size-cells = <2>;
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]187 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]188 dma-coherent;
189 dma-ranges;
190
191 ti,sci-dev-id = <199>;
192
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]193 main_navss_intr: interrupt-controller@310e0000 {
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]194 compatible = "ti,sci-intr";
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]195 reg = <0x0 0x310e0000 0x0 0x4000>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]196 ti,intr-trigger-type = <4>;
197 interrupt-controller;
198 interrupt-parent = <&gic500>;
199 #interrupt-cells = <1>;
200 ti,sci = <&dmsc>;
201 ti,sci-dev-id = <213>;
202 ti,interrupt-ranges = <0 64 64>,
203 <64 448 64>,
204 <128 672 64>;
205 };
206
207 main_udmass_inta: interrupt-controller@33d00000 {
208 compatible = "ti,sci-inta";
209 reg = <0x0 0x33d00000 0x0 0x100000>;
210 interrupt-controller;
211 interrupt-parent = <&main_navss_intr>;
212 msi-controller;
213 #interrupt-cells = <0>;
214 ti,sci = <&dmsc>;
215 ti,sci-dev-id = <209>;
216 ti,interrupt-ranges = <0 0 256>;
217 };
218
219 secure_proxy_main: mailbox@32c00000 {
220 compatible = "ti,am654-secure-proxy";
221 #mbox-cells = <1>;
222 reg-names = "target_data", "rt", "scfg";
223 reg = <0x00 0x32c00000 0x00 0x100000>,
224 <0x00 0x32400000 0x00 0x100000>,
225 <0x00 0x32800000 0x00 0x100000>;
226 interrupt-names = "rx_011";
227 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
228 };
229
230 smmu0: iommu@36600000 {
231 compatible = "arm,smmu-v3";
232 reg = <0x0 0x36600000 0x0 0x100000>;
233 interrupt-parent = <&gic500>;
234 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
235 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
236 interrupt-names = "eventq", "gerror";
237 #iommu-cells = <1>;
238 };
239
240 hwspinlock: spinlock@30e00000 {
241 compatible = "ti,am654-hwspinlock";
242 reg = <0x00 0x30e00000 0x00 0x1000>;
243 #hwlock-cells = <1>;
244 };
245
246 mailbox0_cluster0: mailbox@31f80000 {
247 compatible = "ti,am654-mailbox";
248 reg = <0x00 0x31f80000 0x00 0x200>;
249 #mbox-cells = <1>;
250 ti,mbox-num-users = <4>;
251 ti,mbox-num-fifos = <16>;
252 interrupt-parent = <&main_navss_intr>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]253 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]254 };
255
256 mailbox0_cluster1: mailbox@31f81000 {
257 compatible = "ti,am654-mailbox";
258 reg = <0x00 0x31f81000 0x00 0x200>;
259 #mbox-cells = <1>;
260 ti,mbox-num-users = <4>;
261 ti,mbox-num-fifos = <16>;
262 interrupt-parent = <&main_navss_intr>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]263 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]264 };
265
266 mailbox0_cluster2: mailbox@31f82000 {
267 compatible = "ti,am654-mailbox";
268 reg = <0x00 0x31f82000 0x00 0x200>;
269 #mbox-cells = <1>;
270 ti,mbox-num-users = <4>;
271 ti,mbox-num-fifos = <16>;
272 interrupt-parent = <&main_navss_intr>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]273 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]274 };
275
276 mailbox0_cluster3: mailbox@31f83000 {
277 compatible = "ti,am654-mailbox";
278 reg = <0x00 0x31f83000 0x00 0x200>;
279 #mbox-cells = <1>;
280 ti,mbox-num-users = <4>;
281 ti,mbox-num-fifos = <16>;
282 interrupt-parent = <&main_navss_intr>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]283 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]284 };
285
286 mailbox0_cluster4: mailbox@31f84000 {
287 compatible = "ti,am654-mailbox";
288 reg = <0x00 0x31f84000 0x00 0x200>;
289 #mbox-cells = <1>;
290 ti,mbox-num-users = <4>;
291 ti,mbox-num-fifos = <16>;
292 interrupt-parent = <&main_navss_intr>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]293 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]294 };
295
296 mailbox0_cluster5: mailbox@31f85000 {
297 compatible = "ti,am654-mailbox";
298 reg = <0x00 0x31f85000 0x00 0x200>;
299 #mbox-cells = <1>;
300 ti,mbox-num-users = <4>;
301 ti,mbox-num-fifos = <16>;
302 interrupt-parent = <&main_navss_intr>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]303 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]304 };
305
306 mailbox0_cluster6: mailbox@31f86000 {
307 compatible = "ti,am654-mailbox";
308 reg = <0x00 0x31f86000 0x00 0x200>;
309 #mbox-cells = <1>;
310 ti,mbox-num-users = <4>;
311 ti,mbox-num-fifos = <16>;
312 interrupt-parent = <&main_navss_intr>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]313 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]314 };
315
316 mailbox0_cluster7: mailbox@31f87000 {
317 compatible = "ti,am654-mailbox";
318 reg = <0x00 0x31f87000 0x00 0x200>;
319 #mbox-cells = <1>;
320 ti,mbox-num-users = <4>;
321 ti,mbox-num-fifos = <16>;
322 interrupt-parent = <&main_navss_intr>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]323 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]324 };
325
326 mailbox0_cluster8: mailbox@31f88000 {
327 compatible = "ti,am654-mailbox";
328 reg = <0x00 0x31f88000 0x00 0x200>;
329 #mbox-cells = <1>;
330 ti,mbox-num-users = <4>;
331 ti,mbox-num-fifos = <16>;
332 interrupt-parent = <&main_navss_intr>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]333 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]334 };
335
336 mailbox0_cluster9: mailbox@31f89000 {
337 compatible = "ti,am654-mailbox";
338 reg = <0x00 0x31f89000 0x00 0x200>;
339 #mbox-cells = <1>;
340 ti,mbox-num-users = <4>;
341 ti,mbox-num-fifos = <16>;
342 interrupt-parent = <&main_navss_intr>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]343 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]344 };
345
346 mailbox0_cluster10: mailbox@31f8a000 {
347 compatible = "ti,am654-mailbox";
348 reg = <0x00 0x31f8a000 0x00 0x200>;
349 #mbox-cells = <1>;
350 ti,mbox-num-users = <4>;
351 ti,mbox-num-fifos = <16>;
352 interrupt-parent = <&main_navss_intr>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]353 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]354 };
355
356 mailbox0_cluster11: mailbox@31f8b000 {
357 compatible = "ti,am654-mailbox";
358 reg = <0x00 0x31f8b000 0x00 0x200>;
359 #mbox-cells = <1>;
360 ti,mbox-num-users = <4>;
361 ti,mbox-num-fifos = <16>;
362 interrupt-parent = <&main_navss_intr>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]363 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]364 };
365
366 main_ringacc: ringacc@3c000000 {
367 compatible = "ti,am654-navss-ringacc";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]368 reg = <0x0 0x3c000000 0x0 0x400000>,
369 <0x0 0x38000000 0x0 0x400000>,
370 <0x0 0x31120000 0x0 0x100>,
371 <0x0 0x33000000 0x0 0x40000>,
372 <0x0 0x31080000 0x0 0x40000>;
373 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]374 ti,num-rings = <1024>;
375 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
376 ti,sci = <&dmsc>;
377 ti,sci-dev-id = <211>;
378 msi-parent = <&main_udmass_inta>;
379 };
380
381 main_udmap: dma-controller@31150000 {
382 compatible = "ti,j721e-navss-main-udmap";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]383 reg = <0x0 0x31150000 0x0 0x100>,
384 <0x0 0x34000000 0x0 0x100000>,
385 <0x0 0x35000000 0x0 0x100000>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]386 reg-names = "gcfg", "rchanrt", "tchanrt";
387 msi-parent = <&main_udmass_inta>;
388 #dma-cells = <1>;
389
390 ti,sci = <&dmsc>;
391 ti,sci-dev-id = <212>;
392 ti,ringacc = <&main_ringacc>;
393
394 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
395 <0x0f>, /* TX_HCHAN */
396 <0x10>; /* TX_UHCHAN */
397 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
398 <0x0b>, /* RX_HCHAN */
399 <0x0c>; /* RX_UHCHAN */
400 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
401 };
402
403 cpts@310d0000 {
404 compatible = "ti,j721e-cpts";
405 reg = <0x0 0x310d0000 0x0 0x400>;
406 reg-names = "cpts";
407 clocks = <&k3_clks 201 1>;
408 clock-names = "cpts";
409 interrupts-extended = <&main_navss_intr 391>;
410 interrupt-names = "cpts";
411 ti,cpts-periodic-outputs = <6>;
412 ti,cpts-ext-ts-inputs = <8>;
413 };
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]414 };
415
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]416 cpsw0: ethernet@c000000 {
417 compatible = "ti,j721e-cpswxg-nuss";
418 #address-cells = <2>;
419 #size-cells = <2>;
420 reg = <0x0 0xc000000 0x0 0x200000>;
421 reg-names = "cpsw_nuss";
422 ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>;
423 clocks = <&k3_clks 19 89>;
424 clock-names = "fck";
425 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
426
427 dmas = <&main_udmap 0xca00>,
428 <&main_udmap 0xca01>,
429 <&main_udmap 0xca02>,
430 <&main_udmap 0xca03>,
431 <&main_udmap 0xca04>,
432 <&main_udmap 0xca05>,
433 <&main_udmap 0xca06>,
434 <&main_udmap 0xca07>,
435 <&main_udmap 0x4a00>;
436 dma-names = "tx0", "tx1", "tx2", "tx3",
437 "tx4", "tx5", "tx6", "tx7",
438 "rx";
439
440 status = "disabled";
441
442 ethernet-ports {
443 #address-cells = <1>;
444 #size-cells = <0>;
445 cpsw0_port1: port@1 {
446 reg = <1>;
447 ti,mac-only;
448 label = "port1";
449 status = "disabled";
450 };
451
452 cpsw0_port2: port@2 {
453 reg = <2>;
454 ti,mac-only;
455 label = "port2";
456 status = "disabled";
457 };
458
459 cpsw0_port3: port@3 {
460 reg = <3>;
461 ti,mac-only;
462 label = "port3";
463 status = "disabled";
464 };
465
466 cpsw0_port4: port@4 {
467 reg = <4>;
468 ti,mac-only;
469 label = "port4";
470 status = "disabled";
471 };
472
473 cpsw0_port5: port@5 {
474 reg = <5>;
475 ti,mac-only;
476 label = "port5";
477 status = "disabled";
478 };
479
480 cpsw0_port6: port@6 {
481 reg = <6>;
482 ti,mac-only;
483 label = "port6";
484 status = "disabled";
485 };
486
487 cpsw0_port7: port@7 {
488 reg = <7>;
489 ti,mac-only;
490 label = "port7";
491 status = "disabled";
492 };
493
494 cpsw0_port8: port@8 {
495 reg = <8>;
496 ti,mac-only;
497 label = "port8";
498 status = "disabled";
499 };
500 };
501
502 cpsw9g_mdio: mdio@f00 {
503 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
504 reg = <0x0 0xf00 0x0 0x100>;
505 #address-cells = <1>;
506 #size-cells = <0>;
507 clocks = <&k3_clks 19 89>;
508 clock-names = "fck";
509 bus_freq = <1000000>;
510 status = "disabled";
511 };
512
513 cpts@3d000 {
514 compatible = "ti,j721e-cpts";
515 reg = <0x0 0x3d000 0x0 0x400>;
516 clocks = <&k3_clks 19 16>;
517 clock-names = "cpts";
518 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
519 interrupt-names = "cpts";
520 ti,cpts-ext-ts-inputs = <4>;
521 ti,cpts-periodic-outputs = <2>;
522 };
523 };
524
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]525 main_crypto: crypto@4e00000 {
526 compatible = "ti,j721e-sa2ul";
527 reg = <0x0 0x4e00000 0x0 0x1200>;
528 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
529 #address-cells = <2>;
530 #size-cells = <2>;
531 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
532
533 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
534 <&main_udmap 0x4001>;
535 dma-names = "tx", "rx1", "rx2";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]536
537 rng: rng@4e10000 {
538 compatible = "inside-secure,safexcel-eip76";
539 reg = <0x0 0x4e10000 0x0 0x7d>;
540 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]541 };
542 };
543
544 main_pmx0: pinctrl@11c000 {
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]545 compatible = "pinctrl-single";
546 /* Proxy 0 addressing */
547 reg = <0x0 0x11c000 0x0 0x2b4>;
548 #pinctrl-cells = <1>;
549 pinctrl-single,register-width = <32>;
550 pinctrl-single,function-mask = <0xffffffff>;
551 };
552
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]553 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
554 main_timerio_input: pinctrl@104200 {
555 compatible = "pinctrl-single";
556 reg = <0x00 0x104200 0x00 0x50>;
557 #pinctrl-cells = <1>;
558 pinctrl-single,register-width = <32>;
559 pinctrl-single,function-mask = <0x00000007>;
560 };
561
562 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
563 main_timerio_output: pinctrl@104280 {
564 compatible = "pinctrl-single";
565 reg = <0x00 0x104280 0x00 0x20>;
566 #pinctrl-cells = <1>;
567 pinctrl-single,register-width = <32>;
568 pinctrl-single,function-mask = <0x0000001f>;
569 };
570
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]571 serdes_wiz0: wiz@5000000 {
572 compatible = "ti,j721e-wiz-16g";
573 #address-cells = <1>;
574 #size-cells = <1>;
575 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]576 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]577 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
578 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
579 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
580 num-lanes = <2>;
581 #reset-cells = <1>;
582 ranges = <0x5000000 0x0 0x5000000 0x10000>;
583
584 wiz0_pll0_refclk: pll0-refclk {
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]585 clocks = <&k3_clks 292 11>, <&cmn_refclk>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]586 #clock-cells = <0>;
587 assigned-clocks = <&wiz0_pll0_refclk>;
588 assigned-clock-parents = <&k3_clks 292 11>;
589 };
590
591 wiz0_pll1_refclk: pll1-refclk {
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]592 clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]593 #clock-cells = <0>;
594 assigned-clocks = <&wiz0_pll1_refclk>;
595 assigned-clock-parents = <&k3_clks 292 0>;
596 };
597
598 wiz0_refclk_dig: refclk-dig {
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]599 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]600 #clock-cells = <0>;
601 assigned-clocks = <&wiz0_refclk_dig>;
602 assigned-clock-parents = <&k3_clks 292 11>;
603 };
604
605 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
606 clocks = <&wiz0_refclk_dig>;
607 #clock-cells = <0>;
608 };
609
610 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
611 clocks = <&wiz0_pll1_refclk>;
612 #clock-cells = <0>;
613 };
614
615 serdes0: serdes@5000000 {
616 compatible = "ti,sierra-phy-t0";
617 reg-names = "serdes";
618 reg = <0x5000000 0x10000>;
619 #address-cells = <1>;
620 #size-cells = <0>;
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]621 #clock-cells = <1>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]622 resets = <&serdes_wiz0 0>;
623 reset-names = "sierra_reset";
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]624 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>,
625 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
626 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
627 "pll0_refclk", "pll1_refclk";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]628 };
629 };
630
631 serdes_wiz1: wiz@5010000 {
632 compatible = "ti,j721e-wiz-16g";
633 #address-cells = <1>;
634 #size-cells = <1>;
635 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]636 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]637 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
638 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
639 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
640 num-lanes = <2>;
641 #reset-cells = <1>;
642 ranges = <0x5010000 0x0 0x5010000 0x10000>;
643
644 wiz1_pll0_refclk: pll0-refclk {
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]645 clocks = <&k3_clks 293 13>, <&cmn_refclk>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]646 #clock-cells = <0>;
647 assigned-clocks = <&wiz1_pll0_refclk>;
648 assigned-clock-parents = <&k3_clks 293 13>;
649 };
650
651 wiz1_pll1_refclk: pll1-refclk {
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]652 clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]653 #clock-cells = <0>;
654 assigned-clocks = <&wiz1_pll1_refclk>;
655 assigned-clock-parents = <&k3_clks 293 0>;
656 };
657
658 wiz1_refclk_dig: refclk-dig {
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]659 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]660 #clock-cells = <0>;
661 assigned-clocks = <&wiz1_refclk_dig>;
662 assigned-clock-parents = <&k3_clks 293 13>;
663 };
664
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]665 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div {
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]666 clocks = <&wiz1_refclk_dig>;
667 #clock-cells = <0>;
668 };
669
670 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
671 clocks = <&wiz1_pll1_refclk>;
672 #clock-cells = <0>;
673 };
674
675 serdes1: serdes@5010000 {
676 compatible = "ti,sierra-phy-t0";
677 reg-names = "serdes";
678 reg = <0x5010000 0x10000>;
679 #address-cells = <1>;
680 #size-cells = <0>;
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]681 #clock-cells = <1>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]682 resets = <&serdes_wiz1 0>;
683 reset-names = "sierra_reset";
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]684 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>,
685 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
686 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
687 "pll0_refclk", "pll1_refclk";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]688 };
689 };
690
691 serdes_wiz2: wiz@5020000 {
692 compatible = "ti,j721e-wiz-16g";
693 #address-cells = <1>;
694 #size-cells = <1>;
695 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]696 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]697 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
698 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
699 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
700 num-lanes = <2>;
701 #reset-cells = <1>;
702 ranges = <0x5020000 0x0 0x5020000 0x10000>;
703
704 wiz2_pll0_refclk: pll0-refclk {
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]705 clocks = <&k3_clks 294 11>, <&cmn_refclk>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]706 #clock-cells = <0>;
707 assigned-clocks = <&wiz2_pll0_refclk>;
708 assigned-clock-parents = <&k3_clks 294 11>;
709 };
710
711 wiz2_pll1_refclk: pll1-refclk {
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]712 clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]713 #clock-cells = <0>;
714 assigned-clocks = <&wiz2_pll1_refclk>;
715 assigned-clock-parents = <&k3_clks 294 0>;
716 };
717
718 wiz2_refclk_dig: refclk-dig {
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]719 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]720 #clock-cells = <0>;
721 assigned-clocks = <&wiz2_refclk_dig>;
722 assigned-clock-parents = <&k3_clks 294 11>;
723 };
724
725 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
726 clocks = <&wiz2_refclk_dig>;
727 #clock-cells = <0>;
728 };
729
730 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
731 clocks = <&wiz2_pll1_refclk>;
732 #clock-cells = <0>;
733 };
734
735 serdes2: serdes@5020000 {
736 compatible = "ti,sierra-phy-t0";
737 reg-names = "serdes";
738 reg = <0x5020000 0x10000>;
739 #address-cells = <1>;
740 #size-cells = <0>;
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]741 #clock-cells = <1>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]742 resets = <&serdes_wiz2 0>;
743 reset-names = "sierra_reset";
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]744 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>,
745 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
746 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
747 "pll0_refclk", "pll1_refclk";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]748 };
749 };
750
751 serdes_wiz3: wiz@5030000 {
752 compatible = "ti,j721e-wiz-16g";
753 #address-cells = <1>;
754 #size-cells = <1>;
755 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]756 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]757 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
758 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
759 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
760 num-lanes = <2>;
761 #reset-cells = <1>;
762 ranges = <0x5030000 0x0 0x5030000 0x10000>;
763
764 wiz3_pll0_refclk: pll0-refclk {
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]765 clocks = <&k3_clks 295 9>, <&cmn_refclk>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]766 #clock-cells = <0>;
767 assigned-clocks = <&wiz3_pll0_refclk>;
768 assigned-clock-parents = <&k3_clks 295 9>;
769 };
770
771 wiz3_pll1_refclk: pll1-refclk {
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]772 clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]773 #clock-cells = <0>;
774 assigned-clocks = <&wiz3_pll1_refclk>;
775 assigned-clock-parents = <&k3_clks 295 0>;
776 };
777
778 wiz3_refclk_dig: refclk-dig {
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]779 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]780 #clock-cells = <0>;
781 assigned-clocks = <&wiz3_refclk_dig>;
782 assigned-clock-parents = <&k3_clks 295 9>;
783 };
784
785 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
786 clocks = <&wiz3_refclk_dig>;
787 #clock-cells = <0>;
788 };
789
790 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
791 clocks = <&wiz3_pll1_refclk>;
792 #clock-cells = <0>;
793 };
794
795 serdes3: serdes@5030000 {
796 compatible = "ti,sierra-phy-t0";
797 reg-names = "serdes";
798 reg = <0x5030000 0x10000>;
799 #address-cells = <1>;
800 #size-cells = <0>;
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]801 #clock-cells = <1>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]802 resets = <&serdes_wiz3 0>;
803 reset-names = "sierra_reset";
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]804 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>,
805 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
806 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
807 "pll0_refclk", "pll1_refclk";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]808 };
809 };
810
811 pcie0_rc: pcie@2900000 {
812 compatible = "ti,j721e-pcie-host";
813 reg = <0x00 0x02900000 0x00 0x1000>,
814 <0x00 0x02907000 0x00 0x400>,
815 <0x00 0x0d000000 0x00 0x00800000>,
816 <0x00 0x10000000 0x00 0x00001000>;
817 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
818 interrupt-names = "link_state";
819 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
820 device_type = "pci";
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]821 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]822 max-link-speed = <3>;
823 num-lanes = <2>;
824 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
825 clocks = <&k3_clks 239 1>;
826 clock-names = "fck";
827 #address-cells = <3>;
828 #size-cells = <2>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]829 bus-range = <0x0 0xff>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]830 vendor-id = <0x104c>;
831 device-id = <0xb00d>;
832 msi-map = <0x0 &gic_its 0x0 0x10000>;
833 dma-coherent;
834 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
835 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
836 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]837 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]838 };
839
840 pcie1_rc: pcie@2910000 {
841 compatible = "ti,j721e-pcie-host";
842 reg = <0x00 0x02910000 0x00 0x1000>,
843 <0x00 0x02917000 0x00 0x400>,
844 <0x00 0x0d800000 0x00 0x00800000>,
845 <0x00 0x18000000 0x00 0x00001000>;
846 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
847 interrupt-names = "link_state";
848 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
849 device_type = "pci";
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]850 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]851 max-link-speed = <3>;
852 num-lanes = <2>;
853 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
854 clocks = <&k3_clks 240 1>;
855 clock-names = "fck";
856 #address-cells = <3>;
857 #size-cells = <2>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]858 bus-range = <0x0 0xff>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]859 vendor-id = <0x104c>;
860 device-id = <0xb00d>;
861 msi-map = <0x0 &gic_its 0x10000 0x10000>;
862 dma-coherent;
863 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
864 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
865 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]866 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]867 };
868
869 pcie2_rc: pcie@2920000 {
870 compatible = "ti,j721e-pcie-host";
871 reg = <0x00 0x02920000 0x00 0x1000>,
872 <0x00 0x02927000 0x00 0x400>,
873 <0x00 0x0e000000 0x00 0x00800000>,
874 <0x44 0x00000000 0x00 0x00001000>;
875 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
876 interrupt-names = "link_state";
877 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
878 device_type = "pci";
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]879 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]880 max-link-speed = <3>;
881 num-lanes = <2>;
882 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
883 clocks = <&k3_clks 241 1>;
884 clock-names = "fck";
885 #address-cells = <3>;
886 #size-cells = <2>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]887 bus-range = <0x0 0xff>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]888 vendor-id = <0x104c>;
889 device-id = <0xb00d>;
890 msi-map = <0x0 &gic_its 0x20000 0x10000>;
891 dma-coherent;
892 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
893 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
894 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]895 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]896 };
897
898 pcie3_rc: pcie@2930000 {
899 compatible = "ti,j721e-pcie-host";
900 reg = <0x00 0x02930000 0x00 0x1000>,
901 <0x00 0x02937000 0x00 0x400>,
902 <0x00 0x0e800000 0x00 0x00800000>,
903 <0x44 0x10000000 0x00 0x00001000>;
904 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
905 interrupt-names = "link_state";
906 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
907 device_type = "pci";
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]908 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]909 max-link-speed = <3>;
910 num-lanes = <2>;
911 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
912 clocks = <&k3_clks 242 1>;
913 clock-names = "fck";
914 #address-cells = <3>;
915 #size-cells = <2>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]916 bus-range = <0x0 0xff>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]917 vendor-id = <0x104c>;
918 device-id = <0xb00d>;
919 msi-map = <0x0 &gic_its 0x30000 0x10000>;
920 dma-coherent;
921 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
922 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
923 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]924 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]925 };
926
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]927 serdes_wiz4: wiz@5050000 {
928 compatible = "ti,am64-wiz-10g";
929 #address-cells = <1>;
930 #size-cells = <1>;
931 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
932 clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
933 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
934 assigned-clocks = <&k3_clks 297 9>;
935 assigned-clock-parents = <&k3_clks 297 10>;
936 assigned-clock-rates = <19200000>;
937 num-lanes = <4>;
938 #reset-cells = <1>;
939 #clock-cells = <1>;
940 ranges = <0x05050000 0x00 0x05050000 0x010000>,
941 <0x0a030a00 0x00 0x0a030a00 0x40>;
942
943 serdes4: serdes@5050000 {
944 /*
945 * Note: we also map DPTX PHY registers as the Torrent
946 * needs to manage those.
947 */
948 compatible = "ti,j721e-serdes-10g";
949 reg = <0x05050000 0x010000>,
950 <0x0a030a00 0x40>; /* DPTX PHY */
951 reg-names = "torrent_phy", "dptx_phy";
952
953 resets = <&serdes_wiz4 0>;
954 reset-names = "torrent_reset";
955 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>;
956 clock-names = "refclk";
957 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
958 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
959 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
960 assigned-clock-parents = <&k3_clks 297 9>,
961 <&k3_clks 297 9>,
962 <&k3_clks 297 9>;
963 #address-cells = <1>;
964 #size-cells = <0>;
965 };
966 };
967
968 main_timer0: timer@2400000 {
969 compatible = "ti,am654-timer";
970 reg = <0x00 0x2400000 0x00 0x400>;
971 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
972 clocks = <&k3_clks 49 1>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]973 clock-names = "fck";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]974 assigned-clocks = <&k3_clks 49 1>;
975 assigned-clock-parents = <&k3_clks 49 2>;
976 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
977 ti,timer-pwm;
978 };
979
980 main_timer1: timer@2410000 {
981 compatible = "ti,am654-timer";
982 reg = <0x00 0x2410000 0x00 0x400>;
983 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&k3_clks 50 1>;
985 clock-names = "fck";
986 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
987 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>;
988 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
989 ti,timer-pwm;
990 };
991
992 main_timer2: timer@2420000 {
993 compatible = "ti,am654-timer";
994 reg = <0x00 0x2420000 0x00 0x400>;
995 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&k3_clks 51 1>;
997 clock-names = "fck";
998 assigned-clocks = <&k3_clks 51 1>;
999 assigned-clock-parents = <&k3_clks 51 2>;
1000 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
1001 ti,timer-pwm;
1002 };
1003
1004 main_timer3: timer@2430000 {
1005 compatible = "ti,am654-timer";
1006 reg = <0x00 0x2430000 0x00 0x400>;
1007 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1008 clocks = <&k3_clks 52 1>;
1009 clock-names = "fck";
1010 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
1011 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>;
1012 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1013 ti,timer-pwm;
1014 };
1015
1016 main_timer4: timer@2440000 {
1017 compatible = "ti,am654-timer";
1018 reg = <0x00 0x2440000 0x00 0x400>;
1019 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1020 clocks = <&k3_clks 53 1>;
1021 clock-names = "fck";
1022 assigned-clocks = <&k3_clks 53 1>;
1023 assigned-clock-parents = <&k3_clks 53 2>;
1024 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1025 ti,timer-pwm;
1026 };
1027
1028 main_timer5: timer@2450000 {
1029 compatible = "ti,am654-timer";
1030 reg = <0x00 0x2450000 0x00 0x400>;
1031 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&k3_clks 54 1>;
1033 clock-names = "fck";
1034 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
1035 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>;
1036 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1037 ti,timer-pwm;
1038 };
1039
1040 main_timer6: timer@2460000 {
1041 compatible = "ti,am654-timer";
1042 reg = <0x00 0x2460000 0x00 0x400>;
1043 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
1044 clocks = <&k3_clks 55 1>;
1045 clock-names = "fck";
1046 assigned-clocks = <&k3_clks 55 1>;
1047 assigned-clock-parents = <&k3_clks 55 2>;
1048 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1049 ti,timer-pwm;
1050 };
1051
1052 main_timer7: timer@2470000 {
1053 compatible = "ti,am654-timer";
1054 reg = <0x00 0x2470000 0x00 0x400>;
1055 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1056 clocks = <&k3_clks 57 1>;
1057 clock-names = "fck";
1058 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
1059 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>;
1060 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1061 ti,timer-pwm;
1062 };
1063
1064 main_timer8: timer@2480000 {
1065 compatible = "ti,am654-timer";
1066 reg = <0x00 0x2480000 0x00 0x400>;
1067 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
1068 clocks = <&k3_clks 58 1>;
1069 clock-names = "fck";
1070 assigned-clocks = <&k3_clks 58 1>;
1071 assigned-clock-parents = <&k3_clks 58 2>;
1072 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1073 ti,timer-pwm;
1074 };
1075
1076 main_timer9: timer@2490000 {
1077 compatible = "ti,am654-timer";
1078 reg = <0x00 0x2490000 0x00 0x400>;
1079 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
1080 clocks = <&k3_clks 59 1>;
1081 clock-names = "fck";
1082 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
1083 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>;
1084 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1085 ti,timer-pwm;
1086 };
1087
1088 main_timer10: timer@24a0000 {
1089 compatible = "ti,am654-timer";
1090 reg = <0x00 0x24a0000 0x00 0x400>;
1091 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
1092 clocks = <&k3_clks 60 1>;
1093 clock-names = "fck";
1094 assigned-clocks = <&k3_clks 60 1>;
1095 assigned-clock-parents = <&k3_clks 60 2>;
1096 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1097 ti,timer-pwm;
1098 };
1099
1100 main_timer11: timer@24b0000 {
1101 compatible = "ti,am654-timer";
1102 reg = <0x00 0x24b0000 0x00 0x400>;
1103 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
1104 clocks = <&k3_clks 62 1>;
1105 clock-names = "fck";
1106 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
1107 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>;
1108 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1109 ti,timer-pwm;
1110 };
1111
1112 main_timer12: timer@24c0000 {
1113 compatible = "ti,am654-timer";
1114 reg = <0x00 0x24c0000 0x00 0x400>;
1115 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
1116 clocks = <&k3_clks 63 1>;
1117 clock-names = "fck";
1118 assigned-clocks = <&k3_clks 63 1>;
1119 assigned-clock-parents = <&k3_clks 63 2>;
1120 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1121 ti,timer-pwm;
1122 };
1123
1124 main_timer13: timer@24d0000 {
1125 compatible = "ti,am654-timer";
1126 reg = <0x00 0x24d0000 0x00 0x400>;
1127 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
1128 clocks = <&k3_clks 64 1>;
1129 clock-names = "fck";
1130 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
1131 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>;
1132 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1133 ti,timer-pwm;
1134 };
1135
1136 main_timer14: timer@24e0000 {
1137 compatible = "ti,am654-timer";
1138 reg = <0x00 0x24e0000 0x00 0x400>;
1139 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&k3_clks 65 1>;
1141 clock-names = "fck";
1142 assigned-clocks = <&k3_clks 65 1>;
1143 assigned-clock-parents = <&k3_clks 65 2>;
1144 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1145 ti,timer-pwm;
1146 };
1147
1148 main_timer15: timer@24f0000 {
1149 compatible = "ti,am654-timer";
1150 reg = <0x00 0x24f0000 0x00 0x400>;
1151 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1152 clocks = <&k3_clks 66 1>;
1153 clock-names = "fck";
1154 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
1155 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>;
1156 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1157 ti,timer-pwm;
1158 };
1159
1160 main_timer16: timer@2500000 {
1161 compatible = "ti,am654-timer";
1162 reg = <0x00 0x2500000 0x00 0x400>;
1163 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1164 clocks = <&k3_clks 67 1>;
1165 clock-names = "fck";
1166 assigned-clocks = <&k3_clks 67 1>;
1167 assigned-clock-parents = <&k3_clks 67 2>;
1168 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1169 ti,timer-pwm;
1170 };
1171
1172 main_timer17: timer@2510000 {
1173 compatible = "ti,am654-timer";
1174 reg = <0x00 0x2510000 0x00 0x400>;
1175 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1176 clocks = <&k3_clks 68 1>;
1177 clock-names = "fck";
1178 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
1179 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>;
1180 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1181 ti,timer-pwm;
1182 };
1183
1184 main_timer18: timer@2520000 {
1185 compatible = "ti,am654-timer";
1186 reg = <0x00 0x2520000 0x00 0x400>;
1187 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1188 clocks = <&k3_clks 69 1>;
1189 clock-names = "fck";
1190 assigned-clocks = <&k3_clks 69 1>;
1191 assigned-clock-parents = <&k3_clks 69 2>;
1192 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1193 ti,timer-pwm;
1194 };
1195
1196 main_timer19: timer@2530000 {
1197 compatible = "ti,am654-timer";
1198 reg = <0x00 0x2530000 0x00 0x400>;
1199 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1200 clocks = <&k3_clks 70 1>;
1201 clock-names = "fck";
1202 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
1203 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>;
1204 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1205 ti,timer-pwm;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1206 };
1207
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1208 main_uart0: serial@2800000 {
1209 compatible = "ti,j721e-uart", "ti,am654-uart";
1210 reg = <0x00 0x02800000 0x00 0x100>;
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1211 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
1212 clock-frequency = <48000000>;
1213 current-speed = <115200>;
1214 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
1215 clocks = <&k3_clks 146 0>;
1216 clock-names = "fclk";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1217 status = "disabled";
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1218 };
1219
1220 main_uart1: serial@2810000 {
1221 compatible = "ti,j721e-uart", "ti,am654-uart";
1222 reg = <0x00 0x02810000 0x00 0x100>;
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1223 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
1224 clock-frequency = <48000000>;
1225 current-speed = <115200>;
1226 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
1227 clocks = <&k3_clks 278 0>;
1228 clock-names = "fclk";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1229 status = "disabled";
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1230 };
1231
1232 main_uart2: serial@2820000 {
1233 compatible = "ti,j721e-uart", "ti,am654-uart";
1234 reg = <0x00 0x02820000 0x00 0x100>;
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1235 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
1236 clock-frequency = <48000000>;
1237 current-speed = <115200>;
1238 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
1239 clocks = <&k3_clks 279 0>;
1240 clock-names = "fclk";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1241 status = "disabled";
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1242 };
1243
1244 main_uart3: serial@2830000 {
1245 compatible = "ti,j721e-uart", "ti,am654-uart";
1246 reg = <0x00 0x02830000 0x00 0x100>;
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1247 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
1248 clock-frequency = <48000000>;
1249 current-speed = <115200>;
1250 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
1251 clocks = <&k3_clks 280 0>;
1252 clock-names = "fclk";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1253 status = "disabled";
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1254 };
1255
1256 main_uart4: serial@2840000 {
1257 compatible = "ti,j721e-uart", "ti,am654-uart";
1258 reg = <0x00 0x02840000 0x00 0x100>;
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1259 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
1260 clock-frequency = <48000000>;
1261 current-speed = <115200>;
1262 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
1263 clocks = <&k3_clks 281 0>;
1264 clock-names = "fclk";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1265 status = "disabled";
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1266 };
1267
1268 main_uart5: serial@2850000 {
1269 compatible = "ti,j721e-uart", "ti,am654-uart";
1270 reg = <0x00 0x02850000 0x00 0x100>;
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1271 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1272 clock-frequency = <48000000>;
1273 current-speed = <115200>;
1274 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
1275 clocks = <&k3_clks 282 0>;
1276 clock-names = "fclk";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1277 status = "disabled";
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1278 };
1279
1280 main_uart6: serial@2860000 {
1281 compatible = "ti,j721e-uart", "ti,am654-uart";
1282 reg = <0x00 0x02860000 0x00 0x100>;
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1283 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
1284 clock-frequency = <48000000>;
1285 current-speed = <115200>;
1286 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
1287 clocks = <&k3_clks 283 0>;
1288 clock-names = "fclk";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1289 status = "disabled";
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1290 };
1291
1292 main_uart7: serial@2870000 {
1293 compatible = "ti,j721e-uart", "ti,am654-uart";
1294 reg = <0x00 0x02870000 0x00 0x100>;
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1295 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1296 clock-frequency = <48000000>;
1297 current-speed = <115200>;
1298 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
1299 clocks = <&k3_clks 284 0>;
1300 clock-names = "fclk";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1301 status = "disabled";
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1302 };
1303
1304 main_uart8: serial@2880000 {
1305 compatible = "ti,j721e-uart", "ti,am654-uart";
1306 reg = <0x00 0x02880000 0x00 0x100>;
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1307 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
1308 clock-frequency = <48000000>;
1309 current-speed = <115200>;
1310 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
1311 clocks = <&k3_clks 285 0>;
1312 clock-names = "fclk";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1313 status = "disabled";
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1314 };
1315
1316 main_uart9: serial@2890000 {
1317 compatible = "ti,j721e-uart", "ti,am654-uart";
1318 reg = <0x00 0x02890000 0x00 0x100>;
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1319 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
1320 clock-frequency = <48000000>;
1321 current-speed = <115200>;
1322 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
1323 clocks = <&k3_clks 286 0>;
1324 clock-names = "fclk";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1325 status = "disabled";
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1326 };
1327
Faiz Abbas16217ed2020-01-28 15:40:04 +0530[diff] [blame]1328 main_gpio0: gpio@600000 {
1329 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1330 reg = <0x0 0x00600000 0x0 0x100>;
1331 gpio-controller;
1332 #gpio-cells = <2>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1333 interrupt-parent = <&main_gpio_intr>;
1334 interrupts = <256>, <257>, <258>, <259>,
1335 <260>, <261>, <262>, <263>;
Faiz Abbas16217ed2020-01-28 15:40:04 +0530[diff] [blame]1336 interrupt-controller;
1337 #interrupt-cells = <2>;
1338 ti,ngpio = <128>;
1339 ti,davinci-gpio-unbanked = <0>;
1340 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
1341 clocks = <&k3_clks 105 0>;
1342 clock-names = "gpio";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1343 status = "disabled";
Faiz Abbas16217ed2020-01-28 15:40:04 +0530[diff] [blame]1344 };
1345
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1346 main_gpio1: gpio@601000 {
1347 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1348 reg = <0x0 0x00601000 0x0 0x100>;
1349 gpio-controller;
1350 #gpio-cells = <2>;
1351 interrupt-parent = <&main_gpio_intr>;
1352 interrupts = <288>, <289>, <290>;
1353 interrupt-controller;
1354 #interrupt-cells = <2>;
1355 ti,ngpio = <36>;
1356 ti,davinci-gpio-unbanked = <0>;
1357 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
1358 clocks = <&k3_clks 106 0>;
1359 clock-names = "gpio";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1360 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1361 };
1362
1363 main_gpio2: gpio@610000 {
1364 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1365 reg = <0x0 0x00610000 0x0 0x100>;
1366 gpio-controller;
1367 #gpio-cells = <2>;
1368 interrupt-parent = <&main_gpio_intr>;
1369 interrupts = <264>, <265>, <266>, <267>,
1370 <268>, <269>, <270>, <271>;
1371 interrupt-controller;
1372 #interrupt-cells = <2>;
1373 ti,ngpio = <128>;
1374 ti,davinci-gpio-unbanked = <0>;
1375 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
1376 clocks = <&k3_clks 107 0>;
1377 clock-names = "gpio";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1378 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1379 };
1380
1381 main_gpio3: gpio@611000 {
1382 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1383 reg = <0x0 0x00611000 0x0 0x100>;
1384 gpio-controller;
1385 #gpio-cells = <2>;
1386 interrupt-parent = <&main_gpio_intr>;
1387 interrupts = <292>, <293>, <294>;
1388 interrupt-controller;
1389 #interrupt-cells = <2>;
1390 ti,ngpio = <36>;
1391 ti,davinci-gpio-unbanked = <0>;
1392 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
1393 clocks = <&k3_clks 108 0>;
1394 clock-names = "gpio";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1395 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1396 };
1397
1398 main_gpio4: gpio@620000 {
1399 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1400 reg = <0x0 0x00620000 0x0 0x100>;
1401 gpio-controller;
1402 #gpio-cells = <2>;
1403 interrupt-parent = <&main_gpio_intr>;
1404 interrupts = <272>, <273>, <274>, <275>,
1405 <276>, <277>, <278>, <279>;
1406 interrupt-controller;
1407 #interrupt-cells = <2>;
1408 ti,ngpio = <128>;
1409 ti,davinci-gpio-unbanked = <0>;
1410 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
1411 clocks = <&k3_clks 109 0>;
1412 clock-names = "gpio";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1413 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1414 };
1415
1416 main_gpio5: gpio@621000 {
1417 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1418 reg = <0x0 0x00621000 0x0 0x100>;
1419 gpio-controller;
1420 #gpio-cells = <2>;
1421 interrupt-parent = <&main_gpio_intr>;
1422 interrupts = <296>, <297>, <298>;
1423 interrupt-controller;
1424 #interrupt-cells = <2>;
1425 ti,ngpio = <36>;
1426 ti,davinci-gpio-unbanked = <0>;
1427 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
1428 clocks = <&k3_clks 110 0>;
1429 clock-names = "gpio";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1430 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1431 };
1432
1433 main_gpio6: gpio@630000 {
1434 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1435 reg = <0x0 0x00630000 0x0 0x100>;
1436 gpio-controller;
1437 #gpio-cells = <2>;
1438 interrupt-parent = <&main_gpio_intr>;
1439 interrupts = <280>, <281>, <282>, <283>,
1440 <284>, <285>, <286>, <287>;
1441 interrupt-controller;
1442 #interrupt-cells = <2>;
1443 ti,ngpio = <128>;
1444 ti,davinci-gpio-unbanked = <0>;
1445 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
1446 clocks = <&k3_clks 111 0>;
1447 clock-names = "gpio";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1448 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1449 };
1450
1451 main_gpio7: gpio@631000 {
1452 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1453 reg = <0x0 0x00631000 0x0 0x100>;
1454 gpio-controller;
1455 #gpio-cells = <2>;
1456 interrupt-parent = <&main_gpio_intr>;
1457 interrupts = <300>, <301>, <302>;
1458 interrupt-controller;
1459 #interrupt-cells = <2>;
1460 ti,ngpio = <36>;
1461 ti,davinci-gpio-unbanked = <0>;
1462 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
1463 clocks = <&k3_clks 112 0>;
1464 clock-names = "gpio";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1465 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1466 };
1467
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]1468 main_sdhci0: mmc@4f80000 {
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1469 compatible = "ti,j721e-sdhci-8bit";
1470 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1471 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1472 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]1473 clock-names = "clk_ahb", "clk_xin";
1474 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1475 assigned-clocks = <&k3_clks 91 1>;
1476 assigned-clock-parents = <&k3_clks 91 2>;
1477 bus-width = <8>;
Aswath Govindrajue64665f2021-04-12 21:10:55 +0530[diff] [blame]1478 mmc-hs200-1_8v;
Faiz Abbasc7d106b2020-02-26 13:44:33 +0530[diff] [blame]1479 mmc-ddr-1_8v;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1480 ti,otap-del-sel-legacy = <0x0>;
1481 ti,otap-del-sel-mmc-hs = <0x0>;
Faiz Abbasc7d106b2020-02-26 13:44:33 +0530[diff] [blame]1482 ti,otap-del-sel-ddr52 = <0x5>;
1483 ti,otap-del-sel-hs200 = <0x6>;
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]1484 ti,otap-del-sel-hs400 = <0x0>;
Faiz Abbas52de3c32021-02-04 15:10:57 +0530[diff] [blame]1485 ti,itap-del-sel-legacy = <0x10>;
1486 ti,itap-del-sel-mmc-hs = <0xa>;
1487 ti,itap-del-sel-ddr52 = <0x3>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1488 ti,trm-icp = <0x8>;
1489 dma-coherent;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1490 status = "disabled";
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1491 };
1492
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]1493 main_sdhci1: mmc@4fb0000 {
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1494 compatible = "ti,j721e-sdhci-4bit";
1495 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1496 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1497 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]1498 clock-names = "clk_ahb", "clk_xin";
1499 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1500 assigned-clocks = <&k3_clks 92 0>;
1501 assigned-clock-parents = <&k3_clks 92 1>;
Faiz Abbasc7d106b2020-02-26 13:44:33 +0530[diff] [blame]1502 ti,otap-del-sel-legacy = <0x0>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1503 ti,otap-del-sel-sd-hs = <0x0>;
Faiz Abbasc7d106b2020-02-26 13:44:33 +0530[diff] [blame]1504 ti,otap-del-sel-sdr12 = <0xf>;
1505 ti,otap-del-sel-sdr25 = <0xf>;
1506 ti,otap-del-sel-sdr50 = <0xc>;
Faiz Abbasc7d106b2020-02-26 13:44:33 +0530[diff] [blame]1507 ti,otap-del-sel-ddr50 = <0xc>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1508 ti,otap-del-sel-sdr104 = <0x5>;
Aswath Govindrajue64665f2021-04-12 21:10:55 +0530[diff] [blame]1509 ti,itap-del-sel-legacy = <0x0>;
1510 ti,itap-del-sel-sd-hs = <0x0>;
1511 ti,itap-del-sel-sdr12 = <0x0>;
1512 ti,itap-del-sel-sdr25 = <0x0>;
1513 ti,itap-del-sel-ddr50 = <0x2>;
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1514 ti,trm-icp = <0x8>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1515 ti,clkbuf-sel = <0x7>;
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1516 dma-coherent;
Aswath Govindrajue64665f2021-04-12 21:10:55 +0530[diff] [blame]1517 sdhci-caps-mask = <0x2 0x0>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1518 status = "disabled";
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1519 };
Lokesh Vutla55f8eb32019-09-04 16:01:38 +0530[diff] [blame]1520
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]1521 main_sdhci2: mmc@4f98000 {
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1522 compatible = "ti,j721e-sdhci-4bit";
1523 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1524 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1525 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]1526 clock-names = "clk_ahb", "clk_xin";
1527 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1528 assigned-clocks = <&k3_clks 93 0>;
1529 assigned-clock-parents = <&k3_clks 93 1>;
1530 ti,otap-del-sel-legacy = <0x0>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1531 ti,otap-del-sel-sd-hs = <0x0>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1532 ti,otap-del-sel-sdr12 = <0xf>;
1533 ti,otap-del-sel-sdr25 = <0xf>;
1534 ti,otap-del-sel-sdr50 = <0xc>;
1535 ti,otap-del-sel-ddr50 = <0xc>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1536 ti,otap-del-sel-sdr104 = <0x5>;
Aswath Govindrajue64665f2021-04-12 21:10:55 +0530[diff] [blame]1537 ti,itap-del-sel-legacy = <0x0>;
1538 ti,itap-del-sel-sd-hs = <0x0>;
1539 ti,itap-del-sel-sdr12 = <0x0>;
1540 ti,itap-del-sel-sdr25 = <0x0>;
1541 ti,itap-del-sel-ddr50 = <0x2>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1542 ti,trm-icp = <0x8>;
1543 ti,clkbuf-sel = <0x7>;
1544 dma-coherent;
Aswath Govindrajue64665f2021-04-12 21:10:55 +0530[diff] [blame]1545 sdhci-caps-mask = <0x2 0x0>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1546 status = "disabled";
Lokesh Vutla55f8eb32019-09-04 16:01:38 +0530[diff] [blame]1547 };
1548
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1549 usbss0: cdns-usb@4104000 {
Vignesh Raghavendra5aeab3b2019-11-18 19:16:35 +0530[diff] [blame]1550 compatible = "ti,j721e-usb";
1551 reg = <0x00 0x4104000 0x00 0x100>;
1552 dma-coherent;
1553 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1554 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1555 clock-names = "ref", "lpm";
Vignesh Raghavendra5aeab3b2019-11-18 19:16:35 +0530[diff] [blame]1556 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
1557 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
1558 #address-cells = <2>;
1559 #size-cells = <2>;
1560 ranges;
1561
Vignesh Raghavendra5aeab3b2019-11-18 19:16:35 +0530[diff] [blame]1562 usb0: usb@6000000 {
1563 compatible = "cdns,usb3";
1564 reg = <0x00 0x6000000 0x00 0x10000>,
1565 <0x00 0x6010000 0x00 0x10000>,
1566 <0x00 0x6020000 0x00 0x10000>;
1567 reg-names = "otg", "xhci", "dev";
1568 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1569 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
1570 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1571 interrupt-names = "host",
1572 "peripheral",
1573 "otg";
1574 maximum-speed = "super-speed";
1575 dr_mode = "otg";
1576 };
1577 };
1578
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1579 usbss1: cdns-usb@4114000 {
Vignesh Raghavendra5aeab3b2019-11-18 19:16:35 +0530[diff] [blame]1580 compatible = "ti,j721e-usb";
1581 reg = <0x00 0x4114000 0x00 0x100>;
1582 dma-coherent;
1583 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1584 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1585 clock-names = "ref", "lpm";
Vignesh Raghavendra5aeab3b2019-11-18 19:16:35 +0530[diff] [blame]1586 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
1587 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
1588 #address-cells = <2>;
1589 #size-cells = <2>;
1590 ranges;
1591
Vignesh Raghavendra5aeab3b2019-11-18 19:16:35 +0530[diff] [blame]1592 usb1: usb@6400000 {
1593 compatible = "cdns,usb3";
1594 reg = <0x00 0x6400000 0x00 0x10000>,
1595 <0x00 0x6410000 0x00 0x10000>,
1596 <0x00 0x6420000 0x00 0x10000>;
1597 reg-names = "otg", "xhci", "dev";
1598 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1599 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
1600 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1601 interrupt-names = "host",
1602 "peripheral",
1603 "otg";
1604 maximum-speed = "super-speed";
1605 dr_mode = "otg";
1606 };
1607 };
1608
Vignesh Raghavendra01ec6a52020-01-27 23:22:13 +0530[diff] [blame]1609 main_i2c0: i2c@2000000 {
1610 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1611 reg = <0x0 0x2000000 0x0 0x100>;
1612 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
1613 #address-cells = <1>;
1614 #size-cells = <0>;
1615 clock-names = "fck";
1616 clocks = <&k3_clks 187 0>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1617 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1618 status = "disabled";
Vignesh Raghavendra01ec6a52020-01-27 23:22:13 +0530[diff] [blame]1619 };
1620
1621 main_i2c1: i2c@2010000 {
1622 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1623 reg = <0x0 0x2010000 0x0 0x100>;
1624 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
1625 #address-cells = <1>;
1626 #size-cells = <0>;
1627 clock-names = "fck";
1628 clocks = <&k3_clks 188 0>;
1629 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1630 status = "disabled";
Vignesh Raghavendra01ec6a52020-01-27 23:22:13 +0530[diff] [blame]1631 };
1632
1633 main_i2c2: i2c@2020000 {
1634 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1635 reg = <0x0 0x2020000 0x0 0x100>;
1636 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1637 #address-cells = <1>;
1638 #size-cells = <0>;
1639 clock-names = "fck";
1640 clocks = <&k3_clks 189 0>;
1641 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1642 status = "disabled";
Vignesh Raghavendra01ec6a52020-01-27 23:22:13 +0530[diff] [blame]1643 };
1644
1645 main_i2c3: i2c@2030000 {
1646 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1647 reg = <0x0 0x2030000 0x0 0x100>;
1648 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
1649 #address-cells = <1>;
1650 #size-cells = <0>;
1651 clock-names = "fck";
1652 clocks = <&k3_clks 190 0>;
1653 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1654 status = "disabled";
Vignesh Raghavendra01ec6a52020-01-27 23:22:13 +0530[diff] [blame]1655 };
1656
1657 main_i2c4: i2c@2040000 {
1658 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1659 reg = <0x0 0x2040000 0x0 0x100>;
1660 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
1661 #address-cells = <1>;
1662 #size-cells = <0>;
1663 clock-names = "fck";
1664 clocks = <&k3_clks 191 0>;
1665 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1666 status = "disabled";
Vignesh Raghavendra01ec6a52020-01-27 23:22:13 +0530[diff] [blame]1667 };
1668
1669 main_i2c5: i2c@2050000 {
1670 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1671 reg = <0x0 0x2050000 0x0 0x100>;
1672 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1673 #address-cells = <1>;
1674 #size-cells = <0>;
1675 clock-names = "fck";
1676 clocks = <&k3_clks 192 0>;
1677 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1678 status = "disabled";
Vignesh Raghavendra01ec6a52020-01-27 23:22:13 +0530[diff] [blame]1679 };
1680
1681 main_i2c6: i2c@2060000 {
1682 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1683 reg = <0x0 0x2060000 0x0 0x100>;
1684 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1685 #address-cells = <1>;
1686 #size-cells = <0>;
1687 clock-names = "fck";
1688 clocks = <&k3_clks 193 0>;
1689 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1690 status = "disabled";
Vignesh Raghavendra01ec6a52020-01-27 23:22:13 +0530[diff] [blame]1691 };
Jan Kiszkae1c36682020-06-23 13:15:10 +0200[diff] [blame]1692
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1693 ufs_wrapper: ufs-wrapper@4e80000 {
1694 compatible = "ti,j721e-ufs";
1695 reg = <0x0 0x4e80000 0x0 0x100>;
1696 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1697 clocks = <&k3_clks 277 1>;
1698 assigned-clocks = <&k3_clks 277 1>;
1699 assigned-clock-parents = <&k3_clks 277 4>;
1700 ranges;
1701 #address-cells = <2>;
1702 #size-cells = <2>;
1703
1704 ufs@4e84000 {
1705 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1706 reg = <0x0 0x4e84000 0x0 0x10000>;
1707 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1708 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1709 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1710 clock-names = "core_clk", "phy_clk", "ref_clk";
1711 dma-coherent;
1712 };
1713 };
1714
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1715 mhdp: dp-bridge@a000000 {
1716 compatible = "ti,j721e-mhdp8546";
1717 /*
1718 * Note: we do not map DPTX PHY area, as that is handled by
1719 * the PHY driver.
1720 */
1721 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
1722 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */
1723 reg-names = "mhdptx", "j721e-intg";
1724
1725 clocks = <&k3_clks 151 36>;
1726
1727 interrupt-parent = <&gic500>;
1728 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
1729
1730 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1731
1732 dp0_ports: ports {
1733 #address-cells = <1>;
1734 #size-cells = <0>;
1735
1736 port@0 {
1737 reg = <0>;
1738 };
1739
1740 port@4 {
1741 reg = <4>;
1742 };
1743 };
1744 };
1745
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1746 dss: dss@4a00000 {
1747 compatible = "ti,j721e-dss";
1748 reg =
1749 <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1750 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1751 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1752 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1753
1754 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1755 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1756 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1757 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1758
1759 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1760 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1761 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1762 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1763
1764 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1765 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1766 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1767 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1768 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1769
1770 reg-names = "common_m", "common_s0",
1771 "common_s1", "common_s2",
1772 "vidl1", "vidl2","vid1","vid2",
1773 "ovr1", "ovr2", "ovr3", "ovr4",
1774 "vp1", "vp2", "vp3", "vp4",
1775 "wb";
1776
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1777 clocks = <&k3_clks 152 0>,
1778 <&k3_clks 152 1>,
1779 <&k3_clks 152 4>,
1780 <&k3_clks 152 9>,
1781 <&k3_clks 152 13>;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1782 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1783
1784 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1785
1786 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
1787 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
1788 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
1789 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1790 interrupt-names = "common_m",
1791 "common_s0",
1792 "common_s1",
1793 "common_s2";
1794
1795 dss_ports: ports {
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1796 };
1797 };
1798
1799 mcasp0: mcasp@2b00000 {
1800 compatible = "ti,am33xx-mcasp-audio";
1801 reg = <0x0 0x02b00000 0x0 0x2000>,
1802 <0x0 0x02b08000 0x0 0x1000>;
1803 reg-names = "mpu","dat";
1804 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
1805 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
1806 interrupt-names = "tx", "rx";
1807
1808 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1809 dma-names = "tx", "rx";
1810
1811 clocks = <&k3_clks 174 1>;
1812 clock-names = "fck";
1813 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1814 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1815 };
1816
1817 mcasp1: mcasp@2b10000 {
1818 compatible = "ti,am33xx-mcasp-audio";
1819 reg = <0x0 0x02b10000 0x0 0x2000>,
1820 <0x0 0x02b18000 0x0 0x1000>;
1821 reg-names = "mpu","dat";
1822 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
1823 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
1824 interrupt-names = "tx", "rx";
1825
1826 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1827 dma-names = "tx", "rx";
1828
1829 clocks = <&k3_clks 175 1>;
1830 clock-names = "fck";
1831 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1832 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1833 };
1834
1835 mcasp2: mcasp@2b20000 {
1836 compatible = "ti,am33xx-mcasp-audio";
1837 reg = <0x0 0x02b20000 0x0 0x2000>,
1838 <0x0 0x02b28000 0x0 0x1000>;
1839 reg-names = "mpu","dat";
1840 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
1841 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
1842 interrupt-names = "tx", "rx";
1843
1844 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1845 dma-names = "tx", "rx";
1846
1847 clocks = <&k3_clks 176 1>;
1848 clock-names = "fck";
1849 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1850 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1851 };
1852
1853 mcasp3: mcasp@2b30000 {
1854 compatible = "ti,am33xx-mcasp-audio";
1855 reg = <0x0 0x02b30000 0x0 0x2000>,
1856 <0x0 0x02b38000 0x0 0x1000>;
1857 reg-names = "mpu","dat";
1858 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
1859 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1860 interrupt-names = "tx", "rx";
1861
1862 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1863 dma-names = "tx", "rx";
1864
1865 clocks = <&k3_clks 177 1>;
1866 clock-names = "fck";
1867 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1868 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1869 };
1870
1871 mcasp4: mcasp@2b40000 {
1872 compatible = "ti,am33xx-mcasp-audio";
1873 reg = <0x0 0x02b40000 0x0 0x2000>,
1874 <0x0 0x02b48000 0x0 0x1000>;
1875 reg-names = "mpu","dat";
1876 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
1877 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
1878 interrupt-names = "tx", "rx";
1879
1880 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
1881 dma-names = "tx", "rx";
1882
1883 clocks = <&k3_clks 178 1>;
1884 clock-names = "fck";
1885 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1886 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1887 };
1888
1889 mcasp5: mcasp@2b50000 {
1890 compatible = "ti,am33xx-mcasp-audio";
1891 reg = <0x0 0x02b50000 0x0 0x2000>,
1892 <0x0 0x02b58000 0x0 0x1000>;
1893 reg-names = "mpu","dat";
1894 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
1895 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
1896 interrupt-names = "tx", "rx";
1897
1898 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
1899 dma-names = "tx", "rx";
1900
1901 clocks = <&k3_clks 179 1>;
1902 clock-names = "fck";
1903 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1904 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1905 };
1906
1907 mcasp6: mcasp@2b60000 {
1908 compatible = "ti,am33xx-mcasp-audio";
1909 reg = <0x0 0x02b60000 0x0 0x2000>,
1910 <0x0 0x02b68000 0x0 0x1000>;
1911 reg-names = "mpu","dat";
1912 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
1913 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
1914 interrupt-names = "tx", "rx";
1915
1916 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
1917 dma-names = "tx", "rx";
1918
1919 clocks = <&k3_clks 180 1>;
1920 clock-names = "fck";
1921 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1922 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1923 };
1924
1925 mcasp7: mcasp@2b70000 {
1926 compatible = "ti,am33xx-mcasp-audio";
1927 reg = <0x0 0x02b70000 0x0 0x2000>,
1928 <0x0 0x02b78000 0x0 0x1000>;
1929 reg-names = "mpu","dat";
1930 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
1931 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
1932 interrupt-names = "tx", "rx";
1933
1934 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
1935 dma-names = "tx", "rx";
1936
1937 clocks = <&k3_clks 181 1>;
1938 clock-names = "fck";
1939 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1940 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1941 };
1942
1943 mcasp8: mcasp@2b80000 {
1944 compatible = "ti,am33xx-mcasp-audio";
1945 reg = <0x0 0x02b80000 0x0 0x2000>,
1946 <0x0 0x02b88000 0x0 0x1000>;
1947 reg-names = "mpu","dat";
1948 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
1949 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
1950 interrupt-names = "tx", "rx";
1951
1952 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
1953 dma-names = "tx", "rx";
1954
1955 clocks = <&k3_clks 182 1>;
1956 clock-names = "fck";
1957 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1958 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1959 };
1960
1961 mcasp9: mcasp@2b90000 {
1962 compatible = "ti,am33xx-mcasp-audio";
1963 reg = <0x0 0x02b90000 0x0 0x2000>,
1964 <0x0 0x02b98000 0x0 0x1000>;
1965 reg-names = "mpu","dat";
1966 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
1967 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
1968 interrupt-names = "tx", "rx";
1969
1970 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
1971 dma-names = "tx", "rx";
1972
1973 clocks = <&k3_clks 183 1>;
1974 clock-names = "fck";
1975 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1976 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1977 };
1978
1979 mcasp10: mcasp@2ba0000 {
1980 compatible = "ti,am33xx-mcasp-audio";
1981 reg = <0x0 0x02ba0000 0x0 0x2000>,
1982 <0x0 0x02ba8000 0x0 0x1000>;
1983 reg-names = "mpu","dat";
1984 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
1985 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
1986 interrupt-names = "tx", "rx";
1987
1988 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
1989 dma-names = "tx", "rx";
1990
1991 clocks = <&k3_clks 184 1>;
1992 clock-names = "fck";
1993 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]1994 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]1995 };
1996
1997 mcasp11: mcasp@2bb0000 {
1998 compatible = "ti,am33xx-mcasp-audio";
1999 reg = <0x0 0x02bb0000 0x0 0x2000>,
2000 <0x0 0x02bb8000 0x0 0x1000>;
2001 reg-names = "mpu","dat";
2002 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
2003 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
2004 interrupt-names = "tx", "rx";
2005
2006 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
2007 dma-names = "tx", "rx";
2008
2009 clocks = <&k3_clks 185 1>;
2010 clock-names = "fck";
2011 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]2012 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]2013 };
2014
Jan Kiszkae1c36682020-06-23 13:15:10 +0200[diff] [blame]2015 watchdog0: watchdog@2200000 {
2016 compatible = "ti,j7-rti-wdt";
2017 reg = <0x0 0x2200000 0x0 0x100>;
2018 clocks = <&k3_clks 252 1>;
2019 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
2020 assigned-clocks = <&k3_clks 252 1>;
2021 assigned-clock-parents = <&k3_clks 252 5>;
2022 };
2023
2024 watchdog1: watchdog@2210000 {
2025 compatible = "ti,j7-rti-wdt";
2026 reg = <0x0 0x2210000 0x0 0x100>;
2027 clocks = <&k3_clks 253 1>;
2028 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
2029 assigned-clocks = <&k3_clks 253 1>;
2030 assigned-clock-parents = <&k3_clks 253 5>;
2031 };
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]2032
2033 main_r5fss0: r5fss@5c00000 {
2034 compatible = "ti,j721e-r5fss";
2035 ti,cluster-mode = <1>;
2036 #address-cells = <1>;
2037 #size-cells = <1>;
2038 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
2039 <0x5d00000 0x00 0x5d00000 0x20000>;
2040 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
2041
2042 main_r5fss0_core0: r5f@5c00000 {
2043 compatible = "ti,j721e-r5f";
2044 reg = <0x5c00000 0x00008000>,
2045 <0x5c10000 0x00008000>;
2046 reg-names = "atcm", "btcm";
2047 ti,sci = <&dmsc>;
2048 ti,sci-dev-id = <245>;
2049 ti,sci-proc-ids = <0x06 0xff>;
2050 resets = <&k3_reset 245 1>;
2051 firmware-name = "j7-main-r5f0_0-fw";
2052 ti,atcm-enable = <1>;
2053 ti,btcm-enable = <1>;
2054 ti,loczrama = <1>;
2055 };
2056
2057 main_r5fss0_core1: r5f@5d00000 {
2058 compatible = "ti,j721e-r5f";
2059 reg = <0x5d00000 0x00008000>,
2060 <0x5d10000 0x00008000>;
2061 reg-names = "atcm", "btcm";
2062 ti,sci = <&dmsc>;
2063 ti,sci-dev-id = <246>;
2064 ti,sci-proc-ids = <0x07 0xff>;
2065 resets = <&k3_reset 246 1>;
2066 firmware-name = "j7-main-r5f0_1-fw";
2067 ti,atcm-enable = <1>;
2068 ti,btcm-enable = <1>;
2069 ti,loczrama = <1>;
2070 };
2071 };
2072
2073 main_r5fss1: r5fss@5e00000 {
2074 compatible = "ti,j721e-r5fss";
2075 ti,cluster-mode = <1>;
2076 #address-cells = <1>;
2077 #size-cells = <1>;
2078 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
2079 <0x5f00000 0x00 0x5f00000 0x20000>;
2080 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
2081
2082 main_r5fss1_core0: r5f@5e00000 {
2083 compatible = "ti,j721e-r5f";
2084 reg = <0x5e00000 0x00008000>,
2085 <0x5e10000 0x00008000>;
2086 reg-names = "atcm", "btcm";
2087 ti,sci = <&dmsc>;
2088 ti,sci-dev-id = <247>;
2089 ti,sci-proc-ids = <0x08 0xff>;
2090 resets = <&k3_reset 247 1>;
2091 firmware-name = "j7-main-r5f1_0-fw";
2092 ti,atcm-enable = <1>;
2093 ti,btcm-enable = <1>;
2094 ti,loczrama = <1>;
2095 };
2096
2097 main_r5fss1_core1: r5f@5f00000 {
2098 compatible = "ti,j721e-r5f";
2099 reg = <0x5f00000 0x00008000>,
2100 <0x5f10000 0x00008000>;
2101 reg-names = "atcm", "btcm";
2102 ti,sci = <&dmsc>;
2103 ti,sci-dev-id = <248>;
2104 ti,sci-proc-ids = <0x09 0xff>;
2105 resets = <&k3_reset 248 1>;
2106 firmware-name = "j7-main-r5f1_1-fw";
2107 ti,atcm-enable = <1>;
2108 ti,btcm-enable = <1>;
2109 ti,loczrama = <1>;
2110 };
2111 };
2112
2113 c66_0: dsp@4d80800000 {
2114 compatible = "ti,j721e-c66-dsp";
2115 reg = <0x4d 0x80800000 0x00 0x00048000>,
2116 <0x4d 0x80e00000 0x00 0x00008000>,
2117 <0x4d 0x80f00000 0x00 0x00008000>;
2118 reg-names = "l2sram", "l1pram", "l1dram";
2119 ti,sci = <&dmsc>;
2120 ti,sci-dev-id = <142>;
2121 ti,sci-proc-ids = <0x03 0xff>;
2122 resets = <&k3_reset 142 1>;
2123 firmware-name = "j7-c66_0-fw";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]2124 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]2125 };
2126
2127 c66_1: dsp@4d81800000 {
2128 compatible = "ti,j721e-c66-dsp";
2129 reg = <0x4d 0x81800000 0x00 0x00048000>,
2130 <0x4d 0x81e00000 0x00 0x00008000>,
2131 <0x4d 0x81f00000 0x00 0x00008000>;
2132 reg-names = "l2sram", "l1pram", "l1dram";
2133 ti,sci = <&dmsc>;
2134 ti,sci-dev-id = <143>;
2135 ti,sci-proc-ids = <0x04 0xff>;
2136 resets = <&k3_reset 143 1>;
2137 firmware-name = "j7-c66_1-fw";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]2138 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]2139 };
2140
2141 c71_0: dsp@64800000 {
2142 compatible = "ti,j721e-c71-dsp";
2143 reg = <0x00 0x64800000 0x00 0x00080000>,
2144 <0x00 0x64e00000 0x00 0x0000c000>;
2145 reg-names = "l2sram", "l1dram";
2146 ti,sci = <&dmsc>;
2147 ti,sci-dev-id = <15>;
2148 ti,sci-proc-ids = <0x30 0xff>;
2149 resets = <&k3_reset 15 1>;
2150 firmware-name = "j7-c71_0-fw";
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]2151 status = "disabled";
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]2152 };
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]2153
2154 icssg0: icssg@b000000 {
2155 compatible = "ti,j721e-icssg";
2156 reg = <0x00 0xb000000 0x00 0x80000>;
2157 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
2158 #address-cells = <1>;
2159 #size-cells = <1>;
2160 ranges = <0x0 0x00 0x0b000000 0x100000>;
2161
2162 icssg0_mem: memories@0 {
2163 reg = <0x0 0x2000>,
2164 <0x2000 0x2000>,
2165 <0x10000 0x10000>;
2166 reg-names = "dram0", "dram1",
2167 "shrdram2";
2168 };
2169
2170 icssg0_cfg: cfg@26000 {
2171 compatible = "ti,pruss-cfg", "syscon";
2172 reg = <0x26000 0x200>;
2173 #address-cells = <1>;
2174 #size-cells = <1>;
2175 ranges = <0x0 0x26000 0x2000>;
2176
2177 clocks {
2178 #address-cells = <1>;
2179 #size-cells = <0>;
2180
2181 icssg0_coreclk_mux: coreclk-mux@3c {
2182 reg = <0x3c>;
2183 #clock-cells = <0>;
2184 clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
2185 <&k3_clks 119 1>; /* icssg0_iclk */
2186 assigned-clocks = <&icssg0_coreclk_mux>;
2187 assigned-clock-parents = <&k3_clks 119 1>;
2188 };
2189
2190 icssg0_iepclk_mux: iepclk-mux@30 {
2191 reg = <0x30>;
2192 #clock-cells = <0>;
2193 clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */
2194 <&icssg0_coreclk_mux>; /* core_clk */
2195 assigned-clocks = <&icssg0_iepclk_mux>;
2196 assigned-clock-parents = <&icssg0_coreclk_mux>;
2197 };
2198 };
2199 };
2200
2201 icssg0_mii_rt: mii-rt@32000 {
2202 compatible = "ti,pruss-mii", "syscon";
2203 reg = <0x32000 0x100>;
2204 };
2205
2206 icssg0_mii_g_rt: mii-g-rt@33000 {
2207 compatible = "ti,pruss-mii-g", "syscon";
2208 reg = <0x33000 0x1000>;
2209 };
2210
2211 icssg0_intc: interrupt-controller@20000 {
2212 compatible = "ti,icssg-intc";
2213 reg = <0x20000 0x2000>;
2214 interrupt-controller;
2215 #interrupt-cells = <3>;
2216 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2217 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2218 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2219 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
2220 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
2221 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
2222 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2223 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
2224 interrupt-names = "host_intr0", "host_intr1",
2225 "host_intr2", "host_intr3",
2226 "host_intr4", "host_intr5",
2227 "host_intr6", "host_intr7";
2228 };
2229
2230 pru0_0: pru@34000 {
2231 compatible = "ti,j721e-pru";
2232 reg = <0x34000 0x3000>,
2233 <0x22000 0x100>,
2234 <0x22400 0x100>;
2235 reg-names = "iram", "control", "debug";
2236 firmware-name = "j7-pru0_0-fw";
2237 };
2238
2239 rtu0_0: rtu@4000 {
2240 compatible = "ti,j721e-rtu";
2241 reg = <0x4000 0x2000>,
2242 <0x23000 0x100>,
2243 <0x23400 0x100>;
2244 reg-names = "iram", "control", "debug";
2245 firmware-name = "j7-rtu0_0-fw";
2246 };
2247
2248 tx_pru0_0: txpru@a000 {
2249 compatible = "ti,j721e-tx-pru";
2250 reg = <0xa000 0x1800>,
2251 <0x25000 0x100>,
2252 <0x25400 0x100>;
2253 reg-names = "iram", "control", "debug";
2254 firmware-name = "j7-txpru0_0-fw";
2255 };
2256
2257 pru0_1: pru@38000 {
2258 compatible = "ti,j721e-pru";
2259 reg = <0x38000 0x3000>,
2260 <0x24000 0x100>,
2261 <0x24400 0x100>;
2262 reg-names = "iram", "control", "debug";
2263 firmware-name = "j7-pru0_1-fw";
2264 };
2265
2266 rtu0_1: rtu@6000 {
2267 compatible = "ti,j721e-rtu";
2268 reg = <0x6000 0x2000>,
2269 <0x23800 0x100>,
2270 <0x23c00 0x100>;
2271 reg-names = "iram", "control", "debug";
2272 firmware-name = "j7-rtu0_1-fw";
2273 };
2274
2275 tx_pru0_1: txpru@c000 {
2276 compatible = "ti,j721e-tx-pru";
2277 reg = <0xc000 0x1800>,
2278 <0x25800 0x100>,
2279 <0x25c00 0x100>;
2280 reg-names = "iram", "control", "debug";
2281 firmware-name = "j7-txpru0_1-fw";
2282 };
2283
2284 icssg0_mdio: mdio@32400 {
2285 compatible = "ti,davinci_mdio";
2286 reg = <0x32400 0x100>;
2287 clocks = <&k3_clks 119 1>;
2288 clock-names = "fck";
2289 #address-cells = <1>;
2290 #size-cells = <0>;
2291 bus_freq = <1000000>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]2292 status = "disabled";
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]2293 };
2294 };
2295
2296 icssg1: icssg@b100000 {
2297 compatible = "ti,j721e-icssg";
2298 reg = <0x00 0xb100000 0x00 0x80000>;
2299 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
2300 #address-cells = <1>;
2301 #size-cells = <1>;
2302 ranges = <0x0 0x00 0x0b100000 0x100000>;
2303
2304 icssg1_mem: memories@b100000 {
2305 reg = <0x0 0x2000>,
2306 <0x2000 0x2000>,
2307 <0x10000 0x10000>;
2308 reg-names = "dram0", "dram1",
2309 "shrdram2";
2310 };
2311
2312 icssg1_cfg: cfg@26000 {
2313 compatible = "ti,pruss-cfg", "syscon";
2314 reg = <0x26000 0x200>;
2315 #address-cells = <1>;
2316 #size-cells = <1>;
2317 ranges = <0x0 0x26000 0x2000>;
2318
2319 clocks {
2320 #address-cells = <1>;
2321 #size-cells = <0>;
2322
2323 icssg1_coreclk_mux: coreclk-mux@3c {
2324 reg = <0x3c>;
2325 #clock-cells = <0>;
2326 clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
2327 <&k3_clks 120 4>; /* icssg1_iclk */
2328 assigned-clocks = <&icssg1_coreclk_mux>;
2329 assigned-clock-parents = <&k3_clks 120 4>;
2330 };
2331
2332 icssg1_iepclk_mux: iepclk-mux@30 {
2333 reg = <0x30>;
2334 #clock-cells = <0>;
2335 clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */
2336 <&icssg1_coreclk_mux>; /* core_clk */
2337 assigned-clocks = <&icssg1_iepclk_mux>;
2338 assigned-clock-parents = <&icssg1_coreclk_mux>;
2339 };
2340 };
2341 };
2342
2343 icssg1_mii_rt: mii-rt@32000 {
2344 compatible = "ti,pruss-mii", "syscon";
2345 reg = <0x32000 0x100>;
2346 };
2347
2348 icssg1_mii_g_rt: mii-g-rt@33000 {
2349 compatible = "ti,pruss-mii-g", "syscon";
2350 reg = <0x33000 0x1000>;
2351 };
2352
2353 icssg1_intc: interrupt-controller@20000 {
2354 compatible = "ti,icssg-intc";
2355 reg = <0x20000 0x2000>;
2356 interrupt-controller;
2357 #interrupt-cells = <3>;
2358 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2359 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2360 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
2361 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
2362 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2363 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2364 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2365 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2366 interrupt-names = "host_intr0", "host_intr1",
2367 "host_intr2", "host_intr3",
2368 "host_intr4", "host_intr5",
2369 "host_intr6", "host_intr7";
2370 };
2371
2372 pru1_0: pru@34000 {
2373 compatible = "ti,j721e-pru";
2374 reg = <0x34000 0x4000>,
2375 <0x22000 0x100>,
2376 <0x22400 0x100>;
2377 reg-names = "iram", "control", "debug";
2378 firmware-name = "j7-pru1_0-fw";
2379 };
2380
2381 rtu1_0: rtu@4000 {
2382 compatible = "ti,j721e-rtu";
2383 reg = <0x4000 0x2000>,
2384 <0x23000 0x100>,
2385 <0x23400 0x100>;
2386 reg-names = "iram", "control", "debug";
2387 firmware-name = "j7-rtu1_0-fw";
2388 };
2389
2390 tx_pru1_0: txpru@a000 {
2391 compatible = "ti,j721e-tx-pru";
2392 reg = <0xa000 0x1800>,
2393 <0x25000 0x100>,
2394 <0x25400 0x100>;
2395 reg-names = "iram", "control", "debug";
2396 firmware-name = "j7-txpru1_0-fw";
2397 };
2398
2399 pru1_1: pru@38000 {
2400 compatible = "ti,j721e-pru";
2401 reg = <0x38000 0x4000>,
2402 <0x24000 0x100>,
2403 <0x24400 0x100>;
2404 reg-names = "iram", "control", "debug";
2405 firmware-name = "j7-pru1_1-fw";
2406 };
2407
2408 rtu1_1: rtu@6000 {
2409 compatible = "ti,j721e-rtu";
2410 reg = <0x6000 0x2000>,
2411 <0x23800 0x100>,
2412 <0x23c00 0x100>;
2413 reg-names = "iram", "control", "debug";
2414 firmware-name = "j7-rtu1_1-fw";
2415 };
2416
2417 tx_pru1_1: txpru@c000 {
2418 compatible = "ti,j721e-tx-pru";
2419 reg = <0xc000 0x1800>,
2420 <0x25800 0x100>,
2421 <0x25c00 0x100>;
2422 reg-names = "iram", "control", "debug";
2423 firmware-name = "j7-txpru1_1-fw";
2424 };
2425
2426 icssg1_mdio: mdio@32400 {
2427 compatible = "ti,davinci_mdio";
2428 reg = <0x32400 0x100>;
2429 clocks = <&k3_clks 120 4>;
2430 clock-names = "fck";
2431 #address-cells = <1>;
2432 #size-cells = <0>;
2433 bus_freq = <1000000>;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]2434 status = "disabled";
Tom Rinifa09b122021-09-10 17:37:43 -0400[diff] [blame]2435 };
2436 };
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]2437
2438 main_mcan0: can@2701000 {
2439 compatible = "bosch,m_can";
2440 reg = <0x00 0x02701000 0x00 0x200>,
2441 <0x00 0x02708000 0x00 0x8000>;
2442 reg-names = "m_can", "message_ram";
2443 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
2444 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
2445 clock-names = "hclk", "cclk";
2446 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
2447 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
2448 interrupt-names = "int0", "int1";
2449 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2450 status = "disabled";
2451 };
2452
2453 main_mcan1: can@2711000 {
2454 compatible = "bosch,m_can";
2455 reg = <0x00 0x02711000 0x00 0x200>,
2456 <0x00 0x02718000 0x00 0x8000>;
2457 reg-names = "m_can", "message_ram";
2458 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
2459 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
2460 clock-names = "hclk", "cclk";
2461 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
2462 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
2463 interrupt-names = "int0", "int1";
2464 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2465 status = "disabled";
2466 };
2467
2468 main_mcan2: can@2721000 {
2469 compatible = "bosch,m_can";
2470 reg = <0x00 0x02721000 0x00 0x200>,
2471 <0x00 0x02728000 0x00 0x8000>;
2472 reg-names = "m_can", "message_ram";
2473 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
2474 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
2475 clock-names = "hclk", "cclk";
2476 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2477 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2478 interrupt-names = "int0", "int1";
2479 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2480 status = "disabled";
2481 };
2482
2483 main_mcan3: can@2731000 {
2484 compatible = "bosch,m_can";
2485 reg = <0x00 0x02731000 0x00 0x200>,
2486 <0x00 0x02738000 0x00 0x8000>;
2487 reg-names = "m_can", "message_ram";
2488 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
2489 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
2490 clock-names = "hclk", "cclk";
2491 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
2492 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2493 interrupt-names = "int0", "int1";
2494 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2495 status = "disabled";
2496 };
2497
2498 main_mcan4: can@2741000 {
2499 compatible = "bosch,m_can";
2500 reg = <0x00 0x02741000 0x00 0x200>,
2501 <0x00 0x02748000 0x00 0x8000>;
2502 reg-names = "m_can", "message_ram";
2503 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
2504 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
2505 clock-names = "hclk", "cclk";
2506 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2507 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
2508 interrupt-names = "int0", "int1";
2509 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2510 status = "disabled";
2511 };
2512
2513 main_mcan5: can@2751000 {
2514 compatible = "bosch,m_can";
2515 reg = <0x00 0x02751000 0x00 0x200>,
2516 <0x00 0x02758000 0x00 0x8000>;
2517 reg-names = "m_can", "message_ram";
2518 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
2519 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
2520 clock-names = "hclk", "cclk";
2521 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
2522 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
2523 interrupt-names = "int0", "int1";
2524 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2525 status = "disabled";
2526 };
2527
2528 main_mcan6: can@2761000 {
2529 compatible = "bosch,m_can";
2530 reg = <0x00 0x02761000 0x00 0x200>,
2531 <0x00 0x02768000 0x00 0x8000>;
2532 reg-names = "m_can", "message_ram";
2533 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
2534 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
2535 clock-names = "hclk", "cclk";
2536 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2537 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
2538 interrupt-names = "int0", "int1";
2539 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2540 status = "disabled";
2541 };
2542
2543 main_mcan7: can@2771000 {
2544 compatible = "bosch,m_can";
2545 reg = <0x00 0x02771000 0x00 0x200>,
2546 <0x00 0x02778000 0x00 0x8000>;
2547 reg-names = "m_can", "message_ram";
2548 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
2549 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
2550 clock-names = "hclk", "cclk";
2551 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2552 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2553 interrupt-names = "int0", "int1";
2554 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2555 status = "disabled";
2556 };
2557
2558 main_mcan8: can@2781000 {
2559 compatible = "bosch,m_can";
2560 reg = <0x00 0x02781000 0x00 0x200>,
2561 <0x00 0x02788000 0x00 0x8000>;
2562 reg-names = "m_can", "message_ram";
2563 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
2564 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
2565 clock-names = "hclk", "cclk";
2566 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
2567 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
2568 interrupt-names = "int0", "int1";
2569 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2570 status = "disabled";
2571 };
2572
2573 main_mcan9: can@2791000 {
2574 compatible = "bosch,m_can";
2575 reg = <0x00 0x02791000 0x00 0x200>,
2576 <0x00 0x02798000 0x00 0x8000>;
2577 reg-names = "m_can", "message_ram";
2578 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
2579 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
2580 clock-names = "hclk", "cclk";
2581 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
2582 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2583 interrupt-names = "int0", "int1";
2584 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2585 status = "disabled";
2586 };
2587
2588 main_mcan10: can@27a1000 {
2589 compatible = "bosch,m_can";
2590 reg = <0x00 0x027a1000 0x00 0x200>,
2591 <0x00 0x027a8000 0x00 0x8000>;
2592 reg-names = "m_can", "message_ram";
2593 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
2594 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
2595 clock-names = "hclk", "cclk";
2596 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
2597 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2598 interrupt-names = "int0", "int1";
2599 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2600 status = "disabled";
2601 };
2602
2603 main_mcan11: can@27b1000 {
2604 compatible = "bosch,m_can";
2605 reg = <0x00 0x027b1000 0x00 0x200>,
2606 <0x00 0x027b8000 0x00 0x8000>;
2607 reg-names = "m_can", "message_ram";
2608 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
2609 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
2610 clock-names = "hclk", "cclk";
2611 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
2612 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2613 interrupt-names = "int0", "int1";
2614 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2615 status = "disabled";
2616 };
2617
2618 main_mcan12: can@27c1000 {
2619 compatible = "bosch,m_can";
2620 reg = <0x00 0x027c1000 0x00 0x200>,
2621 <0x00 0x027c8000 0x00 0x8000>;
2622 reg-names = "m_can", "message_ram";
2623 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
2624 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
2625 clock-names = "hclk", "cclk";
2626 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
2627 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
2628 interrupt-names = "int0", "int1";
2629 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2630 status = "disabled";
2631 };
2632
2633 main_mcan13: can@27d1000 {
2634 compatible = "bosch,m_can";
2635 reg = <0x00 0x027d1000 0x00 0x200>,
2636 <0x00 0x027d8000 0x00 0x8000>;
2637 reg-names = "m_can", "message_ram";
2638 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
2639 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
2640 clock-names = "hclk", "cclk";
2641 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
2642 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
2643 interrupt-names = "int0", "int1";
2644 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2645 status = "disabled";
2646 };
2647
2648 main_spi0: spi@2100000 {
2649 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2650 reg = <0x00 0x02100000 0x00 0x400>;
2651 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2652 #address-cells = <1>;
2653 #size-cells = <0>;
2654 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
2655 clocks = <&k3_clks 266 1>;
2656 status = "disabled";
2657 };
2658
2659 main_spi1: spi@2110000 {
2660 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2661 reg = <0x00 0x02110000 0x00 0x400>;
2662 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
2663 #address-cells = <1>;
2664 #size-cells = <0>;
2665 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
2666 clocks = <&k3_clks 267 1>;
2667 status = "disabled";
2668 };
2669
2670 main_spi2: spi@2120000 {
2671 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2672 reg = <0x00 0x02120000 0x00 0x400>;
2673 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
2674 #address-cells = <1>;
2675 #size-cells = <0>;
2676 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
2677 clocks = <&k3_clks 268 1>;
2678 status = "disabled";
2679 };
2680
2681 main_spi3: spi@2130000 {
2682 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2683 reg = <0x00 0x02130000 0x00 0x400>;
2684 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
2685 #address-cells = <1>;
2686 #size-cells = <0>;
2687 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
2688 clocks = <&k3_clks 269 1>;
2689 status = "disabled";
2690 };
2691
2692 main_spi4: spi@2140000 {
2693 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2694 reg = <0x00 0x02140000 0x00 0x400>;
2695 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
2696 #address-cells = <1>;
2697 #size-cells = <0>;
2698 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
2699 clocks = <&k3_clks 270 1>;
2700 status = "disabled";
2701 };
2702
2703 main_spi5: spi@2150000 {
2704 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2705 reg = <0x00 0x02150000 0x00 0x400>;
2706 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
2707 #address-cells = <1>;
2708 #size-cells = <0>;
2709 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
2710 clocks = <&k3_clks 271 1>;
2711 status = "disabled";
2712 };
2713
2714 main_spi6: spi@2160000 {
2715 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2716 reg = <0x00 0x02160000 0x00 0x400>;
2717 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
2718 #address-cells = <1>;
2719 #size-cells = <0>;
2720 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
2721 clocks = <&k3_clks 272 1>;
2722 status = "disabled";
2723 };
2724
2725 main_spi7: spi@2170000 {
2726 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2727 reg = <0x00 0x02170000 0x00 0x400>;
2728 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
2729 #address-cells = <1>;
2730 #size-cells = <0>;
2731 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
2732 clocks = <&k3_clks 273 1>;
2733 status = "disabled";
2734 };
2735
2736 main_esm: esm@700000 {
2737 compatible = "ti,j721e-esm";
2738 reg = <0x0 0x700000 0x0 0x1000>;
2739 ti,esm-pins = <344>, <345>;
2740 };
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]2741};