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Andy Fleming5f184712011-04-08 02:10:27 -05001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
Andy Flemingb21f87a32014-07-25 17:39:08 -05003 * Andy Fleming <afleming@gmail.com>
Andy Fleming5f184712011-04-08 02:10:27 -05004 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Andy Fleming5f184712011-04-08 02:10:27 -05006 *
7 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
8 */
9
10#ifndef _PHY_H
11#define _PHY_H
12
13#include <linux/list.h>
14#include <linux/mii.h>
15#include <linux/ethtool.h>
16#include <linux/mdio.h>
17
18#define PHY_MAX_ADDR 32
19
20#define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
21 SUPPORTED_10baseT_Full | \
22 SUPPORTED_100baseT_Half | \
23 SUPPORTED_100baseT_Full | \
24 SUPPORTED_Autoneg | \
25 SUPPORTED_TP | \
26 SUPPORTED_MII)
27
28#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \
29 SUPPORTED_1000baseT_Half | \
30 SUPPORTED_1000baseT_Full)
31
32#define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
33 SUPPORTED_10000baseT_Full)
34
Stefan Roese4fb3f0c2014-10-22 12:13:15 +020035#ifndef PHY_ANEG_TIMEOUT
Andy Fleming5f184712011-04-08 02:10:27 -050036#define PHY_ANEG_TIMEOUT 4000
Stefan Roese4fb3f0c2014-10-22 12:13:15 +020037#endif
Andy Fleming5f184712011-04-08 02:10:27 -050038
39
40typedef enum {
41 PHY_INTERFACE_MODE_MII,
42 PHY_INTERFACE_MODE_GMII,
43 PHY_INTERFACE_MODE_SGMII,
Shengzhou Liuc35f8692014-10-23 17:20:57 +080044 PHY_INTERFACE_MODE_SGMII_2500,
Shaohui Xie7794b1a2013-03-25 07:39:31 +000045 PHY_INTERFACE_MODE_QSGMII,
Andy Fleming5f184712011-04-08 02:10:27 -050046 PHY_INTERFACE_MODE_TBI,
47 PHY_INTERFACE_MODE_RMII,
48 PHY_INTERFACE_MODE_RGMII,
49 PHY_INTERFACE_MODE_RGMII_ID,
50 PHY_INTERFACE_MODE_RGMII_RXID,
51 PHY_INTERFACE_MODE_RGMII_TXID,
52 PHY_INTERFACE_MODE_RTBI,
53 PHY_INTERFACE_MODE_XGMII,
Simon Glassc74c8e62015-04-05 16:07:39 -060054 PHY_INTERFACE_MODE_NONE, /* Must be last */
55
56 PHY_INTERFACE_MODE_COUNT,
Andy Fleming5f184712011-04-08 02:10:27 -050057} phy_interface_t;
58
59static const char *phy_interface_strings[] = {
60 [PHY_INTERFACE_MODE_MII] = "mii",
61 [PHY_INTERFACE_MODE_GMII] = "gmii",
62 [PHY_INTERFACE_MODE_SGMII] = "sgmii",
Shengzhou Liuc35f8692014-10-23 17:20:57 +080063 [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
Shaohui Xie7794b1a2013-03-25 07:39:31 +000064 [PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
Andy Fleming5f184712011-04-08 02:10:27 -050065 [PHY_INTERFACE_MODE_TBI] = "tbi",
66 [PHY_INTERFACE_MODE_RMII] = "rmii",
67 [PHY_INTERFACE_MODE_RGMII] = "rgmii",
68 [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
69 [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
70 [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
71 [PHY_INTERFACE_MODE_RTBI] = "rtbi",
72 [PHY_INTERFACE_MODE_XGMII] = "xgmii",
73 [PHY_INTERFACE_MODE_NONE] = "",
74};
75
76static inline const char *phy_string_for_interface(phy_interface_t i)
77{
78 /* Default to unknown */
79 if (i > PHY_INTERFACE_MODE_NONE)
80 i = PHY_INTERFACE_MODE_NONE;
81
82 return phy_interface_strings[i];
83}
84
85
86struct phy_device;
87
88#define MDIO_NAME_LEN 32
89
90struct mii_dev {
91 struct list_head link;
92 char name[MDIO_NAME_LEN];
93 void *priv;
94 int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
95 int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
96 u16 val);
97 int (*reset)(struct mii_dev *bus);
98 struct phy_device *phymap[PHY_MAX_ADDR];
99 u32 phy_mask;
100};
101
102/* struct phy_driver: a structure which defines PHY behavior
103 *
104 * uid will contain a number which represents the PHY. During
105 * startup, the driver will poll the PHY to find out what its
106 * UID--as defined by registers 2 and 3--is. The 32-bit result
107 * gotten from the PHY will be masked to
108 * discard any bits which may change based on revision numbers
109 * unimportant to functionality
110 *
111 */
112struct phy_driver {
113 char *name;
114 unsigned int uid;
115 unsigned int mask;
116 unsigned int mmds;
117
118 u32 features;
119
120 /* Called to do any driver startup necessities */
121 /* Will be called during phy_connect */
122 int (*probe)(struct phy_device *phydev);
123
124 /* Called to configure the PHY, and modify the controller
125 * based on the results. Should be called after phy_connect */
126 int (*config)(struct phy_device *phydev);
127
128 /* Called when starting up the controller */
129 int (*startup)(struct phy_device *phydev);
130
131 /* Called when bringing down the controller */
132 int (*shutdown)(struct phy_device *phydev);
133
Stefano Babicb71841b2013-09-02 15:42:30 +0200134 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
135 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
136 u16 val);
Andy Fleming5f184712011-04-08 02:10:27 -0500137 struct list_head list;
138};
139
140struct phy_device {
141 /* Information about the PHY type */
142 /* And management functions */
143 struct mii_dev *bus;
144 struct phy_driver *drv;
145 void *priv;
146
Simon Glassc74c8e62015-04-05 16:07:39 -0600147#ifdef CONFIG_DM_ETH
148 struct udevice *dev;
149#else
Andy Fleming5f184712011-04-08 02:10:27 -0500150 struct eth_device *dev;
Simon Glassc74c8e62015-04-05 16:07:39 -0600151#endif
Andy Fleming5f184712011-04-08 02:10:27 -0500152
153 /* forced speed & duplex (no autoneg)
154 * partner speed & duplex & pause (autoneg)
155 */
156 int speed;
157 int duplex;
158
159 /* The most recently read link state */
160 int link;
161 int port;
162 phy_interface_t interface;
163
164 u32 advertising;
165 u32 supported;
166 u32 mmds;
167
168 int autoneg;
169 int addr;
170 int pause;
171 int asym_pause;
172 u32 phy_id;
173 u32 flags;
174};
175
Shaohui Xief55a7762013-11-14 19:00:31 +0800176struct fixed_link {
177 int phy_id;
178 int duplex;
179 int link_speed;
180 int pause;
181 int asym_pause;
182};
183
Andy Fleming5f184712011-04-08 02:10:27 -0500184static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
185{
186 struct mii_dev *bus = phydev->bus;
187
188 return bus->read(bus, phydev->addr, devad, regnum);
189}
190
191static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
192 u16 val)
193{
194 struct mii_dev *bus = phydev->bus;
195
196 return bus->write(bus, phydev->addr, devad, regnum, val);
197}
198
199#ifdef CONFIG_PHYLIB_10G
200extern struct phy_driver gen10g_driver;
201
202/* For now, XGMII is the only 10G interface */
203static inline int is_10g_interface(phy_interface_t interface)
204{
205 return interface == PHY_INTERFACE_MODE_XGMII;
206}
207
208#endif
209
210int phy_init(void);
211int phy_reset(struct phy_device *phydev);
Troy Kisky1adb4062012-10-22 16:40:43 +0000212struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
213 phy_interface_t interface);
Simon Glassc74c8e62015-04-05 16:07:39 -0600214#ifdef CONFIG_DM_ETH
215void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
216struct phy_device *phy_connect(struct mii_dev *bus, int addr,
217 struct udevice *dev,
218 phy_interface_t interface);
219#else
Troy Kisky1adb4062012-10-22 16:40:43 +0000220void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
Andy Fleming5f184712011-04-08 02:10:27 -0500221struct phy_device *phy_connect(struct mii_dev *bus, int addr,
222 struct eth_device *dev,
223 phy_interface_t interface);
Simon Glassc74c8e62015-04-05 16:07:39 -0600224#endif
Andy Fleming5f184712011-04-08 02:10:27 -0500225int phy_startup(struct phy_device *phydev);
226int phy_config(struct phy_device *phydev);
227int phy_shutdown(struct phy_device *phydev);
228int phy_register(struct phy_driver *drv);
229int genphy_config_aneg(struct phy_device *phydev);
Troy Kisky8682aba2012-02-07 14:08:48 +0000230int genphy_restart_aneg(struct phy_device *phydev);
Andy Fleming5f184712011-04-08 02:10:27 -0500231int genphy_update_link(struct phy_device *phydev);
Yegor Yefremove2043f52012-11-28 11:15:17 +0100232int genphy_parse_link(struct phy_device *phydev);
Andy Fleming5f184712011-04-08 02:10:27 -0500233int genphy_config(struct phy_device *phydev);
234int genphy_startup(struct phy_device *phydev);
235int genphy_shutdown(struct phy_device *phydev);
236int gen10g_config(struct phy_device *phydev);
237int gen10g_startup(struct phy_device *phydev);
238int gen10g_shutdown(struct phy_device *phydev);
239int gen10g_discover_mmds(struct phy_device *phydev);
240
Shaohui Xief7c38cf2014-12-30 18:32:04 +0800241int phy_aquantia_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500242int phy_atheros_init(void);
243int phy_broadcom_init(void);
Shengzhou Liu9b18e512014-11-10 18:32:29 +0800244int phy_cortina_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500245int phy_davicom_init(void);
Matt Porterf485c8a2013-03-20 05:38:13 +0000246int phy_et1011c_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500247int phy_lxt_init(void);
248int phy_marvell_init(void);
249int phy_micrel_init(void);
250int phy_natsemi_init(void);
251int phy_realtek_init(void);
Vladimir Zapolskiyb6abf552011-12-29 15:18:37 +0000252int phy_smsc_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500253int phy_teranetics_init(void);
Edgar E. Iglesias721aed72015-09-25 23:46:08 -0700254int phy_ti_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500255int phy_vitesse_init(void);
Timur Tabia8366262011-10-18 18:44:34 -0500256
Fabio Estevam2fb63962014-02-15 14:52:00 -0200257int board_phy_config(struct phy_device *phydev);
Shengzhou Liu5707d5f2015-04-07 18:46:32 +0800258int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
Fabio Estevam2fb63962014-02-15 14:52:00 -0200259
Simon Glassc74c8e62015-04-05 16:07:39 -0600260/**
261 * phy_get_interface_by_name() - Look up a PHY interface name
262 *
263 * @str: PHY interface name, e.g. "mii"
264 * @return PHY_INTERFACE_MODE_... value, or -1 if not found
265 */
266int phy_get_interface_by_name(const char *str);
267
Timur Tabia8366262011-10-18 18:44:34 -0500268/* PHY UIDs for various PHYs that are referenced in external code */
Shengzhou Liu9b18e512014-11-10 18:32:29 +0800269#define PHY_UID_CS4340 0x13e51002
Timur Tabia8366262011-10-18 18:44:34 -0500270#define PHY_UID_TN2020 0x00a19410
271
Andy Fleming5f184712011-04-08 02:10:27 -0500272#endif