blob: efdc333493ec6d40413d37cf87b12f2346958048 [file] [log] [blame]
Heiko Schocher2605e902007-02-16 07:57:42 +01001/*
2 * (C) Copyright 2007
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc5xxx.h>
29#include <pci.h>
30#include <asm/processor.h>
Grant Likelycf2817a2007-09-06 09:46:23 -060031#include <libfdt.h>
Heiko Schocher2605e902007-02-16 07:57:42 +010032
33#define SDRAM_DDR 0
34#if 1
35/* Settings Icecube */
36#define SDRAM_MODE 0x00CD0000
37#define SDRAM_CONTROL 0x504F0000
38#define SDRAM_CONFIG1 0xD2322800
39#define SDRAM_CONFIG2 0x8AD70000
40#else
41/*Settings Jupiter UB 1.0.0 */
42#define SDRAM_MODE 0x008D0000
43#define SDRAM_CONTROL 0xD04F0000
44#define SDRAM_CONFIG1 0xf7277f00
45#define SDRAM_CONFIG2 0x88b70004
46#endif
47
48#ifndef CFG_RAMBOOT
49static void sdram_start (int hi_addr)
50{
51 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
52
53 /* unlock mode register */
54 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
55 __asm__ volatile ("sync");
56
57 /* precharge all banks */
58 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
59 __asm__ volatile ("sync");
60
61#if SDRAM_DDR
62 /* set mode register: extended mode */
63 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
64 __asm__ volatile ("sync");
65
66 /* set mode register: reset DLL */
67 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
68 __asm__ volatile ("sync");
69#endif
70
71 /* precharge all banks */
72 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
73 __asm__ volatile ("sync");
74
75 /* auto refresh */
76 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
77 __asm__ volatile ("sync");
78
79 /* set mode register */
80 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
81 __asm__ volatile ("sync");
82
83 /* normal operation */
84 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
85 __asm__ volatile ("sync");
86}
87#endif
88
89/*
90 * ATTENTION: Although partially referenced initdram does NOT make real use
91 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
92 * is something else than 0x00000000.
93 */
94
95long int initdram (int board_type)
96{
97 ulong dramsize = 0;
98 ulong dramsize2 = 0;
99 uint svr, pvr;
100
101#ifndef CFG_RAMBOOT
102 ulong test1, test2;
103
104 /* setup SDRAM chip selects */
105 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
106 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
107 __asm__ volatile ("sync");
108
109 /* setup config registers */
110 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
111 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
112 __asm__ volatile ("sync");
113
114#if SDRAM_DDR
115 /* set tap delay */
116 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
117 __asm__ volatile ("sync");
118#endif
119
120 /* find RAM size using SDRAM CS0 only */
121 sdram_start(0);
122 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
123 sdram_start(1);
124 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
125 if (test1 > test2) {
126 sdram_start(0);
127 dramsize = test1;
128 } else {
129 dramsize = test2;
130 }
131
132 /* memory smaller than 1MB is impossible */
133 if (dramsize < (1 << 20)) {
134 dramsize = 0;
135 }
136
137 /* set SDRAM CS0 size according to the amount of RAM found */
138 if (dramsize > 0) {
139 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
140 } else {
141 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
142 }
143
144 /* let SDRAM CS1 start right after CS0 */
145 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
146
147 /* find RAM size using SDRAM CS1 only */
148 if (!dramsize)
149 sdram_start(0);
150 test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
151 if (!dramsize) {
152 sdram_start(1);
153 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
154 }
155 if (test1 > test2) {
156 sdram_start(0);
157 dramsize2 = test1;
158 } else {
159 dramsize2 = test2;
160 }
161
162 /* memory smaller than 1MB is impossible */
163 if (dramsize2 < (1 << 20)) {
164 dramsize2 = 0;
165 }
166
167 /* set SDRAM CS1 size according to the amount of RAM found */
168 if (dramsize2 > 0) {
169 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
170 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
171 } else {
172 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
173 }
174
175#else /* CFG_RAMBOOT */
176
177 /* retrieve size of memory connected to SDRAM CS0 */
178 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
179 if (dramsize >= 0x13) {
180 dramsize = (1 << (dramsize - 0x13)) << 20;
181 } else {
182 dramsize = 0;
183 }
184
185 /* retrieve size of memory connected to SDRAM CS1 */
186 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
187 if (dramsize2 >= 0x13) {
188 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
189 } else {
190 dramsize2 = 0;
191 }
192
193#endif /* CFG_RAMBOOT */
194
195 /*
196 * On MPC5200B we need to set the special configuration delay in the
197 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
198 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
199 *
200 * "The SDelay should be written to a value of 0x00000004. It is
201 * required to account for changes caused by normal wafer processing
202 * parameters."
203 */
204 svr = get_svr();
205 pvr = get_pvr();
206 if ((SVR_MJREV(svr) >= 2) &&
207 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
208
209 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
210 __asm__ volatile ("sync");
211 }
212
213 return dramsize + dramsize2;
214}
215
216int checkboard (void)
217{
218 puts ("Board: Sauter (Jupiter)\n");
219 return 0;
220}
221
222void flash_preinit(void)
223{
224 /*
225 * Now, when we are in RAM, enable flash write
226 * access for detection process.
227 * Note that CS_BOOT cannot be cleared when
228 * executing in flash.
229 */
230#if defined(CONFIG_MGT5100)
231 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
232 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
233#endif
234 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
235}
236
237int board_early_init_r (void)
238{
239 flash_preinit ();
240 return 0;
241}
242
243void flash_afterinit(ulong size)
244{
245 if (size == 0x1000000) { /* adjust mapping */
246 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
247 START_REG(CFG_BOOTCS_START | size);
248 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
249 STOP_REG(CFG_BOOTCS_START | size, size);
250 }
251#if defined(CONFIG_MPC5200)
252 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
253 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
254#endif
255}
256
257int update_flash_size (int flash_size)
258{
259 flash_afterinit (flash_size);
260 return 0;
261}
262
263int board_early_init_f (void)
264{
265 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
266 return 0;
267}
268
269#ifdef CONFIG_PCI
270static struct pci_controller hose;
271
272extern void pci_mpc5xxx_init(struct pci_controller *);
273
274void pci_init_board(void)
275{
276 pci_mpc5xxx_init(&hose);
277}
278#endif
279
Jon Loeligerd39b5742007-07-10 10:48:22 -0500280#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
Heiko Schocher2605e902007-02-16 07:57:42 +0100281
282void init_ide_reset (void)
283{
284 debug ("init_ide_reset\n");
285
286 /* Configure PSC1_4 as GPIO output for ATA reset */
287 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
288 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
289 /* Deassert reset */
290 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
291}
292
293void ide_set_reset (int idereset)
294{
295 debug ("ide_reset(%d)\n", idereset);
296
297 if (idereset) {
298 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
299 /* Make a delay. MPC5200 spec says 25 usec min */
300 udelay(500000);
301 } else {
302 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
303 }
304}
Jon Loeligerd39b5742007-07-10 10:48:22 -0500305#endif
Heiko Schocher2605e902007-02-16 07:57:42 +0100306
Grant Likelycf2817a2007-09-06 09:46:23 -0600307#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Heiko Schocher2605e902007-02-16 07:57:42 +0100308void
309ft_board_setup(void *blob, bd_t *bd)
310{
311 ft_cpu_setup(blob, bd);
312}
313#endif