blob: 5ffa6e4b449fce4fa1a6f016027ead4bed360efc [file] [log] [blame]
Matthias Fuchs1a3ac862008-01-17 10:53:08 +01001/*
2 * (C) Copyright 2008
3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
4 *
5 * based on the Sequoia board configuration by
6 * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Matthias Fuchs1a3ac862008-01-17 10:53:08 +01009 */
10
11/*
12 **********************************************************************
13 * DU440.h - configuration for esd's DU440 board (Power PC440EPx)
14 **********************************************************************
15 */
16#ifndef __CONFIG_H
17#define __CONFIG_H
18
19/*
20 * High Level Configuration Options
21 */
22#define CONFIG_DU440 1 /* Board is esd DU440 */
23#define CONFIG_440EPX 1 /* Specific PPC440EPx */
24#define CONFIG_4xx 1 /* ... PPC4xx family */
25#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
26
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027#ifndef CONFIG_SYS_TEXT_BASE
28#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
29#endif
30
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010031#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
32#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
33#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
34
35/*
36 * Base addresses -- Note these are effective addresses where the
37 * actual resources get mapped (not physical addresses)
38 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
40#define CONFIG_SYS_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010041
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
43#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
44#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
Wolfgang Denk14d0a022010-10-07 21:51:12 +020045#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_NAND0_ADDR 0xd0000000 /* NAND Flash */
47#define CONFIG_SYS_NAND1_ADDR 0xd0100000 /* NAND Flash */
48#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
49#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
50#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
51#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
52#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
53#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
Stefan Roese10954932009-11-12 12:00:49 +010054#define CONFIG_SYS_PCI_IOBASE 0xe8000000
55#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
56#define CONFIG_SYS_PCI_SUBSYS_ID 0x0444 /* device ID for DU440 */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010057
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_USB2D0_BASE 0xe0000100
59#define CONFIG_SYS_USB_DEVICE 0xe0000000
60#define CONFIG_SYS_USB_HOST 0xe0000400
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010061
62/*
63 * Initial RAM & stack pointer
64 */
65/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_INIT_RAM_OCM 1 /* OCM as init ram */
67#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010068
Wolfgang Denk553f0982010-10-26 13:32:32 +020069#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020070#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010072
73/*
74 * Serial Port
75 */
Stefan Roese550650d2010-09-20 16:05:31 +020076#define CONFIG_CONS_INDEX 1 /* Use UART0 */
77#define CONFIG_SYS_NS16550
78#define CONFIG_SYS_NS16550_SERIAL
79#define CONFIG_SYS_NS16550_REG_SIZE 1
80#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#undef CONFIG_SYS_EXT_SERIAL_CLOCK
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010082#define CONFIG_BAUDRATE 115200
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010083
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_BAUDRATE_TABLE \
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010085 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
86
87/*
88 * Video Port
89 */
90#define CONFIG_VIDEO
91#define CONFIG_VIDEO_SMI_LYNXEM
92#define CONFIG_CFB_CONSOLE
93#define CONFIG_VIDEO_LOGO
94#define CONFIG_VGA_AS_SINGLE_DEVICE
95#define CONFIG_SPLASH_SCREEN
96#define CONFIG_SPLASH_SCREEN_ALIGN
97#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */
99#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */
100#define CONFIG_SYS_CONSOLE_IS_IN_ENV
101#define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100102
103/*
104 * Environment
105 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200106#define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100107
108/*
109 * FLASH related
110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200112#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
117#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
120#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100123/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_FLASH_EMPTY_INFO
127#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100128
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200129#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200130#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200132#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100133
134/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200135#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
136#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100137#endif
138
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200139#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200140#define CONFIG_ENV_OFFSET 0 /* environment starts at */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100141 /* the beginning of the EEPROM */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200142#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100143#endif
144
145/*
146 * DDR SDRAM
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100149#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
Stefan Roese02e38922008-03-31 12:20:48 +0200151 /* 440EPx errata CHIP 11 */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100152#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100153#define CONFIG_DDR_ECC /* Use ECC when available */
154#define SPD_EEPROM_ADDRESS {0x50}
155#define CONFIG_PROG_SDRAM_TLB
156
157/*
158 * I2C
159 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000160#define CONFIG_SYS_I2C
161#define CONFIG_SYS_I2C_PPC4XX
162#define CONFIG_SYS_I2C_PPC4XX_CH0
163#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
164#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
165#define CONFIG_SYS_I2C_PPC4XX_CH1
166#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 100000
167#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_SPD_BUS_NUM 0
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100170#define IIC1_MCP3021_ADDR 0x4d
171#define IIC1_USB2507_ADDR 0x2c
Dirk Eibach880540d2013-04-25 02:40:01 +0000172#define CONFIG_SYS_I2C_NOPROBES { {1, IIC1_USB2507_ADDR} }
173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_I2C_MULTI_EEPROMS
175#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
176#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
177#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
178#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
179#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_EEPROM_WREN 1
182#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100183
184/*
185 * standard dtt sensor configuration - bottom bit will determine local or
186 * remote sensor of the TMP401
187 */
188#define CONFIG_DTT_SENSORS { 0, 1 }
189
190/*
191 * The PMC440 uses a TI TMP401 temperature sensor. This part
192 * is basically compatible to the ADM1021 that is supported
193 * by U-Boot.
194 *
195 * - i2c addr 0x4c
196 * - conversion rate 0x02 = 0.25 conversions/second
197 * - ALERT ouput disabled
198 * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
199 * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
200 */
201#define CONFIG_DTT_ADM1021
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100203
204/*
205 * RTC stuff
206 */
207#define CONFIG_RTC_DS1338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100209
210#undef CONFIG_BOOTARGS
211
212#define CONFIG_EXTRA_ENV_SETTINGS \
213 "netdev=eth0\0" \
214 "ethrotate=no\0" \
215 "hostname=du440\0" \
216 "nfsargs=setenv bootargs root=/dev/nfs rw " \
217 "nfsroot=${serverip}:${rootpath}\0" \
218 "ramargs=setenv bootargs root=/dev/ram rw\0" \
219 "addip=setenv bootargs ${bootargs} " \
220 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
221 ":${hostname}:${netdev}:off panic=1\0" \
222 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
223 "flash_self=run ramargs addip addtty optargs;" \
224 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
225 "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
Wolfgang Denk93e14592013-10-04 17:43:24 +0200226 "bootm\0" \
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100227 "rootpath=/tftpboot/du440/target_root_du440\0" \
228 "img=/tftpboot/du440/uImage\0" \
229 "kernel_addr=FFC00000\0" \
230 "ramdisk_addr=FFE00000\0" \
231 "initrd_high=30000000\0" \
232 "load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \
233 "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
234 "cp.b 100000 FFFA0000 60000\0" \
235 ""
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100236
237#define CONFIG_PREBOOT /* enable preboot variable */
238
239#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
240
241#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100243
244#ifndef __ASSEMBLY__
245int du440_phy_addr(int devnum);
246#endif
247
Ben Warren96e21f82008-10-27 23:50:15 -0700248#define CONFIG_PPC4xx_EMAC
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100249#define CONFIG_IBM_EMAC4_V4 1
250#define CONFIG_MII 1 /* MII PHY management */
251#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */
252
253#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
Matthias Fuchs7c91f512008-03-30 18:01:15 +0200254#undef CONFIG_PHY_GIGE /* no GbE detection */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100255
256#define CONFIG_HAS_ETH0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_RX_ETH_BUFFER 128
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100258
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100259#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
260#define CONFIG_PHY1_ADDR du440_phy_addr(1)
261
262/*
263 * USB
264 */
265#define CONFIG_USB_OHCI_NEW
266#define CONFIG_USB_STORAGE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_OHCI_BE_CONTROLLER
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
270#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
271#define CONFIG_SYS_USB_OHCI_SLOT_NAME "du440"
272#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100273
274/* Comment this out to enable USB 1.1 device */
275#define USB_2_0_DEVICE
276
277/* Partitions */
278#define CONFIG_MAC_PARTITION
279#define CONFIG_DOS_PARTITION
280#define CONFIG_ISO_PARTITION
281
282#include <config_cmd_default.h>
283
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100284#define CONFIG_CMD_ASKENV
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200285#define CONFIG_CMD_BMP
286#define CONFIG_CMD_BSP
287#define CONFIG_CMD_DATE
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100288#define CONFIG_CMD_DHCP
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100289#define CONFIG_CMD_DIAG
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200290#define CONFIG_CMD_DTT
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100291#define CONFIG_CMD_EEPROM
292#define CONFIG_CMD_ELF
293#define CONFIG_CMD_FAT
294#define CONFIG_CMD_I2C
295#define CONFIG_CMD_IRQ
296#define CONFIG_CMD_MII
297#define CONFIG_CMD_NAND
298#define CONFIG_CMD_NET
299#define CONFIG_CMD_NFS
300#define CONFIG_CMD_PCI
301#define CONFIG_CMD_PING
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100302#define CONFIG_CMD_REGINFO
303#define CONFIG_CMD_SDRAM
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200304#define CONFIG_CMD_SOURCE
305#define CONFIG_CMD_USB
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100306
307#define CONFIG_SUPPORT_VFAT
308
309/*
310 * Miscellaneous configurable options
311 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_LONGHELP /* undef to save memory */
313#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100314#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100316#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100318#endif
319/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
321#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
322#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100323
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
325#define CONFIG_SYS_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100326
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
328#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100329
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100331
332#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
333#define CONFIG_LOOPW 1 /* enable loopw command */
334#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
335#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
336#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
337
Wolfgang Denkc37207d2008-07-16 16:38:59 +0200338#define CONFIG_AUTOBOOT_KEYED 1
339#define CONFIG_AUTOBOOT_PROMPT \
340 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100341#define CONFIG_AUTOBOOT_DELAY_STR "d"
342#define CONFIG_AUTOBOOT_STOP_STR " "
343
344/*
345 * PCI stuff
346 */
347#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000348#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100349#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
350#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100352
353/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_PCI_TARGET_INIT
355#define CONFIG_SYS_PCI_MASTER_INIT
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100356
357/*
358 * For booting Linux, the board info and command line data
359 * have to be in the first 8 MB of memory, since this is
360 * the maximum mapped by the Linux kernel during initialization.
361 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100363
364/*
365 * External Bus Controller (EBC) Setup
366 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_CPLD_BASE 0xC0000000
370#define CONFIG_SYS_CPLD_RANGE 0x00000010
371#define CONFIG_SYS_DUMEM_BASE 0xC0100000
372#define CONFIG_SYS_DUMEM_RANGE 0x00100000
373#define CONFIG_SYS_DUIO_BASE 0xC0200000
374#define CONFIG_SYS_DUIO_RANGE 0x00010000
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100375
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_NAND0_CS 2 /* NAND chip connected to CSx */
377#define CONFIG_SYS_NAND1_CS 3 /* NAND chip connected to CSx */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100378/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_EBC_PB0AP 0x04017200
380#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100381
382/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_EBC_PB1AP 0x018003c0
384#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100385
386/* Memory Bank 2 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_EBC_PB2AP 0x018003c0
388#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND0_ADDR | 0x1c000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100389
390/* Memory Bank 3 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_EBC_PB3AP 0x018003c0
392#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND1_ADDR | 0x1c000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100393
394/* Memory Bank 4 (DUMEM, 1MB) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_EBC_PB4AP 0x018053c0
396#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_DUMEM_BASE | 0x18000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100397
398/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_EBC_PB5AP 0x018053c0
400#define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_DUIO_BASE | 0x18000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100401
402/*
403 * NAND FLASH
404 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_MAX_NAND_DEVICE 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
407#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
408 CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100409
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100410#if defined(CONFIG_CMD_KGDB)
411#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
412#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
413#endif
414
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200415#define CONFIG_SOURCE 1
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100416
Matthias Fuchs35dd0252008-10-07 13:13:07 +0200417#define CONFIG_OF_LIBFDT
418#define CONFIG_OF_BOARD_SETUP
419
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100420#endif /* __CONFIG_H */