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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Alexey Brodkin288aaac2014-02-04 12:56:13 +04002/*
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
Alexey Brodkin288aaac2014-02-04 12:56:13 +04004 */
5
6#ifndef _ASM_ARC_ARCREGS_H
7#define _ASM_ARC_ARCREGS_H
8
Alexey Brodkin812980b2015-02-03 13:58:11 +03009#include <asm/cache.h>
Eugeniy Paltsev5e0c68e2018-03-21 15:58:49 +030010#include <config.h>
Alexey Brodkin812980b2015-02-03 13:58:11 +030011
Alexey Brodkin288aaac2014-02-04 12:56:13 +040012/*
13 * ARC architecture has additional address space - auxiliary registers.
14 * These registers are mostly used for configuration purposes.
15 * These registers are not memory mapped and special commands are used for
16 * access: "lr"/"sr".
17 */
18
Alexey Brodkin85e529f2018-11-27 09:46:57 +030019/*
20 * Typically 8 least significant bits of Build Configuration Register (BCR)
21 * describe version of the HW block in question. Moreover if decoded version
22 * is 0 this means given HW block is absent - this is especially useful because
23 * we may safely read BRC regardless HW block existence while an attempt to
24 * access any other AUX regs associated with this HW block lead to imediate
25 * "instruction error" exception.
26 *
27 * I.e. before using any cofigurable HW block it's required to make sure it
28 * exists at all, and for that we introduce a special macro below.
29 */
30#define ARC_BCR_VERSION_MASK GENMASK(7, 0)
31#define ARC_FEATURE_EXISTS(bcr) !!(__builtin_arc_lr(bcr) & ARC_BCR_VERSION_MASK)
32
Alexey Brodkin288aaac2014-02-04 12:56:13 +040033#define ARC_AUX_IDENTITY 0x04
34#define ARC_AUX_STATUS32 0x0a
35
Alexey Brodkin8f590062018-07-29 09:47:52 +030036/* STATUS32 Bits Positions */
37#define STATUS_AD_BIT 19 /* Enable unaligned access */
38
Alexey Brodkin288aaac2014-02-04 12:56:13 +040039/* Instruction cache related auxiliary registers */
40#define ARC_AUX_IC_IVIC 0x10
41#define ARC_AUX_IC_CTRL 0x11
42#define ARC_AUX_IC_IVIL 0x19
Alexey Brodkin5ff40f32015-02-03 13:58:12 +030043#if (CONFIG_ARC_MMU_VER == 3)
Alexey Brodkin288aaac2014-02-04 12:56:13 +040044#define ARC_AUX_IC_PTAG 0x1E
45#endif
Igor Guryanovf8cf3d12014-12-24 16:07:07 +030046#define ARC_BCR_IC_BUILD 0x77
Eugeniy Paltsev64f47422017-11-28 16:51:07 +030047#define AUX_AUX_CACHE_LIMIT 0x5D
48#define ARC_AUX_NON_VOLATILE_LIMIT 0x5E
49
50/* ICCM and DCCM auxiliary registers */
51#define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */
52#define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */
Alexey Brodkin288aaac2014-02-04 12:56:13 +040053
54/* Timer related auxiliary registers */
55#define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
56#define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */
57#define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */
58
Vlad Zakharovad9b5f72017-03-21 14:49:47 +030059#define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */
60#define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */
61#define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */
62
Alexey Brodkin288aaac2014-02-04 12:56:13 +040063#define ARC_AUX_INTR_VEC_BASE 0x25
64
65/* Data cache related auxiliary registers */
66#define ARC_AUX_DC_IVDC 0x47
67#define ARC_AUX_DC_CTRL 0x48
68
69#define ARC_AUX_DC_IVDL 0x4A
70#define ARC_AUX_DC_FLSH 0x4B
71#define ARC_AUX_DC_FLDL 0x4C
Alexey Brodkin5ff40f32015-02-03 13:58:12 +030072#if (CONFIG_ARC_MMU_VER == 3)
Alexey Brodkin288aaac2014-02-04 12:56:13 +040073#define ARC_AUX_DC_PTAG 0x5C
74#endif
Igor Guryanovf8cf3d12014-12-24 16:07:07 +030075#define ARC_BCR_DC_BUILD 0x72
Alexey Brodkin6eb15e52015-03-30 13:36:04 +030076#define ARC_BCR_SLC 0xce
Alexey Brodkinef639e62015-05-18 16:56:26 +030077#define ARC_AUX_SLC_CONFIG 0x901
78#define ARC_AUX_SLC_CTRL 0x903
Alexey Brodkin6eb15e52015-03-30 13:36:04 +030079#define ARC_AUX_SLC_FLUSH 0x904
80#define ARC_AUX_SLC_INVALIDATE 0x905
Alexey Brodkinef639e62015-05-18 16:56:26 +030081#define ARC_AUX_SLC_IVDL 0x910
82#define ARC_AUX_SLC_FLDL 0x912
Eugeniy Paltsev41cada42018-01-16 19:20:26 +030083#define ARC_AUX_SLC_RGN_START 0x914
84#define ARC_AUX_SLC_RGN_START1 0x915
85#define ARC_AUX_SLC_RGN_END 0x916
86#define ARC_AUX_SLC_RGN_END1 0x917
Alexey Brodkindb6ce232015-12-14 17:15:13 +030087#define ARC_BCR_CLUSTER 0xcf
88
Eugeniy Paltsev41cada42018-01-16 19:20:26 +030089/* MMU Management regs */
Alexey Brodkin85e529f2018-11-27 09:46:57 +030090#define ARC_AUX_MMU_BCR 0x6f
Eugeniy Paltsev41cada42018-01-16 19:20:26 +030091
Alexey Brodkindb6ce232015-12-14 17:15:13 +030092/* IO coherency related auxiliary registers */
93#define ARC_AUX_IO_COH_ENABLE 0x500
94#define ARC_AUX_IO_COH_PARTIAL 0x501
95#define ARC_AUX_IO_COH_AP0_BASE 0x508
96#define ARC_AUX_IO_COH_AP0_SIZE 0x509
Alexey Brodkin288aaac2014-02-04 12:56:13 +040097
Alexey Brodkin85e529f2018-11-27 09:46:57 +030098/* XY-memory related */
99#define ARC_AUX_XY_BUILD 0x79
100
101/* DSP-extensions related auxiliary registers */
102#define ARC_AUX_DSP_BUILD 0x7A
103
104/* ARC Subsystems related auxiliary registers */
105#define ARC_AUX_SUBSYS_BUILD 0xF0
106
Alexey Brodkin288aaac2014-02-04 12:56:13 +0400107#ifndef __ASSEMBLY__
108/* Accessors for auxiliary registers */
109#define read_aux_reg(reg) __builtin_arc_lr(reg)
110
111/* gcc builtin sr needs reg param to be long immediate */
112#define write_aux_reg(reg_immed, val) \
113 __builtin_arc_sr((unsigned int)val, reg_immed)
Eugeniy Paltseve59c3792017-11-28 16:48:40 +0300114
115/* ARCNUM [15:8] - field to identify each core in a multi-core system */
116#define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8)
Eugeniy Paltsev5e0c68e2018-03-21 15:58:49 +0300117
118static const inline int is_isa_arcv2(void)
119{
120 return IS_ENABLED(CONFIG_ISA_ARCV2);
121}
122
123static const inline int is_isa_arcompact(void)
124{
125 return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
126}
Alexey Brodkin288aaac2014-02-04 12:56:13 +0400127#endif /* __ASSEMBLY__ */
128
129#endif /* _ASM_ARC_ARCREGS_H */