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Dirk Eibachb9944a72013-06-26 15:55:17 +02001/*
2 * (C) Copyright 2013
3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
4 *
5 * based on P1022DS.h
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29#ifdef CONFIG_36BIT
30#define CONFIG_PHYS_64BIT
31#endif
32
33#ifdef CONFIG_SDCARD
34#define CONFIG_RAMBOOT_SDCARD
35#endif
36
37#ifdef CONFIG_SPIFLASH
38#define CONFIG_RAMBOOT_SPIFLASH
39#endif
40
41/* High Level Configuration Options */
42#define CONFIG_BOOKE /* BOOKE */
43#define CONFIG_E500 /* BOOKE e500 family */
Dirk Eibachb9944a72013-06-26 15:55:17 +020044#define CONFIG_P1022
45#define CONFIG_CONTROLCENTERD
46#define CONFIG_MP /* support multiple processors */
47
Dirk Eibachd9f923f2014-07-25 10:10:24 +020048
Dirk Eibachb9944a72013-06-26 15:55:17 +020049#define CONFIG_SYS_NO_FLASH
50#define CONFIG_ENABLE_36BIT_PHYS
51#define CONFIG_FSL_LAW /* Use common FSL init code */
52
53#ifdef CONFIG_TRAILBLAZER
54#define CONFIG_IDENT_STRING " controlcenterd trailblazer 0.01"
55#else
56#define CONFIG_IDENT_STRING " controlcenterd 0.01"
57#endif
58
59#ifdef CONFIG_PHYS_64BIT
60#define CONFIG_ADDR_MAP
61#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
62#endif
63
64#define CONFIG_L2_CACHE
65#define CONFIG_BTB
66
67#define CONFIG_SYS_CLK_FREQ 66666600
68#define CONFIG_DDR_CLK_FREQ 66666600
69
70#define CONFIG_SYS_RAMBOOT
71
72#ifdef CONFIG_TRAILBLAZER
73
74#define CONFIG_SYS_TEXT_BASE 0xf8fc0000
75#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
76#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
77
78/*
79 * Config the L2 Cache
80 */
81#define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000
82#ifdef CONFIG_PHYS_64BIT
83#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull
84#else
85#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
86#endif
87#define CONFIG_SYS_L2_SIZE (256 << 10)
88#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
89
90#else /* CONFIG_TRAILBLAZER */
91
92#define CONFIG_SYS_TEXT_BASE 0x11000000
93#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
94#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
95
96#endif /* CONFIG_TRAILBLAZER */
97
98#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
99#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
100
101
102/*
103 * Memory map
104 *
105 * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
106 * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable
107 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
108 *
109 * Localbus non-cacheable
110 * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable
111 * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable
112 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
113 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
114 */
115
116#define CONFIG_SYS_INIT_RAM_LOCK
117#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
118#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */
119#define CONFIG_SYS_GBL_DATA_OFFSET \
120 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
121#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
122
123#ifdef CONFIG_TRAILBLAZER
124/* leave CCSRBAR at default, because u-boot expects it to be exactly there */
125#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
126#else
127#define CONFIG_SYS_CCSRBAR 0xffe00000
128#endif
129#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
130#define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200)
131
132/*
133 * DDR Setup
134 */
135
136#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
137#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
138#define CONFIG_SYS_SDRAM_SIZE 1024
139#define CONFIG_VERY_BIG_RAM
140
York Sun5614e712013-09-30 09:22:09 -0700141#define CONFIG_SYS_FSL_DDR3
Dirk Eibachb9944a72013-06-26 15:55:17 +0200142#define CONFIG_NUM_DDR_CONTROLLERS 1
143#define CONFIG_DIMM_SLOTS_PER_CTLR 1
144#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
145
146#define CONFIG_SYS_MEMTEST_START 0x00000000
147#define CONFIG_SYS_MEMTEST_END 0x3fffffff
148
149#ifdef CONFIG_TRAILBLAZER
150#define CONFIG_SPD_EEPROM
151#define SPD_EEPROM_ADDRESS 0x52
152/*#define CONFIG_FSL_DDR_INTERACTIVE*/
153#endif
154
155/*
156 * Local Bus Definitions
157 */
158#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
159
160#define CONFIG_SYS_ELBC_BASE 0xe0000000
161#ifdef CONFIG_PHYS_64BIT
162#define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull
163#else
164#define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE
165#endif
166
167#define CONFIG_UART_BR_PRELIM \
168 (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
169#define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7)
170
171#define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */
172#define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */
173
174#define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM
175#define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM
176
177/*
178 * Serial Port
179 */
180#define CONFIG_CONS_INDEX 2
Dirk Eibachb9944a72013-06-26 15:55:17 +0200181#define CONFIG_SYS_NS16550_SERIAL
182#define CONFIG_SYS_NS16550_REG_SIZE 1
183#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
184
185#define CONFIG_SYS_BAUDRATE_TABLE \
186 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
187
188#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
189#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
190
191/*
192 * I2C
193 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200194#define CONFIG_SYS_I2C
195#define CONFIG_SYS_I2C_FSL
196#define CONFIG_SYS_FSL_I2C_SPEED 400000
197#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
198#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
199#define CONFIG_SYS_FSL_I2C2_SPEED 400000
200#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
201#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Dirk Eibach5568fb42014-07-03 09:28:21 +0200202
203#ifndef CONFIG_TRAILBLAZER
204#define CONFIG_CMD_I2C
205#endif
Dirk Eibachb9944a72013-06-26 15:55:17 +0200206
207#define CONFIG_PCA9698 /* NXP PCA9698 */
208
209#define CONFIG_CMD_EEPROM
210#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
211#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
212
213#ifndef CONFIG_TRAILBLAZER
214/*
215 * eSPI - Enhanced SPI
216 */
217#define CONFIG_HARD_SPI
Dirk Eibachb9944a72013-06-26 15:55:17 +0200218
Dirk Eibachb9944a72013-06-26 15:55:17 +0200219
220#define CONFIG_CMD_SF
221#define CONFIG_SF_DEFAULT_SPEED 10000000
222#define CONFIG_SF_DEFAULT_MODE 0
223#endif
224
Dirk Eibachb9944a72013-06-26 15:55:17 +0200225#define CONFIG_SHA1
Dirk Eibachb9944a72013-06-26 15:55:17 +0200226
227/*
228 * MMC
229 */
230#define CONFIG_MMC
231#define CONFIG_GENERIC_MMC
232#define CONFIG_CMD_MMC
233
234#define CONFIG_FSL_ESDHC
235#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
236
237
238#ifndef CONFIG_TRAILBLAZER
239
240/*
241 * Video
242 */
243#define CONFIG_FSL_DIU_FB
244#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
245#define CONFIG_VIDEO
246#define CONFIG_CFB_CONSOLE
247#define CONFIG_VGA_AS_SINGLE_DEVICE
248#define CONFIG_CMD_BMP
249
250/*
251 * General PCI
252 * Memory space is mapped 1-1, but I/O space must start from 0.
253 */
254#define CONFIG_PCI /* Enable PCI/PCIE */
255#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
256#define CONFIG_PCI_INDIRECT_BRIDGE
257#define CONFIG_PCI_PNP /* do pci plug-and-play */
258#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
259#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
260#define CONFIG_CMD_PCI
261
262#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
263#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
264
265#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
266#ifdef CONFIG_PHYS_64BIT
267#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
268#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
269#else
270#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
271#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
272#endif
273#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
274#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
275#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
276#ifdef CONFIG_PHYS_64BIT
277#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
278#else
279#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
280#endif
281#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
282
283/*
284 * SATA
285 */
286#define CONFIG_LIBATA
287#define CONFIG_LBA48
288#define CONFIG_CMD_SATA
289
290#define CONFIG_FSL_SATA
291#define CONFIG_SYS_SATA_MAX_DEVICE 2
292#define CONFIG_SATA1
293#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
294#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
295#define CONFIG_SATA2
296#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
297#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
298
299/*
300 * Ethernet
301 */
302#define CONFIG_TSEC_ENET
303
304#define CONFIG_TSECV2
305
306#define CONFIG_MII /* MII PHY management */
307#define CONFIG_TSEC1 1
308#define CONFIG_TSEC1_NAME "eTSEC1"
309#define CONFIG_TSEC2 1
310#define CONFIG_TSEC2_NAME "eTSEC2"
311
312#define TSEC1_PHY_ADDR 0
313#define TSEC2_PHY_ADDR 1
314
315#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
316#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
317
318#define TSEC1_PHYIDX 0
319#define TSEC2_PHYIDX 0
320
321#define CONFIG_ETHPRIME "eTSEC1"
322
323#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
324
325/*
326 * USB
327 */
328#define CONFIG_USB_EHCI
329#define CONFIG_CMD_USB
330#define CONFIG_USB_STORAGE
331
332#define CONFIG_HAS_FSL_DR_USB
333#define CONFIG_USB_EHCI_FSL
334#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
335
336#endif /* CONFIG_TRAILBLAZER */
337
338/*
339 * Environment
340 */
341#if defined(CONFIG_TRAILBLAZER)
342#define CONFIG_ENV_IS_NOWHERE
343#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
Dirk Eibachb9944a72013-06-26 15:55:17 +0200344#elif defined(CONFIG_RAMBOOT_SPIFLASH)
345#define CONFIG_ENV_IS_IN_SPI_FLASH
346#define CONFIG_ENV_SPI_BUS 0
347#define CONFIG_ENV_SPI_CS 0
348#define CONFIG_ENV_SPI_MAX_HZ 10000000
349#define CONFIG_ENV_SPI_MODE 0
350#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
351#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
352#define CONFIG_ENV_SECT_SIZE 0x10000
353#elif defined(CONFIG_RAMBOOT_SDCARD)
354#define CONFIG_ENV_IS_IN_MMC
355#define CONFIG_FSL_FIXED_MMC_LOCATION
356#define CONFIG_ENV_SIZE 0x2000
357#define CONFIG_SYS_MMC_ENV_DEV 0
358#endif
359
360#define CONFIG_SYS_EXTRA_ENV_RELOC
361
362#define CONFIG_SYS_CONSOLE_IS_IN_ENV
363
364/*
365 * Command line configuration.
366 */
367#ifndef CONFIG_TRAILBLAZER
368#define CONFIG_SYS_HUSH_PARSER
369#define CONFIG_SYS_LONGHELP
370#define CONFIG_CMDLINE_EDITING /* Command-line editing */
371#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
372#endif /* CONFIG_TRAILBLAZER */
373
374#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Dirk Eibachb9944a72013-06-26 15:55:17 +0200375#ifdef CONFIG_CMD_KGDB
376#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
377#else
378#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
379#endif
380/* Print Buffer Size */
381#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
382#define CONFIG_SYS_MAXARGS 16
383#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
384
Dirk Eibachb9944a72013-06-26 15:55:17 +0200385#ifndef CONFIG_TRAILBLAZER
386
Dirk Eibachb9944a72013-06-26 15:55:17 +0200387#define CONFIG_CMD_ERRATA
388#define CONFIG_CMD_EXT2
389#define CONFIG_CMD_FAT
390#define CONFIG_CMD_IRQ
391#define CONFIG_CMD_MII
Dirk Eibachb9944a72013-06-26 15:55:17 +0200392#define CONFIG_CMD_PING
Dirk Eibachb9944a72013-06-26 15:55:17 +0200393#define CONFIG_CMD_REGINFO
394
395/*
396 * Board initialisation callbacks
397 */
398#define CONFIG_BOARD_EARLY_INIT_F
399#define CONFIG_BOARD_EARLY_INIT_R
400#define CONFIG_MISC_INIT_R
401#define CONFIG_LAST_STAGE_INIT
402
403/*
404 * Pass open firmware flat tree
405 */
406#define CONFIG_OF_LIBFDT
407#define CONFIG_OF_BOARD_SETUP
408#define CONFIG_OF_STDOUT_VIA_ALIAS
409
410/* new uImage format support */
411#define CONFIG_FIT
412#define CONFIG_FIT_VERBOSE
413
414#else /* CONFIG_TRAILBLAZER */
415
416#define CONFIG_BOARD_EARLY_INIT_F
417#define CONFIG_BOARD_EARLY_INIT_R
418#define CONFIG_LAST_STAGE_INIT
Dirk Eibachb9944a72013-06-26 15:55:17 +0200419
420#endif /* CONFIG_TRAILBLAZER */
421
422/*
423 * Miscellaneous configurable options
424 */
Dirk Eibachb9944a72013-06-26 15:55:17 +0200425#define CONFIG_HW_WATCHDOG
426#define CONFIG_LOADS_ECHO
427#define CONFIG_SYS_LOADS_BAUD_CHANGE
428#define CONFIG_DOS_PARTITION
429
430/*
431 * For booting Linux, the board info and command line data
432 * have to be in the first 64 MB of memory, since this is
433 * the maximum mapped by the Linux kernel during initialization.
434 */
435#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */
436#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
437
438/*
439 * Environment Configuration
440 */
441
442#ifdef CONFIG_TRAILBLAZER
443
444#define CONFIG_BOOTDELAY 0 /* -1 disables auto-boot */
445#define CONFIG_BAUDRATE 115200
446
447#define CONFIG_EXTRA_ENV_SETTINGS \
448 "mp_holdoff=1\0"
449
450#else
451
452#define CONFIG_HOSTNAME controlcenterd
453#define CONFIG_ROOTPATH "/opt/nfsroot"
454#define CONFIG_BOOTFILE "uImage"
455#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */
456
457#define CONFIG_LOADADDR 1000000
458
459#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
460
461#define CONFIG_BAUDRATE 115200
462
463#define CONFIG_EXTRA_ENV_SETTINGS \
464 "netdev=eth0\0" \
465 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
466 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
467 "tftpflash=tftpboot $loadaddr $uboot && " \
468 "protect off $ubootaddr +$filesize && " \
469 "erase $ubootaddr +$filesize && " \
470 "cp.b $loadaddr $ubootaddr $filesize && " \
471 "protect on $ubootaddr +$filesize && " \
472 "cmp.b $loadaddr $ubootaddr $filesize\0" \
473 "consoledev=ttyS1\0" \
474 "ramdiskaddr=2000000\0" \
475 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
476 "fdtaddr=c00000\0" \
477 "fdtfile=controlcenterd.dtb\0" \
478 "bdev=sda3\0"
479
480/* these are used and NUL-terminated in env_default.h */
481#define CONFIG_NFSBOOTCOMMAND \
482 "setenv bootargs root=/dev/nfs rw " \
483 "nfsroot=$serverip:$rootpath " \
484 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
485 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
486 "tftp $loadaddr $bootfile;" \
487 "tftp $fdtaddr $fdtfile;" \
488 "bootm $loadaddr - $fdtaddr"
489
490#define CONFIG_RAMBOOTCOMMAND \
491 "setenv bootargs root=/dev/ram rw " \
492 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
493 "tftp $ramdiskaddr $ramdiskfile;" \
494 "tftp $loadaddr $bootfile;" \
495 "tftp $fdtaddr $fdtfile;" \
496 "bootm $loadaddr $ramdiskaddr $fdtaddr"
497
498#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
499
500#endif /* CONFIG_TRAILBLAZER */
501
502#endif