blob: 3c4a70c45e8bfaf5456b6f4caa97e573c0dafdf5 [file] [log] [blame]
Heiko Schocher03efcb02013-08-05 16:00:38 +02001/*
2 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
3 * Based on:
4 * U-Boot:include/configs/da850evm.h
5 *
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 * Based on davinci_dvevm.h. Original Copyrights follow:
9 *
10 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
11 *
12 * SPDX-License-Identifier: GPL-2.0+
13 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/*
19 * Board
20 */
21#define CONFIG_DRIVER_TI_EMAC
22#define CONFIG_BARIX_IPAM390
23
24/*
25 * SoC Configuration
26 */
27#define CONFIG_MACH_DAVINCI_DA850_EVM
Heiko Schocher03efcb02013-08-05 16:00:38 +020028#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
29#define CONFIG_SOC_DA850 /* TI DA850 SoC */
30#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
31#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
32#define CONFIG_SYS_OSCIN_FREQ 24000000
33#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
34#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
Heiko Schocher03efcb02013-08-05 16:00:38 +020035#define CONFIG_SYS_DA850_PLL_INIT
36#define CONFIG_SYS_DA850_DDR_INIT
37#define CONFIG_SYS_TEXT_BASE 0xc1080000
38
39/*
40 * Memory Info
41 */
42#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
43#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
44#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
45#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
46
47/* memtest start addr */
48#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
49
50/* memtest will be run on 16MB */
51#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024)
52
53#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
54
55#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
56 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
57 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
58 DAVINCI_SYSCFG_SUSPSRC_UART0 | \
59 DAVINCI_SYSCFG_SUSPSRC_EMAC)
60
61/*
62 * PLL configuration
63 */
64#define CONFIG_SYS_DV_CLKMODE 0
65#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
66#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
67#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
68#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
69#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
70#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
71#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
72#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
73
74#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
75#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
76#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
77#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
78
79#define CONFIG_SYS_DA850_PLL0_PLLM 24
80#define CONFIG_SYS_DA850_PLL1_PLLM 24
81
82/*
83 * DDR2 memory configuration
84 */
85#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
86 DV_DDR_PHY_EXT_STRBEN | \
87 (0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT))
88#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000498
89
90#define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004
91#define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020
92
93
94#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
95 (13 << DV_DDR_SDTMR1_RFC_SHIFT) | \
96 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
97 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
98 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
99 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
100 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
101 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
102 (1 << DV_DDR_SDTMR1_WTR_SHIFT))
103
104#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
105 (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
106 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
107 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
108 (14 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
109 (0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
110 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
111 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
112
113#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
114 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
115 (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \
116 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
117 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
118 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
119 (2 << DV_DDR_SDCR_CL_SHIFT) | \
120 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
121 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
122
Heiko Schocher660a2e62013-09-06 05:21:24 +0200123#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
Heiko Schocher03efcb02013-08-05 16:00:38 +0200124 DAVINCI_ABCR_WSTROBE(2) | \
Heiko Schocher660a2e62013-09-06 05:21:24 +0200125 DAVINCI_ABCR_WHOLD(0) | \
Heiko Schocher03efcb02013-08-05 16:00:38 +0200126 DAVINCI_ABCR_RSETUP(1) | \
Heiko Schocher660a2e62013-09-06 05:21:24 +0200127 DAVINCI_ABCR_RSTROBE(2) | \
128 DAVINCI_ABCR_RHOLD(1) | \
129 DAVINCI_ABCR_TA(0) | \
Heiko Schocher03efcb02013-08-05 16:00:38 +0200130 DAVINCI_ABCR_ASIZE_8BIT)
131
132
133/*
134 * Serial Driver info
135 */
Heiko Schocher03efcb02013-08-05 16:00:38 +0200136#define CONFIG_SYS_NS16550_SERIAL
137#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
138#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
139#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
140#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
141#define CONFIG_BAUDRATE 115200 /* Default baud rate */
142
143/*
144 * Flash & Environment
145 */
146#define CONFIG_NAND_DAVINCI
147#define CONFIG_SYS_NO_FLASH
148#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
149#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
150#define CONFIG_ENV_SIZE (128 << 10)
151#define CONFIG_SYS_NAND_USE_FLASH_BBT
152#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
153#define CONFIG_SYS_NAND_PAGE_2K
154#define CONFIG_SYS_NAND_CS 3
155#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
156#define CONFIG_SYS_NAND_MASK_CLE 0x10
157#define CONFIG_SYS_NAND_MASK_ALE 0x8
158#undef CONFIG_SYS_NAND_HW_ECC
159#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
160#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
Heiko Schocher660a2e62013-09-06 05:21:24 +0200161#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
Heiko Schocher03efcb02013-08-05 16:00:38 +0200162#define CONFIG_SYS_NAND_5_ADDR_CYCLE
163#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
164#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
165#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
166#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x120000
167#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
168#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
169#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
170 CONFIG_SYS_NAND_U_BOOT_SIZE - \
171 CONFIG_SYS_MALLOC_LEN - \
172 GENERATED_GBL_DATA_SIZE)
173#define CONFIG_SYS_NAND_ECCPOS { \
Heiko Schocher660a2e62013-09-06 05:21:24 +0200174 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
175 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
176 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
177 54, 55, 56, 57, 58, 59, 60, 61, 62, 63}
Heiko Schocher03efcb02013-08-05 16:00:38 +0200178#define CONFIG_SYS_NAND_PAGE_COUNT 64
179#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
180#define CONFIG_SYS_NAND_ECCSIZE 512
181#define CONFIG_SYS_NAND_ECCBYTES 10
182#define CONFIG_SYS_NAND_OOBSIZE 64
183#define CONFIG_SPL_NAND_SUPPORT
184#define CONFIG_SPL_NAND_BASE
185#define CONFIG_SPL_NAND_DRIVERS
186#define CONFIG_SPL_NAND_ECC
187#define CONFIG_SPL_NAND_SIMPLE
188#define CONFIG_SPL_NAND_LOAD
189
190/*
191 * Network & Ethernet Configuration
192 */
193#ifdef CONFIG_DRIVER_TI_EMAC
194#define CONFIG_DRIVER_TI_EMAC_USE_RMII
195#define CONFIG_BOOTP_DEFAULT
196#define CONFIG_BOOTP_DNS
197#define CONFIG_BOOTP_DNS2
198#define CONFIG_BOOTP_SEND_HOSTNAME
199#define CONFIG_NET_RETRY_COUNT 10
200#endif
201
202/*
203 * U-Boot general configuration
204 */
205#define CONFIG_MISC_INIT_R
206#define CONFIG_BOARD_EARLY_INIT_F
207#define CONFIG_BOOTFILE "uImage" /* Boot file name */
Heiko Schocher03efcb02013-08-05 16:00:38 +0200208#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
209#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
210#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
211#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
212#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
213#define CONFIG_VERSION_VARIABLE
214#define CONFIG_AUTO_COMPLETE
215#define CONFIG_SYS_HUSH_PARSER
216#define CONFIG_CMDLINE_EDITING
217#define CONFIG_SYS_LONGHELP
218#define CONFIG_CRC32_VERIFY
219#define CONFIG_MX_CYCLIC
220
221/*
222 * Linux Information
223 */
224#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
225#define CONFIG_HWCONFIG /* enable hwconfig */
226#define CONFIG_CMDLINE_TAG
227#define CONFIG_REVISION_TAG
228#define CONFIG_SETUP_MEMORY_TAGS
Heiko Schocher660a2e62013-09-06 05:21:24 +0200229#define CONFIG_BOOTDELAY 2
Heiko Schocher03efcb02013-08-05 16:00:38 +0200230#define CONFIG_EXTRA_ENV_SETTINGS \
Heiko Schocher660a2e62013-09-06 05:21:24 +0200231 "defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \
232 "root=/dev/mtdblock5 rw noinitrd " \
233 "rootfstype=jffs2 noinitrd\0" \
Heiko Schocher03efcb02013-08-05 16:00:38 +0200234 "hwconfig=dsp:wake=yes\0" \
Heiko Schocher660a2e62013-09-06 05:21:24 +0200235 "bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \
236 "bootfile=uImage\0" \
Heiko Schocher03efcb02013-08-05 16:00:38 +0200237 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
Heiko Schocher660a2e62013-09-06 05:21:24 +0200238 "mtddevname=uboot-env\0" \
239 "mtddevnum=0\0" \
Heiko Schocher03efcb02013-08-05 16:00:38 +0200240 "mtdids=" MTDIDS_DEFAULT "\0" \
241 "mtdparts=" MTDPARTS_DEFAULT "\0" \
Heiko Schocher660a2e62013-09-06 05:21:24 +0200242 "u-boot=/tftpboot/ipam390/u-boot.ais\0" \
243 "upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \
244 "nand write c0000000 20000 ${filesize}\0" \
Heiko Schocher03efcb02013-08-05 16:00:38 +0200245 "setbootparms=nand read c0100000 200000 400000;" \
Heiko Schocher660a2e62013-09-06 05:21:24 +0200246 "run defbootargs addmtd;" \
Heiko Schocher03efcb02013-08-05 16:00:38 +0200247 "spl export atags c0100000;" \
248 "nand erase.part bootparms;" \
249 "nand write c0000100 180000 20000\0" \
250 "\0"
251
252/*
253 * U-Boot commands
254 */
Heiko Schocher03efcb02013-08-05 16:00:38 +0200255#define CONFIG_CMD_ENV
256#define CONFIG_CMD_ASKENV
257#define CONFIG_CMD_DHCP
258#define CONFIG_CMD_DIAG
259#define CONFIG_CMD_MII
260#define CONFIG_CMD_PING
261#define CONFIG_CMD_SAVES
Heiko Schocher03efcb02013-08-05 16:00:38 +0200262
263#ifdef CONFIG_CMD_BDI
264#define CONFIG_CLOCKS
265#endif
266
267#ifndef CONFIG_DRIVER_TI_EMAC
Heiko Schocher03efcb02013-08-05 16:00:38 +0200268#undef CONFIG_CMD_DHCP
269#undef CONFIG_CMD_MII
270#undef CONFIG_CMD_PING
271#endif
272
273#define CONFIG_CMD_NAND
274#define CONFIG_CMD_NAND_TRIMFFS
275
276#define CONFIG_CMD_MTDPARTS
277#define CONFIG_MTD_DEVICE
278#define CONFIG_MTD_PARTITIONS
279#define CONFIG_LZO
280#define CONFIG_RBTREE
281#define CONFIG_CMD_UBI
282#define CONFIG_CMD_UBIFS
283
284#define MTDIDS_NAME_STR "davinci_nand.0"
285#define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR
286#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
287 "128k(u-boot-env)," \
288 "1408k(u-boot)," \
289 "128k(bootparms)," \
290 "384k(factory-info)," \
291 "4M(kernel)," \
292 "-(rootfs)"
293
294/* defines for SPL */
Heiko Schocher03efcb02013-08-05 16:00:38 +0200295#define CONFIG_SPL_FRAMEWORK
296#define CONFIG_SPL_BOARD_INIT
297#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
298 CONFIG_SYS_MALLOC_LEN)
299#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
300#define CONFIG_SPL_SERIAL_SUPPORT
301#define CONFIG_SPL_LIBCOMMON_SUPPORT
302#define CONFIG_SPL_LIBGENERIC_SUPPORT
303#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-ipam390.lds"
304#define CONFIG_SPL_STACK 0x8001ff00
305#define CONFIG_SPL_TEXT_BASE 0x80000000
306#define CONFIG_SPL_MAX_SIZE 0x20000
307#define CONFIG_SPL_MAX_FOOTPRINT 32768
308
309/* additions for new relocation code, must added to all boards */
310#define CONFIG_SYS_SDRAM_BASE 0xc0000000
311
312#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
313 GENERATED_GBL_DATA_SIZE)
314
315/* add FALCON boot mode */
316#define CONFIG_CMD_SPL
317#define CONFIG_SPL_OS_BOOT
318#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
319#define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR
320#define CONFIG_CMD_SPL_NAND_OFS 0x00180000
321#define CONFIG_CMD_SPL_WRITE_SIZE 0x400
322
323/* GPIO support */
324#define CONFIG_SPL_GPIO_SUPPORT
325#define CONFIG_DA8XX_GPIO
326#define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14)
327
328#define CONFIG_SHOW_BOOT_PROGRESS
329#define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11)
330#define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12)
331
332#endif /* __CONFIG_H */