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Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00001/*
2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
3 *
Tom Rini0b179982013-07-24 09:34:30 -04004 * SPDX-License-Identifier: GPL-2.0
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00005 */
6
Paul Burton7a9d1092013-11-09 10:22:08 +00007#ifndef _MALTA_CONFIG_H
8#define _MALTA_CONFIG_H
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00009
10#include <asm/addrspace.h>
11#include <asm/malta.h>
12
13/*
14 * System configuration
15 */
Paul Burton7a9d1092013-11-09 10:22:08 +000016#define CONFIG_MALTA
Paul Burton5f978d72014-04-07 10:11:23 +010017#define CONFIG_BOARD_EARLY_INIT_F
18#define CONFIG_DISPLAY_BOARDINFO
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000019
Gabor Juhosab413052013-10-24 14:32:00 +020020#define CONFIG_MEMSIZE_IN_BYTES
21
Gabor Juhosfeaa6062013-05-22 03:57:42 +000022#define CONFIG_PCI
23#define CONFIG_PCI_GT64120
Paul Burtonbaf37f02013-11-08 11:18:50 +000024#define CONFIG_PCI_MSC01
Gabor Juhosfeaa6062013-05-22 03:57:42 +000025#define CONFIG_PCI_PNP
Gabor Juhosf1957492013-05-22 03:57:44 +000026#define CONFIG_PCNET
Paul Burtone0878af2013-11-08 11:18:52 +000027#define CONFIG_PCNET_79C973
28#define PCNET_HAS_PROM
Gabor Juhosfeaa6062013-05-22 03:57:42 +000029
Paul Burton3ced12a2013-11-08 11:18:55 +000030#define CONFIG_MISC_INIT_R
31#define CONFIG_RTC_MC146818
32#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
33
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000034/*
35 * CPU Configuration
36 */
37#define CONFIG_SYS_MHZ 250 /* arbitrary value */
38#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000039
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000040/*
41 * Memory map
42 */
Gabor Juhos10473d02013-11-12 16:47:32 +010043#define CONFIG_SYS_TEXT_BASE 0xbe000000 /* Rom version */
44#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000045
46#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
47#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024)
48
49#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
50
51#define CONFIG_SYS_LOAD_ADDR 0x81000000
52#define CONFIG_SYS_MEMTEST_START 0x80100000
53#define CONFIG_SYS_MEMTEST_END 0x80800000
54
55#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
56#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
Paul Burton67d47522013-11-26 17:45:28 +000057#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000058
59/*
60 * Console configuration
61 */
Nikita Kiryanov181bd9d2015-08-03 12:36:58 +030062#undef CONFIG_SYS_PROMPT
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000063#if defined(CONFIG_SYS_LITTLE_ENDIAN)
Paul Burton7a9d1092013-11-09 10:22:08 +000064#define CONFIG_SYS_PROMPT "maltael # "
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000065#else
Paul Burton7a9d1092013-11-09 10:22:08 +000066#define CONFIG_SYS_PROMPT "malta # "
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000067#endif
68
69#define CONFIG_SYS_CBSIZE 256
70#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
71 sizeof(CONFIG_SYS_PROMPT) + 16)
72#define CONFIG_SYS_MAXARGS 16
73
Paul Burtona3bdaac2015-01-29 10:38:22 +000074#define CONFIG_SYS_HUSH_PARSER
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000075#define CONFIG_AUTO_COMPLETE
76#define CONFIG_CMDLINE_EDITING
77
78/*
79 * Serial driver
80 */
81#define CONFIG_BAUDRATE 115200
82
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000083#define CONFIG_SYS_NS16550_SERIAL
84#define CONFIG_SYS_NS16550_REG_SIZE 1
Paul Burton72117da2013-11-26 17:45:26 +000085#define CONFIG_SYS_NS16550_CLK (115200 * 16)
Paul Burtonbaf37f02013-11-08 11:18:50 +000086#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_GT_UART0_BASE)
87#define CONFIG_SYS_NS16550_COM2 CKSEG1ADDR(MALTA_MSC01_UART0_BASE)
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000088#define CONFIG_CONS_INDEX 1
89
90/*
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000091 * Flash configuration
92 */
Gabor Juhos52caee02013-05-22 03:57:39 +000093#define CONFIG_SYS_FLASH_BASE (KSEG1 | MALTA_FLASH_BASE)
94#define CONFIG_SYS_MAX_FLASH_BANKS 1
95#define CONFIG_SYS_MAX_FLASH_SECT 128
96#define CONFIG_SYS_FLASH_CFI
97#define CONFIG_FLASH_CFI_DRIVER
98#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000099
100/*
Paul Burtonfba6f452013-11-08 11:18:56 +0000101 * Environment
102 */
103#define CONFIG_ENV_IS_IN_FLASH
104#define CONFIG_ENV_SECT_SIZE 0x20000
105#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
106#define CONFIG_ENV_ADDR \
107 (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
108
109/*
Paul Burtonba21a452015-01-29 10:38:20 +0000110 * IDE/ATA
111 */
112#define CONFIG_SYS_IDE_MAXBUS 1
113#define CONFIG_SYS_IDE_MAXDEVICE 2
114#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS
115#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0
116#define CONFIG_SYS_ATA_DATA_OFFSET 0
117#define CONFIG_SYS_ATA_REG_OFFSET 0
118
119/*
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +0000120 * Commands
121 */
Paul Burton3ced12a2013-11-08 11:18:55 +0000122#define CONFIG_CMD_DATE
Paul Burtone0878af2013-11-08 11:18:52 +0000123#define CONFIG_CMD_DHCP
Paul Burtonba21a452015-01-29 10:38:20 +0000124#define CONFIG_CMD_IDE
Gabor Juhosfeaa6062013-05-22 03:57:42 +0000125#define CONFIG_CMD_PCI
Gabor Juhosf1957492013-05-22 03:57:44 +0000126#define CONFIG_CMD_PING
Gabor Juhosfeaa6062013-05-22 03:57:42 +0000127
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +0000128#define CONFIG_SYS_LONGHELP /* verbose help, undef to save memory */
129
Paul Burton7a9d1092013-11-09 10:22:08 +0000130#endif /* _MALTA_CONFIG_H */