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Stefano Babicdeb53482011-10-23 23:58:20 +00001/*
2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
3 *
4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
5 *
6 * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <asm/io.h>
29#include <asm/errno.h>
30#include <asm/arch/imx-regs.h>
31#include <asm/arch/crm_regs.h>
32#include <asm/arch/mx35_pins.h>
33#include <asm/arch/iomux.h>
34#include <i2c.h>
35#include <linux/types.h>
36#include <asm/gpio.h>
37#include <asm/arch/sys_proto.h>
38#include <netdev.h>
39
40#ifndef CONFIG_BOARD_EARLY_INIT_F
41#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
42#endif
43
44#define CCM_CCMR_CONFIG 0x003F4208
45
46#define ESDCTL_DDR2_CONFIG 0x007FFC3F
47#define ESDCTL_0x92220000 0x92220000
48#define ESDCTL_0xA2220000 0xA2220000
49#define ESDCTL_0xB2220000 0xB2220000
50#define ESDCTL_0x82228080 0x82228080
51#define ESDCTL_DDR2_EMR2 0x04000000
52#define ESDCTL_DDR2_EMR3 0x06000000
53#define ESDCTL_PRECHARGE 0x00000400
54#define ESDCTL_DDR2_EN_DLL 0x02000400
55#define ESDCTL_DDR2_RESET_DLL 0x00000333
56#define ESDCTL_DDR2_MR 0x00000233
57#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
58#define ESDCTL_DELAY_LINE5 0x00F49F00
59
60static inline void dram_wait(unsigned int count)
61{
62 volatile unsigned int wait = count;
63
64 while (wait--)
65 ;
66}
67
68DECLARE_GLOBAL_DATA_PTR;
69
70int dram_init(void)
71{
72 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
73 PHYS_SDRAM_1_SIZE);
74
75 return 0;
76}
77
78static void board_setup_sdram_bank(u32 start_address)
79
80{
81 struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
82 u32 *cfg_reg, *ctl_reg;
83 u32 val;
84
85 switch (start_address) {
86 case CSD0_BASE_ADDR:
87 cfg_reg = &esdc->esdcfg0;
88 ctl_reg = &esdc->esdctl0;
89 break;
90 case CSD1_BASE_ADDR:
91 cfg_reg = &esdc->esdcfg1;
92 ctl_reg = &esdc->esdctl1;
93 break;
94 default:
95 return;
96 }
97
98 /* Initialize MISC register for DDR2 */
99 val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
100 ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
101 writel(val, &esdc->esdmisc);
102 val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
103 writel(val, &esdc->esdmisc);
104
105 /*
106 * according to DDR2 specs, wait a while before
107 * the PRECHARGE_ALL command
108 */
109 dram_wait(0x20000);
110
111 /* Load DDR2 config and timing */
112 writel(ESDCTL_DDR2_CONFIG, cfg_reg);
113
114 /* Precharge ALL */
115 writel(ESDCTL_0x92220000,
116 ctl_reg);
117 writel(0xda, start_address + ESDCTL_PRECHARGE);
118
119 /* Load mode */
120 writel(ESDCTL_0xB2220000,
121 ctl_reg);
122 writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
123 writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
124 writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
125 writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
126
127 /* Precharge ALL */
128 writel(ESDCTL_0x92220000,
129 ctl_reg);
130 writel(0xda, start_address + ESDCTL_PRECHARGE);
131
132 /* Set mode auto refresh : at least two refresh are required */
133 writel(ESDCTL_0xA2220000,
134 ctl_reg);
135 writel(0xda, start_address);
136 writel(0xda, start_address);
137
138 writel(ESDCTL_0xB2220000,
139 ctl_reg);
140 writeb(0xda, start_address + ESDCTL_DDR2_MR);
141 writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
142
143 /* OCD mode exit */
144 writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
145
146 /* Set normal mode */
147 writel(ESDCTL_0x82228080,
148 ctl_reg);
149
150 dram_wait(0x20000);
151
152 /* Do not set delay lines, only for MDDR */
153}
154
155static void board_setup_sdram(void)
156{
157 struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
158
159 /* Initialize with default values both CSD0/1 */
160 writel(0x2000, &esdc->esdctl0);
161 writel(0x2000, &esdc->esdctl1);
162
Stefano Babicfda241d2011-11-25 09:08:36 +0100163 board_setup_sdram_bank(CSD0_BASE_ADDR);
Stefano Babicdeb53482011-10-23 23:58:20 +0000164}
165
166static void setup_iomux_uart3(void)
167{
168 mxc_request_iomux(MX35_PIN_RTS2_UART3_RXD_MUX, MUX_CONFIG_ALT7);
169 mxc_request_iomux(MX35_PIN_CTS2_UART3_TXD_MUX, MUX_CONFIG_ALT7);
170}
171
172static void setup_iomux_i2c(void)
173{
174 int pad;
175
176 mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
177 mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
178
179 pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
180 | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
181
182 mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
183 mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
184
185 mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1);
186 mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1);
187
188 mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad);
189 mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad);
190}
191
192
193static void setup_iomux_spi(void)
194{
195 mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
196 mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
197 mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
198 mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
199 mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
200}
201
202static void setup_iomux_fec(void)
203{
204 /* setup pins for FEC */
205 mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
206 mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
207 mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
208 mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
209 mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
210 mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
211 mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
212 mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
213 mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
214 mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
215 mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
216 mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
217 mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
218 mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
219 mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
220 mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
221 mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
222 mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
223
224}
225
226int board_early_init_f(void)
227{
228 struct ccm_regs *ccm =
229 (struct ccm_regs *)IMX_CCM_BASE;
230
231 /* setup GPIO3_1 to set HighVCore signal */
Stefano Babicfda241d2011-11-25 09:08:36 +0100232 mxc_request_iomux(MX35_PIN_ATA_DA1, MUX_CONFIG_ALT5);
Stefano Babicdeb53482011-10-23 23:58:20 +0000233 gpio_direction_output(65, 1);
234
235 /* initialize PLL and clock configuration */
236 writel(CCM_CCMR_CONFIG, &ccm->ccmr);
237
238 writel(CCM_MPLL_532_HZ, &ccm->mpctl);
239 writel(CCM_PPLL_300_HZ, &ccm->ppctl);
240
241 /* Set the core to run at 532 Mhz */
242 writel(0x00001000, &ccm->pdr0);
243
244 /* Set-up RAM */
245 board_setup_sdram();
246
247 /* enable clocks */
248 writel(readl(&ccm->cgr0) |
249 MXC_CCM_CGR0_EMI_MASK |
250 MXC_CCM_CGR0_EDI0_MASK |
251 MXC_CCM_CGR0_EPIT1_MASK,
252 &ccm->cgr0);
253
254 writel(readl(&ccm->cgr1) |
255 MXC_CCM_CGR1_FEC_MASK |
256 MXC_CCM_CGR1_GPIO1_MASK |
257 MXC_CCM_CGR1_GPIO2_MASK |
258 MXC_CCM_CGR1_GPIO3_MASK |
259 MXC_CCM_CGR1_I2C1_MASK |
260 MXC_CCM_CGR1_I2C2_MASK |
261 MXC_CCM_CGR1_I2C3_MASK,
262 &ccm->cgr1);
263
264 /* Set-up NAND */
265 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
266
267 /* Set pinmux for the required peripherals */
268 setup_iomux_uart3();
269 setup_iomux_i2c();
270 setup_iomux_fec();
271 setup_iomux_spi();
272
273 return 0;
274}
275
276int board_init(void)
277{
278 /* address of boot parameters */
279 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
280
281 return 0;
282}
283
284u32 get_board_rev(void)
285{
286 int rev = 0;
287
288 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
289}