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Niklaus Giger6e5de262007-07-27 11:30:33 +02001/*
Niklaus Giger74973122008-02-05 11:31:28 +01002 *(C) Copyright 2005-2008 Netstal Maschinen AG
Niklaus Giger6e5de262007-07-27 11:30:33 +02003 * Niklaus Giger (Niklaus.Giger@netstal.com)
4 *
5 * This source code is free software; you can redistribute it
6 * and/or modify it in source code form under the terms of the GNU
7 * General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
19 */
20
21#include <common.h>
22#include <ppc4xx.h>
23#include <asm/processor.h>
24#include <asm/io.h>
Peter Tyser61f2b382010-04-12 22:28:07 -050025#include <asm/u-boot.h>
Niklaus Giger055606b2008-01-16 18:39:20 +010026#include "../common/nm.h"
Niklaus Giger6e5de262007-07-27 11:30:33 +020027
28DECLARE_GLOBAL_DATA_PTR;
29
Stefan Roese35d22f92007-08-10 10:42:25 +020030#define HCU_MACH_VERSIONS_REGISTER (0x7C000000 + 0xF00000)
Niklaus Giger74973122008-02-05 11:31:28 +010031#define HCU_SLOT_ADDRESS (0x7C000000 + 0x400000)
32#define HCU_DIGITAL_IO_REGISTER (0x7C000000 + 0x500000)
Niklaus Giger055606b2008-01-16 18:39:20 +010033#define HCU_SW_INSTALL_REQUESTED 0x10
Stefan Roese35d22f92007-08-10 10:42:25 +020034
Niklaus Giger6e5de262007-07-27 11:30:33 +020035/*
36 * This function is run very early, out of flash, and before devices are
Peter Tyserea0364f2010-04-12 22:28:04 -050037 * initialized. It is called by arch/ppc/lib/board.c:board_init_f by virtue
Niklaus Giger6e5de262007-07-27 11:30:33 +020038 * of being in the init_sequence array.
39 *
40 * The SDRAM has been initialized already -- start.S:start called
41 * init.S:init_sdram early on -- but it is not yet being used for
42 * anything, not even stack. So be careful.
43 */
44
Niklaus Giger6e5de262007-07-27 11:30:33 +020045/* Attention: If you want 1 microsecs times from the external oscillator
Niklaus Giger74973122008-02-05 11:31:28 +010046 * 0x00004051 is okay for u-boot/linux, but different from old vxworks values
47 * 0x00804051 causes problems with u-boot and linux!
Niklaus Giger6e5de262007-07-27 11:30:33 +020048 */
Niklaus Giger055606b2008-01-16 18:39:20 +010049#define CPC0_CR0_VALUE 0x0030103c
Niklaus Giger6e5de262007-07-27 11:30:33 +020050#define CPC0_CR1_VALUE 0x00004051
Niklaus Giger6e5de262007-07-27 11:30:33 +020051
52int board_early_init_f (void)
53{
Niklaus Giger055606b2008-01-16 18:39:20 +010054 /*
55 * Interrupt controller setup for the HCU4 board.
56 * Note: IRQ 0-15 405GP internally generated; high; level sensitive
57 * IRQ 16 405GP internally generated; low; level sensitive
58 * IRQ 17-24 RESERVED/UNUSED
59 * IRQ 31 (EXT IRQ 6) (unused)
60 */
Stefan Roese952e7762009-09-24 09:55:50 +020061 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
62 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
63 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
64 mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
65 mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
66 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
Niklaus Giger6e5de262007-07-27 11:30:33 +020067
Niklaus Giger74973122008-02-05 11:31:28 +010068 mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
69 mtdcr(CPC0_ECR, 0x60606000);
70 mtdcr(CPC0_EIRR, 0x7C000000);
Niklaus Giger6e5de262007-07-27 11:30:33 +020071
72 return 0;
73}
74
75#ifdef CONFIG_BOARD_PRE_INIT
76int board_pre_init (void)
77{
78 return board_early_init_f ();
79}
Niklaus Giger6e5de262007-07-27 11:30:33 +020080#endif
81
Niklaus Giger055606b2008-01-16 18:39:20 +010082int sys_install_requested(void)
83{
Niklaus Giger74973122008-02-05 11:31:28 +010084 u16 ioValue = in_be16((u16 *)HCU_DIGITAL_IO_REGISTER);
85 return (ioValue & HCU_SW_INSTALL_REQUESTED) != 0;
Niklaus Giger055606b2008-01-16 18:39:20 +010086}
87
Niklaus Giger6e5de262007-07-27 11:30:33 +020088int checkboard (void)
89{
Niklaus Giger74973122008-02-05 11:31:28 +010090 u16 boardVersReg = in_be16((u16 *)HCU_MACH_VERSIONS_REGISTER);
91 u16 generation = boardVersReg & 0xf0;
92 u16 index = boardVersReg & 0x0f;
Stefan Roese35d22f92007-08-10 10:42:25 +020093
Niklaus Giger74973122008-02-05 11:31:28 +010094 /* Cannot be done in board_early_init */
Stefan Roesed1c3b272009-09-09 16:25:29 +020095 mtdcr(CPC0_CR0, CPC0_CR0_VALUE);
Niklaus Giger74973122008-02-05 11:31:28 +010096
Niklaus Giger6e5de262007-07-27 11:30:33 +020097 /* Force /RTS to active. The board it not wired quite
Niklaus Giger055606b2008-01-16 18:39:20 +010098 * correctly to use cts/rtc flow control, so just force the
99 * /RST active and forget about it.
100 */
Niklaus Giger6e5de262007-07-27 11:30:33 +0200101 writeb (readb (0xef600404) | 0x03, 0xef600404);
Niklaus Giger055606b2008-01-16 18:39:20 +0100102 nm_show_print(generation, index, 0);
Stefan Roese35d22f92007-08-10 10:42:25 +0200103
Niklaus Giger6e5de262007-07-27 11:30:33 +0200104 return 0;
105}
106
Niklaus Giger07bc2052007-08-16 15:16:03 +0200107u32 hcu_led_get(void)
Niklaus Giger6e5de262007-07-27 11:30:33 +0200108{
Niklaus Giger055606b2008-01-16 18:39:20 +0100109 return (~(in_be32((u32 *)GPIO0_OR)) >> 23) & 0xff;
Niklaus Giger6e5de262007-07-27 11:30:33 +0200110}
111
Niklaus Giger055606b2008-01-16 18:39:20 +0100112/*
Niklaus Giger07bc2052007-08-16 15:16:03 +0200113 * hcu_led_set value to be placed into the LEDs (max 6 bit)
Niklaus Giger055606b2008-01-16 18:39:20 +0100114 */
Niklaus Giger07bc2052007-08-16 15:16:03 +0200115void hcu_led_set(u32 value)
Niklaus Giger6e5de262007-07-27 11:30:33 +0200116{
117 u32 tmp = ~value;
Stefan Roese35d22f92007-08-10 10:42:25 +0200118
119 tmp = (tmp << 23) | 0x7FFFFF;
Niklaus Giger055606b2008-01-16 18:39:20 +0100120 out_be32((u32 *)GPIO0_OR, tmp);
Niklaus Giger6e5de262007-07-27 11:30:33 +0200121}
122
123/*
Niklaus Giger055606b2008-01-16 18:39:20 +0100124 * hcu_get_slot
125 */
126u32 hcu_get_slot(void)
Niklaus Giger6e5de262007-07-27 11:30:33 +0200127{
Niklaus Giger74973122008-02-05 11:31:28 +0100128 u16 slot = in_be16((u16 *)HCU_SLOT_ADDRESS);
129 return slot & 0x7f;
Niklaus Giger6e5de262007-07-27 11:30:33 +0200130}
Niklaus Giger6e5de262007-07-27 11:30:33 +0200131
Niklaus Giger6e5de262007-07-27 11:30:33 +0200132/*
Niklaus Giger055606b2008-01-16 18:39:20 +0100133 * get_serial_number
Niklaus Giger6e5de262007-07-27 11:30:33 +0200134 */
Niklaus Giger055606b2008-01-16 18:39:20 +0100135u32 get_serial_number(void)
Niklaus Giger6e5de262007-07-27 11:30:33 +0200136{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137 u32 serial = in_be32((u32 *)CONFIG_SYS_FLASH_BASE);
Stefan Roese35d22f92007-08-10 10:42:25 +0200138
Niklaus Giger74973122008-02-05 11:31:28 +0100139 if (serial == 0xffffffff)
Niklaus Giger055606b2008-01-16 18:39:20 +0100140 return 0;
Stefan Roese35d22f92007-08-10 10:42:25 +0200141
Niklaus Giger74973122008-02-05 11:31:28 +0100142 return serial;
Niklaus Giger6e5de262007-07-27 11:30:33 +0200143}
144
145
Niklaus Giger055606b2008-01-16 18:39:20 +0100146/*
Niklaus Giger6e5de262007-07-27 11:30:33 +0200147 * misc_init_r.
Niklaus Giger055606b2008-01-16 18:39:20 +0100148 */
Niklaus Giger6e5de262007-07-27 11:30:33 +0200149
150int misc_init_r(void)
151{
Niklaus Giger055606b2008-01-16 18:39:20 +0100152 common_misc_init_r();
153 set_params_for_sw_install( sys_install_requested(), "hcu4" );
Niklaus Giger6e5de262007-07-27 11:30:33 +0200154 return 0;
155}
156
Becky Bruce9973e3c2008-06-09 16:03:40 -0500157phys_size_t initdram(int board_type)
Niklaus Giger6e5de262007-07-27 11:30:33 +0200158{
159 long dram_size = 0;
Niklaus Giger74973122008-02-05 11:31:28 +0100160 u16 boardVersReg = in_be16((u16 *)HCU_MACH_VERSIONS_REGISTER);
161 u16 generation = boardVersReg & 0xf0;
162 u16 index = boardVersReg & 0x0f;
163
164 if (generation == HW_GENERATION_HCU3 && index < 0xf)
165 dram_size = 32 << 20; /* 32 MB - RAM */
166 else
167 dram_size = 64 << 20; /* 64 MB - RAM */
168 init_ppc405_sdram(dram_size);
Niklaus Giger6e5de262007-07-27 11:30:33 +0200169
170#ifdef DEBUG
171 show_sdram_registers();
172#endif
173
Niklaus Giger6e5de262007-07-27 11:30:33 +0200174 return dram_size;
175}
Niklaus Giger055606b2008-01-16 18:39:20 +0100176
Niklaus Giger055606b2008-01-16 18:39:20 +0100177#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
178void ft_board_setup(void *blob, bd_t *bd)
179{
180 ft_cpu_setup(blob, bd);
181
182}
183#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
Niklaus Gigera0794942008-02-25 18:37:01 +0100184
185/*
186 * Hardcoded flash setup:
187 * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
188 */
189ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
190{
191 if (banknum == 0) { /* non-CFI boot flash */
192 info->portwidth = 1;
193 info->chipwidth = 1;
194 info->interface = FLASH_CFI_X8;
195 return 1;
196 } else
197 return 0;
198}