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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * Cirrus Logic CS8900A Ethernet
3 *
Ben Warrenb1c0eaa2009-08-25 13:09:37 -07004 * (C) 2009 Ben Warren , biggerbadderben@gmail.com
5 * Converted to use CONFIG_NET_MULTI API
6 *
wdenk6069ff22003-02-28 00:49:47 +00007 * (C) 2003 Wolfgang Denk, wd@denx.de
8 * Extension to synchronize ethaddr environment variable
9 * against value in EEPROM
10 *
wdenkc6097192002-11-03 00:24:07 +000011 * (C) Copyright 2002
12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13 * Marius Groeger <mgroeger@sysgo.de>
14 *
15 * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
16 *
wdenkc6097192002-11-03 00:24:07 +000017 * This program is loaded into SRAM in bootstrap mode, where it waits
18 * for commands on UART1 to read and write memory, jump to code etc.
19 * A design goal for this program is to be entirely independent of the
20 * target board. Anything with a CL-PS7111 or EP7211 should be able to run
21 * this code in bootstrap mode. All the board specifics can be handled on
22 * the host.
23 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020024 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +000025 */
26
27#include <common.h>
28#include <command.h>
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070029#include <asm/io.h>
wdenkc6097192002-11-03 00:24:07 +000030#include <net.h>
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070031#include <malloc.h>
32#include "cs8900.h"
wdenkc6097192002-11-03 00:24:07 +000033
wdenka2663ea2003-12-07 18:32:37 +000034#undef DEBUG
wdenkc6097192002-11-03 00:24:07 +000035
36/* packet page register access functions */
37
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070038#ifdef CONFIG_CS8900_BUS32
39
40#define REG_WRITE(v, a) writel((v),(a))
41#define REG_READ(a) readl((a))
42
wdenkc6097192002-11-03 00:24:07 +000043/* we don't need 16 bit initialisation on 32 bit bus */
Ben Warren830c7b62009-11-09 11:43:18 -080044#define get_reg_init_bus(r,d) get_reg((r),(d))
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070045
wdenkc6097192002-11-03 00:24:07 +000046#else
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070047
48#define REG_WRITE(v, a) writew((v),(a))
49#define REG_READ(a) readw((a))
50
51static u16 get_reg_init_bus(struct eth_device *dev, int regno)
wdenkc6097192002-11-03 00:24:07 +000052{
wdenk6069ff22003-02-28 00:49:47 +000053 /* force 16 bit busmode */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070054 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
55 uint8_t volatile * const iob = (uint8_t volatile * const)dev->iobase;
wdenkc6097192002-11-03 00:24:07 +000056
Anatolij Gustschinda227352011-11-19 13:12:14 +000057 readb(iob);
58 readb(iob + 1);
59 readb(iob);
60 readb(iob + 1);
61 readb(iob);
wdenk6069ff22003-02-28 00:49:47 +000062
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070063 REG_WRITE(regno, &priv->regs->pptr);
64 return REG_READ(&priv->regs->pdata);
wdenkc6097192002-11-03 00:24:07 +000065}
66#endif
67
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070068static u16 get_reg(struct eth_device *dev, int regno)
wdenkc6097192002-11-03 00:24:07 +000069{
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070070 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
71 REG_WRITE(regno, &priv->regs->pptr);
72 return REG_READ(&priv->regs->pdata);
wdenkc6097192002-11-03 00:24:07 +000073}
74
75
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070076static void put_reg(struct eth_device *dev, int regno, u16 val)
wdenkc6097192002-11-03 00:24:07 +000077{
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070078 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
79 REG_WRITE(regno, &priv->regs->pptr);
80 REG_WRITE(val, &priv->regs->pdata);
wdenkc6097192002-11-03 00:24:07 +000081}
82
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070083static void cs8900_reset(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +000084{
wdenk6069ff22003-02-28 00:49:47 +000085 int tmo;
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070086 u16 us;
wdenkc6097192002-11-03 00:24:07 +000087
wdenk6069ff22003-02-28 00:49:47 +000088 /* reset NIC */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070089 put_reg(dev, PP_SelfCTL, get_reg(dev, PP_SelfCTL) | PP_SelfCTL_Reset);
wdenkc6097192002-11-03 00:24:07 +000090
wdenk6069ff22003-02-28 00:49:47 +000091 /* wait for 200ms */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070092 udelay(200000);
wdenk6069ff22003-02-28 00:49:47 +000093 /* Wait until the chip is reset */
wdenkc6097192002-11-03 00:24:07 +000094
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070095 tmo = get_timer(0) + 1 * CONFIG_SYS_HZ;
96 while ((((us = get_reg_init_bus(dev, PP_SelfSTAT)) &
97 PP_SelfSTAT_InitD) == 0) && tmo < get_timer(0))
wdenk6069ff22003-02-28 00:49:47 +000098 /*NOP*/;
wdenkc6097192002-11-03 00:24:07 +000099}
100
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700101static void cs8900_reginit(struct eth_device *dev)
wdenka2663ea2003-12-07 18:32:37 +0000102{
103 /* receive only error free packets addressed to this card */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700104 put_reg(dev, PP_RxCTL,
105 PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
wdenka2663ea2003-12-07 18:32:37 +0000106 /* do not generate any interrupts on receive operations */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700107 put_reg(dev, PP_RxCFG, 0);
wdenka2663ea2003-12-07 18:32:37 +0000108 /* do not generate any interrupts on transmit operations */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700109 put_reg(dev, PP_TxCFG, 0);
wdenka2663ea2003-12-07 18:32:37 +0000110 /* do not generate any interrupts on buffer operations */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700111 put_reg(dev, PP_BufCFG, 0);
wdenka2663ea2003-12-07 18:32:37 +0000112 /* enable transmitter/receiver mode */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700113 put_reg(dev, PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
wdenka2663ea2003-12-07 18:32:37 +0000114}
115
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700116void cs8900_get_enetaddr(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000117{
wdenk6069ff22003-02-28 00:49:47 +0000118 int i;
wdenk6069ff22003-02-28 00:49:47 +0000119
120 /* verify chip id */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700121 if (get_reg_init_bus(dev, PP_ChipID) != 0x630e)
wdenk6069ff22003-02-28 00:49:47 +0000122 return;
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700123 cs8900_reset(dev);
124 if ((get_reg(dev, PP_SelfSTAT) &
125 (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
126 (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {
wdenk6069ff22003-02-28 00:49:47 +0000127
128 /* Load the MAC from EEPROM */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700129 for (i = 0; i < 3; i++) {
130 u32 Addr;
wdenk6069ff22003-02-28 00:49:47 +0000131
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700132 Addr = get_reg(dev, PP_IA + i * 2);
133 dev->enetaddr[i * 2] = Addr & 0xFF;
134 dev->enetaddr[i * 2 + 1] = Addr >> 8;
wdenk6069ff22003-02-28 00:49:47 +0000135 }
wdenk6069ff22003-02-28 00:49:47 +0000136 }
wdenkc6097192002-11-03 00:24:07 +0000137}
138
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700139void cs8900_halt(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000140{
wdenk6069ff22003-02-28 00:49:47 +0000141 /* disable transmitter/receiver mode */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700142 put_reg(dev, PP_LineCTL, 0);
wdenkc6097192002-11-03 00:24:07 +0000143
wdenk6069ff22003-02-28 00:49:47 +0000144 /* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700145 get_reg_init_bus(dev, PP_ChipID);
wdenkc6097192002-11-03 00:24:07 +0000146}
147
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700148static int cs8900_init(struct eth_device *dev, bd_t * bd)
wdenkc6097192002-11-03 00:24:07 +0000149{
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700150 uchar *enetaddr = dev->enetaddr;
151 u16 id;
Mike Frysinger0a5238c2009-02-11 19:06:09 -0500152
wdenk6069ff22003-02-28 00:49:47 +0000153 /* verify chip id */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700154 id = get_reg_init_bus(dev, PP_ChipID);
155 if (id != 0x630e) {
156 printf ("CS8900 Ethernet chip not found: "
157 "ID=0x%04x instead 0x%04x\n", id, 0x630e);
158 return 1;
wdenk6069ff22003-02-28 00:49:47 +0000159 }
160
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700161 cs8900_reset (dev);
wdenk6069ff22003-02-28 00:49:47 +0000162 /* set the ethernet address */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700163 put_reg(dev, PP_IA + 0, enetaddr[0] | (enetaddr[1] << 8));
164 put_reg(dev, PP_IA + 2, enetaddr[2] | (enetaddr[3] << 8));
165 put_reg(dev, PP_IA + 4, enetaddr[4] | (enetaddr[5] << 8));
wdenk6069ff22003-02-28 00:49:47 +0000166
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700167 cs8900_reginit(dev);
wdenkc6097192002-11-03 00:24:07 +0000168 return 0;
wdenkc6097192002-11-03 00:24:07 +0000169}
170
171/* Get a data block via Ethernet */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700172static int cs8900_recv(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000173{
wdenk6069ff22003-02-28 00:49:47 +0000174 int i;
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700175 u16 rxlen;
176 u16 *addr;
177 u16 status;
wdenkc6097192002-11-03 00:24:07 +0000178
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700179 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
180
181 status = get_reg(dev, PP_RER);
wdenkc6097192002-11-03 00:24:07 +0000182
wdenk6069ff22003-02-28 00:49:47 +0000183 if ((status & PP_RER_RxOK) == 0)
184 return 0;
wdenkc6097192002-11-03 00:24:07 +0000185
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700186 status = REG_READ(&priv->regs->rtdata);
187 rxlen = REG_READ(&priv->regs->rtdata);
wdenkc6097192002-11-03 00:24:07 +0000188
wdenk6069ff22003-02-28 00:49:47 +0000189 if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700190 debug("packet too big!\n");
191 for (addr = (u16 *) NetRxPackets[0], i = rxlen >> 1; i > 0;
wdenk6069ff22003-02-28 00:49:47 +0000192 i--)
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700193 *addr++ = REG_READ(&priv->regs->rtdata);
wdenk6069ff22003-02-28 00:49:47 +0000194 if (rxlen & 1)
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700195 *addr++ = REG_READ(&priv->regs->rtdata);
wdenkc6097192002-11-03 00:24:07 +0000196
wdenk6069ff22003-02-28 00:49:47 +0000197 /* Pass the packet up to the protocol layers. */
198 NetReceive (NetRxPackets[0], rxlen);
wdenk6069ff22003-02-28 00:49:47 +0000199 return rxlen;
wdenkc6097192002-11-03 00:24:07 +0000200}
201
202/* Send a data block via Ethernet. */
Joe Hershberger9d295172012-05-21 14:45:21 +0000203static int cs8900_send(struct eth_device *dev, void *packet, int length)
wdenkc6097192002-11-03 00:24:07 +0000204{
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700205 volatile u16 *addr;
wdenk6069ff22003-02-28 00:49:47 +0000206 int tmo;
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700207 u16 s;
208 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
wdenkc6097192002-11-03 00:24:07 +0000209
210retry:
wdenk6069ff22003-02-28 00:49:47 +0000211 /* initiate a transmit sequence */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700212 REG_WRITE(PP_TxCmd_TxStart_Full, &priv->regs->txcmd);
213 REG_WRITE(length, &priv->regs->txlen);
wdenkc6097192002-11-03 00:24:07 +0000214
wdenk6069ff22003-02-28 00:49:47 +0000215 /* Test to see if the chip has allocated memory for the packet */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700216 if ((get_reg(dev, PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
wdenk6069ff22003-02-28 00:49:47 +0000217 /* Oops... this should not happen! */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700218 debug("cs: unable to send packet; retrying...\n");
219 for (tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
220 get_timer(0) < tmo;)
wdenk6069ff22003-02-28 00:49:47 +0000221 /*NOP*/;
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700222 cs8900_reset(dev);
223 cs8900_reginit(dev);
wdenk6069ff22003-02-28 00:49:47 +0000224 goto retry;
225 }
wdenkc6097192002-11-03 00:24:07 +0000226
wdenk6069ff22003-02-28 00:49:47 +0000227 /* Write the contents of the packet */
228 /* assume even number of bytes */
229 for (addr = packet; length > 0; length -= 2)
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700230 REG_WRITE(*addr++, &priv->regs->rtdata);
wdenkc6097192002-11-03 00:24:07 +0000231
wdenk6069ff22003-02-28 00:49:47 +0000232 /* wait for transfer to succeed */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700233 tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
234 while ((s = get_reg(dev, PP_TER) & ~0x1F) == 0) {
235 if (get_timer(0) >= tmo)
wdenk6069ff22003-02-28 00:49:47 +0000236 break;
237 }
wdenkc6097192002-11-03 00:24:07 +0000238
wdenk6069ff22003-02-28 00:49:47 +0000239 /* nothing */ ;
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700240 if((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) {
241 debug("\ntransmission error %#x\n", s);
wdenk6069ff22003-02-28 00:49:47 +0000242 }
wdenkc6097192002-11-03 00:24:07 +0000243
wdenk6069ff22003-02-28 00:49:47 +0000244 return 0;
wdenkc6097192002-11-03 00:24:07 +0000245}
246
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700247static void cs8900_e2prom_ready(struct eth_device *dev)
wdenk1cb8e982003-03-06 21:55:29 +0000248{
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700249 while (get_reg(dev, PP_SelfSTAT) & SI_BUSY)
Guennadi Liakhovetski13e0b8f2008-04-03 13:36:18 +0200250 ;
wdenk1cb8e982003-03-06 21:55:29 +0000251}
252
253/***********************************************************/
254/* read a 16-bit word out of the EEPROM */
255/***********************************************************/
256
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700257int cs8900_e2prom_read(struct eth_device *dev,
258 u8 addr, u16 *value)
wdenk1cb8e982003-03-06 21:55:29 +0000259{
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700260 cs8900_e2prom_ready(dev);
261 put_reg(dev, PP_EECMD, EEPROM_READ_CMD | addr);
262 cs8900_e2prom_ready(dev);
263 *value = get_reg(dev, PP_EEData);
wdenk1cb8e982003-03-06 21:55:29 +0000264
265 return 0;
266}
267
268
269/***********************************************************/
270/* write a 16-bit word into the EEPROM */
271/***********************************************************/
272
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700273int cs8900_e2prom_write(struct eth_device *dev, u8 addr, u16 value)
wdenk1cb8e982003-03-06 21:55:29 +0000274{
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700275 cs8900_e2prom_ready(dev);
276 put_reg(dev, PP_EECMD, EEPROM_WRITE_EN);
277 cs8900_e2prom_ready(dev);
278 put_reg(dev, PP_EEData, value);
279 put_reg(dev, PP_EECMD, EEPROM_WRITE_CMD | addr);
280 cs8900_e2prom_ready(dev);
281 put_reg(dev, PP_EECMD, EEPROM_WRITE_DIS);
282 cs8900_e2prom_ready(dev);
wdenk1cb8e982003-03-06 21:55:29 +0000283
wdenk06d01db2003-03-14 20:47:52 +0000284 return 0;
wdenk1cb8e982003-03-06 21:55:29 +0000285}
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700286
287int cs8900_initialize(u8 dev_num, int base_addr)
288{
289 struct eth_device *dev;
290 struct cs8900_priv *priv;
291
292 dev = malloc(sizeof(*dev));
293 if (!dev) {
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700294 return 0;
295 }
296 memset(dev, 0, sizeof(*dev));
297
298 priv = malloc(sizeof(*priv));
299 if (!priv) {
Matthias Kaehlcke07c96602010-01-21 22:16:34 +0100300 free(dev);
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700301 return 0;
302 }
303 memset(priv, 0, sizeof(*priv));
304 priv->regs = (struct cs8900_regs *)base_addr;
305
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700306 dev->iobase = base_addr;
307 dev->priv = priv;
308 dev->init = cs8900_init;
309 dev->halt = cs8900_halt;
310 dev->send = cs8900_send;
311 dev->recv = cs8900_recv;
Hui.Tang497ab0e2009-11-05 09:58:44 +0800312
313 /* Load MAC address from EEPROM */
314 cs8900_get_enetaddr(dev);
315
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700316 sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);
317
318 eth_register(dev);
319 return 0;
320}