blob: 51d56662c6f76d897a0c90c9d66e3873d63166ea [file] [log] [blame]
Alison Wang427eba72013-05-27 22:55:45 +00001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 */
19
20#include <common.h>
21#include <watchdog.h>
22#include <asm/io.h>
23#include <serial.h>
24#include <linux/compiler.h>
25#include <asm/arch/imx-regs.h>
26#include <asm/arch/clock.h>
27
28#define US1_TDRE (1 << 7)
29#define US1_RDRF (1 << 5)
30#define UC2_TE (1 << 3)
31#define UC2_RE (1 << 2)
32
33DECLARE_GLOBAL_DATA_PTR;
34
35struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
36
37static void lpuart_serial_setbrg(void)
38{
39 u32 clk = mxc_get_clock(MXC_UART_CLK);
40 u16 sbr;
41
42 if (!gd->baudrate)
43 gd->baudrate = CONFIG_BAUDRATE;
44
45 sbr = (u16)(clk / (16 * gd->baudrate));
46 /* place adjustment later - n/32 BRFA */
47
48 __raw_writeb(sbr >> 8, &base->ubdh);
49 __raw_writeb(sbr & 0xff, &base->ubdl);
50}
51
52static int lpuart_serial_getc(void)
53{
54 u8 status;
55
56 while (!(__raw_readb(&base->us1) & US1_RDRF))
57 WATCHDOG_RESET();
58
59 status = __raw_readb(&base->us1);
60 status |= US1_RDRF;
61 __raw_writeb(status, &base->us1);
62
63 return __raw_readb(&base->ud);
64}
65
66static void lpuart_serial_putc(const char c)
67{
68 if (c == '\n')
69 serial_putc('\r');
70
71 while (!(__raw_readb(&base->us1) & US1_TDRE))
72 WATCHDOG_RESET();
73
74 __raw_writeb(c, &base->ud);
75}
76
77/*
78 * Test whether a character is in the RX buffer
79 */
80static int lpuart_serial_tstc(void)
81{
82 if (__raw_readb(&base->urcfifo) == 0)
83 return 0;
84
85 return 1;
86}
87
88/*
89 * Initialise the serial port with the given baudrate. The settings
90 * are always 8 data bits, no parity, 1 stop bit, no start bits.
91 */
92static int lpuart_serial_init(void)
93{
94 u8 ctrl;
95
96 ctrl = __raw_readb(&base->uc2);
97 ctrl &= ~UC2_RE;
98 ctrl &= ~UC2_TE;
99 __raw_writeb(ctrl, &base->uc2);
100
101 __raw_writeb(0, &base->umodem);
102 __raw_writeb(0, &base->uc1);
103
104 /* provide data bits, parity, stop bit, etc */
105
106 serial_setbrg();
107
108 __raw_writeb(UC2_RE | UC2_TE, &base->uc2);
109
110 return 0;
111}
112
113static struct serial_device lpuart_serial_drv = {
114 .name = "lpuart_serial",
115 .start = lpuart_serial_init,
116 .stop = NULL,
117 .setbrg = lpuart_serial_setbrg,
118 .putc = lpuart_serial_putc,
119 .puts = default_serial_puts,
120 .getc = lpuart_serial_getc,
121 .tstc = lpuart_serial_tstc,
122};
123
124void lpuart_serial_initialize(void)
125{
126 serial_register(&lpuart_serial_drv);
127}
128
129__weak struct serial_device *default_serial_console(void)
130{
131 return &lpuart_serial_drv;
132}