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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 6213a68fe8da8be772e12def2302eb2bef85e1c9 / . / drivers / net / fm / memac_phy.c
blob: ea6118b9b9953ed9fede92f71ef500d1750bf687 [file] [log] [blame]
Roy Zang111fd192012-10-08 07:44:21 +0000[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Andy Fleming <afleming@freescale.com>
4 * Roy Zang <tie-fei.zang@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 * Some part is taken from tsec.c
21 */
22#include <common.h>
23#include <miiphy.h>
24#include <phy.h>
25#include <asm/io.h>
26#include <asm/fsl_memac.h>
27#include <fm_eth.h>
28
29/*
30 * Write value to the PHY for this device to the register at regnum, waiting
31 * until the write is done before it returns. All PHY configuration has to be
32 * done through the TSEC1 MIIM regs
33 */
34int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
35 int regnum, u16 value)
36{
37 u32 mdio_ctl;
38 struct memac_mdio_controller *regs = bus->priv;
39 u32 c45 = 1; /* Default to 10G interface */
40
41 if (dev_addr == MDIO_DEVAD_NONE) {
42 c45 = 0; /* clause 22 */
43 dev_addr = regnum & 0x1f;
44 clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
45 } else {
46 setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
47 setbits_be32(&regs->mdio_stat, MDIO_STAT_HOLD_15_CLK);
48 }
49
50 /* Wait till the bus is free */
51 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
52 ;
53
54 /* Set the port and dev addr */
55 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
56 out_be32(&regs->mdio_ctl, mdio_ctl);
57
58 /* Set the register address */
59 if (c45)
60 out_be32(&regs->mdio_addr, regnum & 0xffff);
61
62 /* Wait till the bus is free */
63 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
64 ;
65
66 /* Write the value to the register */
67 out_be32(&regs->mdio_data, MDIO_DATA(value));
68
69 /* Wait till the MDIO write is complete */
70 while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY)
71 ;
72
73 return 0;
74}
75
76/*
77 * Reads from register regnum in the PHY for device dev, returning the value.
78 * Clears miimcom first. All PHY configuration has to be done through the
79 * TSEC1 MIIM regs
80 */
81int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
82 int regnum)
83{
84 u32 mdio_ctl;
85 struct memac_mdio_controller *regs = bus->priv;
86 u32 c45 = 1;
87
88 if (dev_addr == MDIO_DEVAD_NONE) {
89 c45 = 0; /* clause 22 */
90 dev_addr = regnum & 0x1f;
91 clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
92 } else {
93 setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
94 setbits_be32(&regs->mdio_stat, MDIO_STAT_HOLD_15_CLK);
95 }
96
97 /* Wait till the bus is free */
98 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
99 ;
100
101 /* Set the Port and Device Addrs */
102 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
103 out_be32(&regs->mdio_ctl, mdio_ctl);
104
105 /* Set the register address */
106 if (c45)
107 out_be32(&regs->mdio_addr, regnum & 0xffff);
108
109 /* Wait till the bus is free */
110 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
111 ;
112
113 /* Initiate the read */
114 mdio_ctl |= MDIO_CTL_READ;
115 out_be32(&regs->mdio_ctl, mdio_ctl);
116
117 /* Wait till the MDIO write is complete */
118 while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY)
119 ;
120
121 /* Return all Fs if nothing was there */
122 if (in_be32(&regs->mdio_stat) & MDIO_STAT_RD_ER)
123 return 0xffff;
124
125 return in_be32(&regs->mdio_data) & 0xffff;
126}
127
128int memac_mdio_reset(struct mii_dev *bus)
129{
130 return 0;
131}
132
133int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
134{
135 struct mii_dev *bus = mdio_alloc();
136
137 if (!bus) {
138 printf("Failed to allocate FM TGEC MDIO bus\n");
139 return -1;
140 }
141
142 bus->read = memac_mdio_read;
143 bus->write = memac_mdio_write;
144 bus->reset = memac_mdio_reset;
145 sprintf(bus->name, info->name);
146
147 bus->priv = info->regs;
148
149 return mdio_register(bus);
150}