David Wu | e7ae4cf | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * (C) Copyright 2019 Rockchip Electronics Co., Ltd |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <dm.h> |
| 8 | #include <dm/pinctrl.h> |
| 9 | #include <regmap.h> |
| 10 | #include <syscon.h> |
| 11 | |
| 12 | #include "pinctrl-rockchip.h" |
| 13 | |
| 14 | static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { |
| 15 | { |
| 16 | .num = 1, |
| 17 | .pin = 0, |
| 18 | .reg = 0x418, |
| 19 | .bit = 0, |
| 20 | .mask = 0x3 |
| 21 | }, { |
| 22 | .num = 1, |
| 23 | .pin = 1, |
| 24 | .reg = 0x418, |
| 25 | .bit = 2, |
| 26 | .mask = 0x3 |
| 27 | }, { |
| 28 | .num = 1, |
| 29 | .pin = 2, |
| 30 | .reg = 0x418, |
| 31 | .bit = 4, |
| 32 | .mask = 0x3 |
| 33 | }, { |
| 34 | .num = 1, |
| 35 | .pin = 3, |
| 36 | .reg = 0x418, |
| 37 | .bit = 6, |
| 38 | .mask = 0x3 |
| 39 | }, { |
| 40 | .num = 1, |
| 41 | .pin = 4, |
| 42 | .reg = 0x418, |
| 43 | .bit = 8, |
| 44 | .mask = 0x3 |
| 45 | }, { |
| 46 | .num = 1, |
| 47 | .pin = 5, |
| 48 | .reg = 0x418, |
| 49 | .bit = 10, |
| 50 | .mask = 0x3 |
| 51 | }, { |
| 52 | .num = 1, |
| 53 | .pin = 6, |
| 54 | .reg = 0x418, |
| 55 | .bit = 12, |
| 56 | .mask = 0x3 |
| 57 | }, { |
| 58 | .num = 1, |
| 59 | .pin = 7, |
| 60 | .reg = 0x418, |
| 61 | .bit = 14, |
| 62 | .mask = 0x3 |
| 63 | }, { |
| 64 | .num = 1, |
| 65 | .pin = 8, |
| 66 | .reg = 0x41c, |
| 67 | .bit = 0, |
| 68 | .mask = 0x3 |
| 69 | }, { |
| 70 | .num = 1, |
| 71 | .pin = 9, |
| 72 | .reg = 0x41c, |
| 73 | .bit = 2, |
| 74 | .mask = 0x3 |
| 75 | }, |
| 76 | }; |
| 77 | |
David Wu | 54e7570 | 2019-04-16 21:50:55 +0800 | [diff] [blame] | 78 | static int rv1108_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) |
| 79 | { |
| 80 | struct rockchip_pinctrl_priv *priv = bank->priv; |
| 81 | int iomux_num = (pin / 8); |
| 82 | struct regmap *regmap; |
| 83 | int reg, ret, mask, mux_type; |
| 84 | u8 bit; |
| 85 | u32 data; |
| 86 | |
| 87 | regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) |
| 88 | ? priv->regmap_pmu : priv->regmap_base; |
| 89 | |
| 90 | /* get basic quadrupel of mux registers and the correct reg inside */ |
| 91 | mux_type = bank->iomux[iomux_num].type; |
| 92 | reg = bank->iomux[iomux_num].offset; |
| 93 | reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); |
| 94 | |
| 95 | if (bank->recalced_mask & BIT(pin)) |
| 96 | rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); |
| 97 | |
| 98 | data = (mask << (bit + 16)); |
| 99 | data |= (mux & mask) << bit; |
| 100 | ret = regmap_write(regmap, reg, data); |
| 101 | |
| 102 | return ret; |
| 103 | } |
| 104 | |
David Wu | e7ae4cf | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 105 | #define RV1108_PULL_PMU_OFFSET 0x10 |
| 106 | #define RV1108_PULL_OFFSET 0x110 |
| 107 | |
| 108 | static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, |
| 109 | int pin_num, struct regmap **regmap, |
| 110 | int *reg, u8 *bit) |
| 111 | { |
| 112 | struct rockchip_pinctrl_priv *priv = bank->priv; |
| 113 | |
| 114 | /* The first 24 pins of the first bank are located in PMU */ |
| 115 | if (bank->bank_num == 0) { |
| 116 | *regmap = priv->regmap_pmu; |
| 117 | *reg = RV1108_PULL_PMU_OFFSET; |
| 118 | } else { |
| 119 | *reg = RV1108_PULL_OFFSET; |
| 120 | *regmap = priv->regmap_base; |
| 121 | /* correct the offset, as we're starting with the 2nd bank */ |
| 122 | *reg -= 0x10; |
| 123 | *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; |
| 124 | } |
| 125 | |
| 126 | *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); |
| 127 | *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); |
| 128 | *bit *= ROCKCHIP_PULL_BITS_PER_PIN; |
| 129 | } |
| 130 | |
| 131 | #define RV1108_DRV_PMU_OFFSET 0x20 |
| 132 | #define RV1108_DRV_GRF_OFFSET 0x210 |
| 133 | |
| 134 | static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, |
| 135 | int pin_num, struct regmap **regmap, |
| 136 | int *reg, u8 *bit) |
| 137 | { |
| 138 | struct rockchip_pinctrl_priv *priv = bank->priv; |
| 139 | |
| 140 | /* The first 24 pins of the first bank are located in PMU */ |
| 141 | if (bank->bank_num == 0) { |
| 142 | *regmap = priv->regmap_pmu; |
| 143 | *reg = RV1108_DRV_PMU_OFFSET; |
| 144 | } else { |
| 145 | *regmap = priv->regmap_base; |
| 146 | *reg = RV1108_DRV_GRF_OFFSET; |
| 147 | |
| 148 | /* correct the offset, as we're starting with the 2nd bank */ |
| 149 | *reg -= 0x10; |
| 150 | *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; |
| 151 | } |
| 152 | |
| 153 | *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); |
| 154 | *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG; |
| 155 | *bit *= ROCKCHIP_DRV_BITS_PER_PIN; |
| 156 | } |
| 157 | |
David Wu | 625ab11 | 2019-04-16 21:55:26 +0800 | [diff] [blame^] | 158 | static int rv1108_set_drive(struct rockchip_pin_bank *bank, |
| 159 | int pin_num, int strength) |
| 160 | { |
| 161 | struct regmap *regmap; |
| 162 | int reg, ret; |
| 163 | u32 data; |
| 164 | u8 bit; |
| 165 | int type = bank->drv[pin_num / 8].drv_type; |
| 166 | |
| 167 | rv1108_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); |
| 168 | ret = rockchip_translate_drive_value(type, strength); |
| 169 | if (ret < 0) { |
| 170 | debug("unsupported driver strength %d\n", strength); |
| 171 | return ret; |
| 172 | } |
| 173 | |
| 174 | /* enable the write to the equivalent lower bits */ |
| 175 | data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); |
| 176 | |
| 177 | data |= (ret << bit); |
| 178 | ret = regmap_write(regmap, reg, data); |
| 179 | return ret; |
| 180 | } |
| 181 | |
David Wu | e7ae4cf | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 182 | #define RV1108_SCHMITT_PMU_OFFSET 0x30 |
| 183 | #define RV1108_SCHMITT_GRF_OFFSET 0x388 |
| 184 | #define RV1108_SCHMITT_BANK_STRIDE 8 |
| 185 | #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 |
| 186 | #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 |
| 187 | |
| 188 | static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, |
| 189 | int pin_num, |
| 190 | struct regmap **regmap, |
| 191 | int *reg, u8 *bit) |
| 192 | { |
| 193 | struct rockchip_pinctrl_priv *priv = bank->priv; |
| 194 | int pins_per_reg; |
| 195 | |
| 196 | if (bank->bank_num == 0) { |
| 197 | *regmap = priv->regmap_pmu; |
| 198 | *reg = RV1108_SCHMITT_PMU_OFFSET; |
| 199 | pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; |
| 200 | } else { |
| 201 | *regmap = priv->regmap_base; |
| 202 | *reg = RV1108_SCHMITT_GRF_OFFSET; |
| 203 | pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; |
| 204 | *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; |
| 205 | } |
| 206 | *reg += ((pin_num / pins_per_reg) * 4); |
| 207 | *bit = pin_num % pins_per_reg; |
| 208 | |
| 209 | return 0; |
| 210 | } |
| 211 | |
| 212 | static struct rockchip_pin_bank rv1108_pin_banks[] = { |
| 213 | PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, |
| 214 | IOMUX_SOURCE_PMU, |
| 215 | IOMUX_SOURCE_PMU, |
| 216 | IOMUX_SOURCE_PMU), |
| 217 | PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), |
| 218 | PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), |
| 219 | PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), |
| 220 | }; |
| 221 | |
| 222 | static struct rockchip_pin_ctrl rv1108_pin_ctrl = { |
| 223 | .pin_banks = rv1108_pin_banks, |
| 224 | .nr_banks = ARRAY_SIZE(rv1108_pin_banks), |
| 225 | .label = "RV1108-GPIO", |
| 226 | .type = RV1108, |
| 227 | .grf_mux_offset = 0x10, |
| 228 | .pmu_mux_offset = 0x0, |
| 229 | .iomux_recalced = rv1108_mux_recalced_data, |
| 230 | .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), |
David Wu | 54e7570 | 2019-04-16 21:50:55 +0800 | [diff] [blame] | 231 | .set_mux = rv1108_set_mux, |
David Wu | e7ae4cf | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 232 | .pull_calc_reg = rv1108_calc_pull_reg_and_bit, |
David Wu | 625ab11 | 2019-04-16 21:55:26 +0800 | [diff] [blame^] | 233 | .set_drive = rv1108_set_drive, |
David Wu | e7ae4cf | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 234 | .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, |
| 235 | }; |
| 236 | |
| 237 | static const struct udevice_id rv1108_pinctrl_ids[] = { |
| 238 | { |
| 239 | .compatible = "rockchip,rv1108-pinctrl", |
| 240 | .data = (ulong)&rv1108_pin_ctrl |
| 241 | }, |
| 242 | { } |
| 243 | }; |
| 244 | |
| 245 | U_BOOT_DRIVER(pinctrl_rv1108) = { |
| 246 | .name = "pinctrl_rv1108", |
| 247 | .id = UCLASS_PINCTRL, |
| 248 | .of_match = rv1108_pinctrl_ids, |
| 249 | .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), |
| 250 | .ops = &rockchip_pinctrl_ops, |
| 251 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
| 252 | .bind = dm_scan_fdt_dev, |
| 253 | #endif |
| 254 | .probe = rockchip_pinctrl_probe, |
| 255 | }; |