blob: 326a5533b78ca2afb8862fc1bfe0337322b8b17b [file] [log] [blame]
dillon minf132c492021-04-09 15:28:44 +08001// SPDX-License-Identifier: GPL-2.0+
2
3#include <stm32h7-u-boot.dtsi>
4
5&fmc {
6 /*
7 * Memory configuration from sdram datasheet W9825G6KH
8 * first bank is bank@0
9 * second bank is bank@1
10 */
11 bank1: bank@0 {
12 st,sdram-control = /bits/ 8 <NO_COL_9
13 NO_ROW_13
14 MWIDTH_16
15 BANKS_4
16 CAS_2
17 SDCLK_3
18 RD_BURST_EN
19 RD_PIPE_DL_0>;
20 st,sdram-timing = /bits/ 8 <TMRD_2
21 TXSR_6
22 TRAS_6
23 TRC_6
24 TRP_2
25 TWR_2
26 TRCD_2>;
27 st,sdram-refcount = <677>;
28 };
29};
30
31&pinctrl {
32 fmc_pins: fmc@0 {
33 pins {
34 pinmux = <STM32_PINMUX('D', 0, AF12)>,
35 <STM32_PINMUX('D', 1, AF12)>,
36 <STM32_PINMUX('D', 8, AF12)>,
37 <STM32_PINMUX('D', 9, AF12)>,
38 <STM32_PINMUX('D',10, AF12)>,
39 <STM32_PINMUX('D',14, AF12)>,
40 <STM32_PINMUX('D',15, AF12)>,
41
42 <STM32_PINMUX('E', 0, AF12)>,
43 <STM32_PINMUX('E', 1, AF12)>,
44 <STM32_PINMUX('E', 7, AF12)>,
45 <STM32_PINMUX('E', 8, AF12)>,
46 <STM32_PINMUX('E', 9, AF12)>,
47 <STM32_PINMUX('E',10, AF12)>,
48 <STM32_PINMUX('E',11, AF12)>,
49 <STM32_PINMUX('E',12, AF12)>,
50 <STM32_PINMUX('E',13, AF12)>,
51 <STM32_PINMUX('E',14, AF12)>,
52 <STM32_PINMUX('E',15, AF12)>,
53
54 <STM32_PINMUX('F', 0, AF12)>,
55 <STM32_PINMUX('F', 1, AF12)>,
56 <STM32_PINMUX('F', 2, AF12)>,
57 <STM32_PINMUX('F', 3, AF12)>,
58 <STM32_PINMUX('F', 4, AF12)>,
59 <STM32_PINMUX('F', 5, AF12)>,
60 <STM32_PINMUX('F',11, AF12)>,
61 <STM32_PINMUX('F',12, AF12)>,
62 <STM32_PINMUX('F',13, AF12)>,
63 <STM32_PINMUX('F',14, AF12)>,
64 <STM32_PINMUX('F',15, AF12)>,
65
66 <STM32_PINMUX('G', 0, AF12)>,
67 <STM32_PINMUX('G', 1, AF12)>,
68 <STM32_PINMUX('G', 2, AF12)>,
69 <STM32_PINMUX('G', 4, AF12)>,
70 <STM32_PINMUX('G', 5, AF12)>,
71 <STM32_PINMUX('G', 8, AF12)>,
72 <STM32_PINMUX('G',15, AF12)>,
73
74 <STM32_PINMUX('H', 5, AF12)>,
75 <STM32_PINMUX('C', 2, AF12)>,
76 <STM32_PINMUX('C', 3, AF12)>;
77
78 slew-rate = <3>;
79 };
80 };
81};