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maxims@google.comf6a6a9f2017-01-18 13:44:57 -08001/*
2 * Copyright (C) 2012-2020 ASPEED Technology Inc.
3 * Ryan Chen <ryan_chen@aspeedtech.com>
4 *
5 * Copyright 2016 IBM Corporation
6 * (C) Copyright 2016 Google, Inc
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#ifndef __AST_COMMON_CONFIG_H
12#define __AST_COMMON_CONFIG_H
13
14/* Misc CPU related */
15#define CONFIG_CMDLINE_TAG
16#define CONFIG_SETUP_MEMORY_TAGS
17#define CONFIG_INITRD_TAG
18
19#define CONFIG_CMDLINE_EDITING
20
21/* Enable cache controller */
22#define CONFIG_SYS_DCACHE_OFF
23
24#define CONFIG_SYS_SDRAM_BASE 0x80000000
25
26#ifdef CONFIG_PRE_CON_BUF_SZ
27#define CONFIG_SYS_INIT_RAM_ADDR (0x1e720000 + CONFIG_PRE_CON_BUF_SZ)
28#define CONFIG_SYS_INIT_RAM_SIZE (36*1024 - CONFIG_PRE_CON_BUF_SZ)
29#else
30#define CONFIG_SYS_INIT_RAM_ADDR (0x1e720000)
31#define CONFIG_SYS_INIT_RAM_SIZE (36*1024)
32#endif
33
34#define SYS_INIT_RAM_END (CONFIG_SYS_INIT_RAM_ADDR \
35 + CONFIG_SYS_INIT_RAM_SIZE)
36#define CONFIG_SYS_INIT_SP_ADDR (SYS_INIT_RAM_END \
37 - GENERATED_GBL_DATA_SIZE)
38
39#define CONFIG_NR_DRAM_BANKS 1
40
41#define CONFIG_SYS_MALLOC_LEN (32 << 20)
42
43/*
44 * NS16550 Configuration
45 */
maxims@google.comf6a6a9f2017-01-18 13:44:57 -080046
47/*
48 * BOOTP options
49 */
50#define CONFIG_BOOTP_BOOTFILESIZE
51#define CONFIG_BOOTP_BOOTPATH
52#define CONFIG_BOOTP_GATEWAY
53#define CONFIG_BOOTP_HOSTNAME
54#define CONFIG_BOOTP_SUBNETMASK
55
56/*
57 * Miscellaneous configurable options
58 */
59#define CONFIG_SYS_LONGHELP
60#define CONFIG_SYS_CBSIZE 256
61
62/* Print Buffer Size */
63#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
64 + sizeof(CONFIG_SYS_PROMPT) + 16)
65#define CONFIG_SYS_MAXARGS 16
66#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
67
68#define CONFIG_BOOTARGS \
69 "console=ttyS4,115200n8" \
70 " root=/dev/ram rw"
71
72#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
73#define CONFIG_ENV_OVERWRITE
74
75#define CONFIG_EXTRA_ENV_SETTINGS \
76 "verify=yes\0" \
77 "spi_dma=yes\0" \
78 ""
79
80#endif /* __AST_COMMON_CONFIG_H */