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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Rick Chen8bbb2902017-12-26 13:55:49 +08002/*
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
Rick Chen8bbb2902017-12-26 13:55:49 +08005 */
6
7#include <common.h>
8
9void flush_dcache_range(unsigned long start, unsigned long end)
10{
11}
12
13void invalidate_icache_range(unsigned long start, unsigned long end)
14{
Lukas Auer62a09ad2018-11-22 11:26:23 +010015 /*
16 * RISC-V does not have an instruction for invalidating parts of the
17 * instruction cache. Invalidate all of it instead.
18 */
19 invalidate_icache_all();
20}
21
22void invalidate_icache_all(void)
23{
24 asm volatile ("fence.i" ::: "memory");
Rick Chen8bbb2902017-12-26 13:55:49 +080025}
26
27void invalidate_dcache_range(unsigned long start, unsigned long end)
28{
29}
30
31void flush_cache(unsigned long addr, unsigned long size)
32{
33}
34
35void icache_enable(void)
36{
37}
38
39void icache_disable(void)
40{
41}
42
43int icache_status(void)
44{
45 return 0;
46}
47
48void dcache_enable(void)
49{
50}
51
52void dcache_disable(void)
53{
54}
55
56int dcache_status(void)
57{
58 return 0;
59}