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Tapani Utriainen550e3752013-12-04 09:27:33 +01001/*
2 * Configuration settings for the TechNexion TAO-3530 SOM
3 * equipped on Thunder baseboard.
4 *
5 * Edward Lin <linuxfae@technexion.com>
6 * Tapani Utriainen <linuxfae@technexion.com>
7 *
Stefan Roesea9f52492013-12-04 09:27:34 +01008 * Copyright (C) 2013 Stefan Roese <sr@denx.de>
9 *
Tapani Utriainen550e3752013-12-04 09:27:33 +010010 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
Albert ARIBAUD37098442016-01-27 08:46:11 +010016#define CONFIG_SYS_CACHELINE_SIZE 64
17
Tapani Utriainen550e3752013-12-04 09:27:33 +010018/*
19 * High Level Configuration Options
20 */
Tapani Utriainen550e3752013-12-04 09:27:33 +010021#define CONFIG_OMAP /* in a TI OMAP core */
Tapani Utriainen550e3752013-12-04 09:27:33 +010022
23#define CONFIG_OMAP_GPIO
24#define CONFIG_OMAP_COMMON
Nishanth Menonc6f90e12015-03-09 17:12:08 -050025/* Common ARM Erratas */
26#define CONFIG_ARM_ERRATA_454179
27#define CONFIG_ARM_ERRATA_430973
28#define CONFIG_ARM_ERRATA_621766
Tapani Utriainen550e3752013-12-04 09:27:33 +010029
30#define MACH_TYPE_OMAP3_TAO3530 2836
31
32#define CONFIG_SDRC /* Has an SDRC controller */
33
34#include <asm/arch/cpu.h> /* get chip and board defs */
Nishanth Menon987ec582015-03-09 17:12:04 -050035#include <asm/arch/omap.h>
Tapani Utriainen550e3752013-12-04 09:27:33 +010036
37/*
38 * Display CPU and Board information
39 */
40#define CONFIG_DISPLAY_CPUINFO
41#define CONFIG_DISPLAY_BOARDINFO
42
43/* Clock Defines */
44#define V_OSCK 26000000 /* Clock output from T2 */
45#define V_SCLK (V_OSCK >> 1)
46
47#define CONFIG_MISC_INIT_R
48
49#define CONFIG_OF_LIBFDT
50
51#define CONFIG_CMDLINE_TAG
52#define CONFIG_SETUP_MEMORY_TAGS
53#define CONFIG_INITRD_TAG
54#define CONFIG_REVISION_TAG
55
56/*
57 * Size of malloc() pool
58 */
59#define CONFIG_SYS_MALLOC_LEN (4 << 20)
60#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
61
62/*
63 * Hardware drivers
64 */
65
66/*
67 * NS16550 Configuration
68 */
69#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
70
Tapani Utriainen550e3752013-12-04 09:27:33 +010071#define CONFIG_SYS_NS16550_SERIAL
72#define CONFIG_SYS_NS16550_REG_SIZE (-4)
73#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
74
75/*
76 * select serial console configuration
77 */
78#define CONFIG_CONS_INDEX 3
79#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
80
81/* allow to overwrite serial and ethaddr */
82#define CONFIG_ENV_OVERWRITE
83#define CONFIG_BAUDRATE 115200
84#define CONFIG_GENERIC_MMC
85#define CONFIG_MMC
86#define CONFIG_OMAP_HSMMC
87#define CONFIG_DOS_PARTITION
88
Stefan Roese36481de2014-02-14 09:47:17 +010089/* GPIO banks */
90#define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */
91#define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */
92#define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */
93#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
94#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
95
Tapani Utriainen550e3752013-12-04 09:27:33 +010096/* commands to include */
Tapani Utriainen550e3752013-12-04 09:27:33 +010097#define CONFIG_CMD_CACHE
98#define CONFIG_CMD_EXT2 /* EXT2 Support */
99#define CONFIG_CMD_FAT /* FAT support */
100#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
101#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
102#define MTDIDS_DEFAULT "nand0=nand"
103#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
104 "1920k(u-boot),128k(u-boot-env),"\
105 "4m(kernel),-(fs)"
106
107#define CONFIG_CMD_I2C /* I2C serial bus support */
108#define CONFIG_CMD_MMC /* MMC support */
109#define CONFIG_CMD_NAND /* NAND support */
110#define CONFIG_CMD_DHCP
111#define CONFIG_CMD_PING
112
Tapani Utriainen550e3752013-12-04 09:27:33 +0100113#define CONFIG_SYS_NO_FLASH
114#define CONFIG_SYS_I2C
115#define CONFIG_SYS_I2C_OMAP34XX
116#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
117#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
118#define CONFIG_I2C_MULTI_BUS
119
120/*
121 * TWL4030
122 */
123#define CONFIG_TWL4030_POWER
124#define CONFIG_TWL4030_LED
125
126/*
127 * Board NAND Info.
128 */
Tapani Utriainen550e3752013-12-04 09:27:33 +0100129#define CONFIG_NAND_OMAP_GPMC
130#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
131 /* to access nand */
132#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
133 /* to access nand at */
134 /* CS0 */
Tapani Utriainen550e3752013-12-04 09:27:33 +0100135
136#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
137 /* devices */
Stefano Babic55f1b392015-07-26 15:18:15 +0200138#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
Tapani Utriainen550e3752013-12-04 09:27:33 +0100139/* Environment information */
140#define CONFIG_BOOTDELAY 3
141
142#define CONFIG_EXTRA_ENV_SETTINGS \
143 "loadaddr=0x82000000\0" \
144 "console=ttyO2,115200n8\0" \
145 "mpurate=600\0" \
146 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
147 "tv_mode=omapfb.mode=tv:ntsc\0" \
148 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
149 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
150 "extra_options= \0" \
Tapani Utriainen550e3752013-12-04 09:27:33 +0100151 "mmcdev=0\0" \
152 "mmcroot=/dev/mmcblk0p2 rw\0" \
153 "mmcrootfstype=ext3 rootwait\0" \
154 "nandroot=ubi0:rootfs ubi.mtd=4\0" \
155 "nandrootfstype=ubifs\0" \
156 "mmcargs=setenv bootargs console=${console} " \
Tapani Utriainen550e3752013-12-04 09:27:33 +0100157 "mpurate=${mpurate} " \
158 "${video_mode} " \
159 "root=${mmcroot} " \
160 "rootfstype=${mmcrootfstype} " \
161 "${extra_options}\0" \
162 "nandargs=setenv bootargs console=${console} " \
Tapani Utriainen550e3752013-12-04 09:27:33 +0100163 "mpurate=${mpurate} " \
164 "${video_mode} " \
165 "${network_setting} " \
166 "root=${nandroot} " \
167 "rootfstype=${nandrootfstype} "\
168 "${extra_options}\0" \
169 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
170 "bootscript=echo Running bootscript from mmc ...; " \
171 "source ${loadaddr}\0" \
172 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
173 "mmcboot=echo Booting from mmc ...; " \
174 "run mmcargs; " \
175 "bootm ${loadaddr}\0" \
176 "nandboot=echo Booting from nand ...; " \
177 "run nandargs; " \
178 "nand read ${loadaddr} 280000 400000; " \
179 "bootm ${loadaddr}\0" \
180
181#define CONFIG_BOOTCOMMAND \
182 "if mmc rescan ${mmcdev}; then " \
183 "if run loadbootscript; then " \
184 "run bootscript; " \
185 "else " \
186 "if run loaduimage; then " \
187 "run mmcboot; " \
188 "else run nandboot; " \
189 "fi; " \
190 "fi; " \
191 "else run nandboot; fi"
192
193/*
194 * Miscellaneous configurable options
195 */
196#define CONFIG_SYS_LONGHELP /* undef to save memory */
197#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Tapani Utriainen550e3752013-12-04 09:27:33 +0100198#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
199
200/* turn on command-line edit/hist/auto */
201#define CONFIG_CMDLINE_EDITING
202#define CONFIG_COMMAND_HISTORY
203#define CONFIG_AUTO_COMPLETE
204
205/* Print Buffer Size */
206#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
207 sizeof(CONFIG_SYS_PROMPT) + 16)
208#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
209/* Boot Argument Buffer Size */
210#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
211
212#define CONFIG_SYS_ALT_MEMTEST 1
213#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
214 /* defaults */
215#define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */
216#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
217
218#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
219 /* load address */
220#define CONFIG_SYS_TEXT_BASE 0x80008000
221
222/*
223 * OMAP3 has 12 GP timers, they can be driven by the system clock
224 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
225 * This rate is divided by a local divisor.
226 */
227#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
228#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
229
230/*
231 * Stack sizes
232 *
233 * The stack sizes are set up in start.S using the settings below
234 */
235#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
236
237/*
238 * Physical Memory Map
239 */
240#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
241#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
242#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
243#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
244
245/*
246 * FLASH and environment organization
247 */
248
249/* **** PISMO SUPPORT *** */
Tapani Utriainen550e3752013-12-04 09:27:33 +0100250#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
pekon gupta222a3112014-07-18 17:59:41 +0530251#define CONFIG_SYS_FLASH_BASE NAND_BASE
Tapani Utriainen550e3752013-12-04 09:27:33 +0100252
253/* Monitor at start of flash */
254#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
255#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
256
257#define CONFIG_ENV_IS_IN_NAND 1
258#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
259#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
260
261#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
262#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
263#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
264
265#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
266#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
267#define CONFIG_SYS_INIT_RAM_SIZE 0x800
268#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
269 CONFIG_SYS_INIT_RAM_SIZE - \
270 GENERATED_GBL_DATA_SIZE)
271
272#define CONFIG_OMAP3_SPI
273
274/*
275 * USB
276 *
277 * Currently only EHCI is enabled, the MUSB OTG controller
278 * is not enabled.
279 */
280
281/* USB EHCI */
282#define CONFIG_CMD_USB
283#define CONFIG_USB_EHCI
284#define CONFIG_USB_EHCI_OMAP
285#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162
286
287#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
288#define CONFIG_USB_HOST_ETHER
289#define CONFIG_USB_ETHER_SMSC95XX
290
291#define CONFIG_USB_ETHER
292#define CONFIG_USB_ETHER_RNDIS
293#define CONFIG_USB_STORAGE
294#define CONGIG_CMD_STORAGE
295
Stefan Roesea9f52492013-12-04 09:27:34 +0100296/* Defines for SPL */
Stefan Roesea9f52492013-12-04 09:27:34 +0100297#define CONFIG_SPL_FRAMEWORK
298#define CONFIG_SPL_NAND_SIMPLE
299
300#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
301#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
Paul Kocialkowskie2ccdf82014-11-08 23:14:55 +0100302#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
Guillaume GARDET205b4f32014-10-15 17:53:11 +0200303#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Stefan Roesea9f52492013-12-04 09:27:34 +0100304
305#define CONFIG_SPL_BOARD_INIT
306#define CONFIG_SPL_LIBCOMMON_SUPPORT
307#define CONFIG_SPL_LIBDISK_SUPPORT
308#define CONFIG_SPL_I2C_SUPPORT
309#define CONFIG_SPL_LIBGENERIC_SUPPORT
310#define CONFIG_SPL_MMC_SUPPORT
311#define CONFIG_SPL_FAT_SUPPORT
312#define CONFIG_SPL_SERIAL_SUPPORT
313#define CONFIG_SPL_NAND_SUPPORT
314#define CONFIG_SPL_NAND_BASE
315#define CONFIG_SPL_NAND_DRIVERS
316#define CONFIG_SPL_NAND_ECC
317#define CONFIG_SPL_GPIO_SUPPORT
318#define CONFIG_SPL_POWER_SUPPORT
319#define CONFIG_SPL_OMAP3_ID_NAND
320#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
321
322/* NAND boot config */
323#define CONFIG_SYS_NAND_5_ADDR_CYCLE
324#define CONFIG_SYS_NAND_PAGE_COUNT 64
325#define CONFIG_SYS_NAND_PAGE_SIZE 2048
326#define CONFIG_SYS_NAND_OOBSIZE 64
327#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
328#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
329/*
330 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
331 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
332 */
333#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
334 10, 11, 12, 13 }
335#define CONFIG_SYS_NAND_ECCSIZE 512
336#define CONFIG_SYS_NAND_ECCBYTES 3
337#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
338
339#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
340#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
341
342#define CONFIG_SPL_TEXT_BASE 0x40200800
343#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
Stefan Roesea9f52492013-12-04 09:27:34 +0100344
345/*
346 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
347 * older x-loader implementations. And move the BSS area so that it
348 * doesn't overlap with TEXT_BASE.
349 */
350#define CONFIG_SYS_TEXT_BASE 0x80008000
351#define CONFIG_SPL_BSS_START_ADDR 0x80100000
352#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
353
354#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
355#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
356
Tapani Utriainen550e3752013-12-04 09:27:33 +0100357#endif /* __CONFIG_H */