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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 62e92077a8936e60087d55683538ee386cc673aa / . / arch / x86 / dts / chromebook_link.dts
blob: f27263a54749acf3c17dceb9b684f56632e560ee [file] [log] [blame]
Simon Glass2712f082012-12-03 13:56:51 +0000[diff] [blame]1/dts-v1/;
2
Bin Meng120c4162014-12-24 13:06:39 +0800[diff] [blame]3/include/ "skeleton.dtsi"
Bin Meng9ca5a0c2014-12-24 13:06:38 +0800[diff] [blame]4/include/ "serial.dtsi"
Bin Meng93f8a312015-07-15 16:23:39 +0800[diff] [blame]5/include/ "rtc.dtsi"
Simon Glass2712f082012-12-03 13:56:51 +0000[diff] [blame]6
7/ {
Simon Glass2712f082012-12-03 13:56:51 +0000[diff] [blame]8 model = "Google Link";
9 compatible = "google,link", "intel,celeron-ivybridge";
10
Simon Glassa9aff2f2015-01-19 22:16:13 -0700[diff] [blame]11 aliases {
Simon Glass90b16d12015-03-26 09:29:29 -0600[diff] [blame]12 spi0 = "/pci/pch/spi";
Simon Glassa9aff2f2015-01-19 22:16:13 -0700[diff] [blame]13 };
14
Simon Glass2712f082012-12-03 13:56:51 +0000[diff] [blame]15 config {
16 silent_console = <0>;
17 };
18
Simon Glassd1259c92014-10-10 07:49:19 -0600[diff] [blame]19 gpioa {
20 compatible = "intel,ich6-gpio";
Simon Glass437c2b72014-11-12 22:42:25 -0700[diff] [blame]21 u-boot,dm-pre-reloc;
Simon Glassd1259c92014-10-10 07:49:19 -0600[diff] [blame]22 reg = <0 0x10>;
23 bank-name = "A";
24 };
25
26 gpiob {
27 compatible = "intel,ich6-gpio";
Simon Glass437c2b72014-11-12 22:42:25 -0700[diff] [blame]28 u-boot,dm-pre-reloc;
Simon Glassd1259c92014-10-10 07:49:19 -0600[diff] [blame]29 reg = <0x30 0x10>;
30 bank-name = "B";
31 };
32
33 gpioc {
34 compatible = "intel,ich6-gpio";
Simon Glass437c2b72014-11-12 22:42:25 -0700[diff] [blame]35 u-boot,dm-pre-reloc;
Simon Glassd1259c92014-10-10 07:49:19 -0600[diff] [blame]36 reg = <0x40 0x10>;
37 bank-name = "C";
38 };
Simon Glass2712f082012-12-03 13:56:51 +0000[diff] [blame]39
Bin Meng120c4162014-12-24 13:06:39 +0800[diff] [blame]40 chosen {
41 stdout-path = "/serial";
Simon Glass2712f082012-12-03 13:56:51 +0000[diff] [blame]42 };
43
Simon Glass65dd74a2014-11-12 22:42:28 -0700[diff] [blame]44 spd {
45 compatible = "memory-spd";
46 #address-cells = <1>;
47 #size-cells = <0>;
48 elpida_4Gb_1600_x16 {
49 reg = <0>;
50 data = [92 10 0b 03 04 19 02 02
51 03 52 01 08 0a 00 fe 00
52 69 78 69 3c 69 11 18 81
53 20 08 3c 3c 01 40 83 81
54 00 00 00 00 00 00 00 00
55 00 00 00 00 00 00 00 00
56 00 00 00 00 00 00 00 00
57 00 00 00 00 0f 11 42 00
58 00 00 00 00 00 00 00 00
59 00 00 00 00 00 00 00 00
60 00 00 00 00 00 00 00 00
61 00 00 00 00 00 00 00 00
62 00 00 00 00 00 00 00 00
63 00 00 00 00 00 00 00 00
64 00 00 00 00 00 02 fe 00
65 11 52 00 00 00 07 7f 37
66 45 42 4a 32 30 55 47 36
67 45 42 55 30 2d 47 4e 2d
68 46 20 30 20 02 fe 00 00
69 00 00 00 00 00 00 00 00
70 00 00 00 00 00 00 00 00
71 00 00 00 00 00 00 00 00
72 00 00 00 00 00 00 00 00
73 00 00 00 00 00 00 00 00
74 00 00 00 00 00 00 00 00
75 00 00 00 00 00 00 00 00
76 00 00 00 00 00 00 00 00
77 00 00 00 00 00 00 00 00
78 00 00 00 00 00 00 00 00
79 00 00 00 00 00 00 00 00
80 00 00 00 00 00 00 00 00
81 00 00 00 00 00 00 00 00];
82 };
83 samsung_4Gb_1600_1.35v_x16 {
84 reg = <1>;
85 data = [92 11 0b 03 04 19 02 02
86 03 11 01 08 0a 00 fe 00
87 69 78 69 3c 69 11 18 81
88 f0 0a 3c 3c 01 40 83 01
89 00 80 00 00 00 00 00 00
90 00 00 00 00 00 00 00 00
91 00 00 00 00 00 00 00 00
92 00 00 00 00 0f 11 02 00
93 00 00 00 00 00 00 00 00
94 00 00 00 00 00 00 00 00
95 00 00 00 00 00 00 00 00
96 00 00 00 00 00 00 00 00
97 00 00 00 00 00 00 00 00
98 00 00 00 00 00 00 00 00
99 00 00 00 00 00 80 ce 01
100 00 00 00 00 00 00 6a 04
101 4d 34 37 31 42 35 36 37
102 34 42 48 30 2d 59 4b 30
103 20 20 00 00 80 ce 00 00
104 00 00 00 00 00 00 00 00
105 00 00 00 00 00 00 00 00
106 00 00 00 00 00 00 00 00
107 00 00 00 00 00 00 00 00
108 00 00 00 00 00 00 00 00
109 00 00 00 00 00 00 00 00
110 00 00 00 00 00 00 00 00
111 00 00 00 00 00 00 00 00
112 00 00 00 00 00 00 00 00
113 00 00 00 00 00 00 00 00
114 00 00 00 00 00 00 00 00
115 00 00 00 00 00 00 00 00
116 00 00 00 00 00 00 00 00];
117 };
118 micron_4Gb_1600_1.35v_x16 {
119 reg = <2>;
120 data = [92 11 0b 03 04 19 02 02
121 03 11 01 08 0a 00 fe 00
122 69 78 69 3c 69 11 18 81
123 20 08 3c 3c 01 40 83 05
124 00 00 00 00 00 00 00 00
125 00 00 00 00 00 00 00 00
126 00 00 00 00 00 00 00 00
127 00 00 00 00 0f 01 02 00
128 00 00 00 00 00 00 00 00
129 00 00 00 00 00 00 00 00
130 00 00 00 00 00 00 00 00
131 00 00 00 00 00 00 00 00
132 00 00 00 00 00 00 00 00
133 00 00 00 00 00 00 00 00
134 00 00 00 00 00 80 2c 00
135 00 00 00 00 00 00 ad 75
136 34 4b 54 46 32 35 36 36
137 34 48 5a 2d 31 47 36 45
138 31 20 45 31 80 2c 00 00
139 00 00 00 00 00 00 00 00
140 00 00 00 00 00 00 00 00
141 00 00 00 00 00 00 00 00
142 ff ff ff ff ff ff ff ff
143 ff ff ff ff ff ff ff ff
144 ff ff ff ff ff ff ff ff
145 ff ff ff ff ff ff ff ff
146 ff ff ff ff ff ff ff ff
147 ff ff ff ff ff ff ff ff
148 ff ff ff ff ff ff ff ff
149 ff ff ff ff ff ff ff ff
150 ff ff ff ff ff ff ff ff
151 ff ff ff ff ff ff ff ff];
152 };
153 };
154
Simon Glassb021e052014-11-14 18:18:36 -0700[diff] [blame]155 pci {
Simon Glass801f4f12015-03-05 12:25:32 -0700[diff] [blame]156 compatible = "intel,pci-ivybridge", "pci-x86";
157 #address-cells = <3>;
158 #size-cells = <2>;
159 u-boot,dm-pre-reloc;
160 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
161 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
162 0x01000000 0x0 0x1000 0x1000 0 0xefff>;
Simon Glass4896f4a2014-11-14 18:18:39 -0700[diff] [blame]163 sata {
164 compatible = "intel,pantherpoint-ahci";
165 intel,sata-mode = "ahci";
166 intel,sata-port-map = <1>;
167 intel,sata-port0-gen3-tx = <0x00880a7f>;
168 };
169
Simon Glassf3e56fe2014-11-14 20:56:37 -0700[diff] [blame]170 gma {
171 compatible = "intel,gma";
172 intel,dp_hotplug = <0 0 0x06>;
173 intel,panel-port-select = <1>;
174 intel,panel-power-cycle-delay = <6>;
175 intel,panel-power-up-delay = <2000>;
176 intel,panel-power-down-delay = <500>;
177 intel,panel-power-backlight-on-delay = <2000>;
178 intel,panel-power-backlight-off-delay = <2000>;
179 intel,cpu-backlight = <0x00000200>;
180 intel,pch-backlight = <0x04000000>;
181 };
182
Simon Glass90b16d12015-03-26 09:29:29 -0600[diff] [blame]183 pch {
Simon Glassaad78d22015-03-05 12:25:33 -0700[diff] [blame]184 reg = <0x0000f800 0 0 0 0>;
Simon Glass87f4cd32015-04-20 07:07:03 -0600[diff] [blame]185 compatible = "intel,bd82x6x", "intel,pch";
Simon Glass90b16d12015-03-26 09:29:29 -0600[diff] [blame]186 u-boot,dm-pre-reloc;
Simon Glass6ddc4fd2014-10-10 07:30:13 -0600[diff] [blame]187 #address-cells = <1>;
188 #size-cells = <1>;
Simon Glassb021e052014-11-14 18:18:36 -0700[diff] [blame]189 gen-dec = <0x800 0xfc 0x900 0xfc>;
Simon Glass05efc392014-11-14 18:18:37 -0700[diff] [blame]190 intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
191 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
192 0x80 0x80 0x80 0x80>;
193 intel,gpi-routing = <0 0 0 0 0 0 0 2
194 1 0 0 0 0 0 0 0>;
195 /* Enable EC SMI source */
196 intel,alt-gp-smi-enable = <0x0100>;
Simon Glass90b16d12015-03-26 09:29:29 -0600[diff] [blame]197 spi {
Simon Glassb021e052014-11-14 18:18:36 -0700[diff] [blame]198 #address-cells = <1>;
Simon Glass90b16d12015-03-26 09:29:29 -0600[diff] [blame]199 #size-cells = <0>;
200 compatible = "intel,ich-spi";
201 spi-flash@0 {
202 #size-cells = <1>;
203 #address-cells = <1>;
204 reg = <0>;
205 compatible = "winbond,w25q64",
206 "spi-flash";
207 memory-map = <0xff800000 0x00800000>;
208 rw-mrc-cache {
209 label = "rw-mrc-cache";
210 reg = <0x003e0000 0x00010000>;
Simon Glass90b16d12015-03-26 09:29:29 -0600[diff] [blame]211 };
212 };
213 };
214
215 lpc {
216 compatible = "intel,bd82x6x-lpc";
217 #address-cells = <1>;
218 #size-cells = <0>;
219 cros-ec@200 {
220 compatible = "google,cros-ec";
221 reg = <0x204 1 0x200 1 0x880 0x80>;
222
223 /*
224 * Describes the flash memory within
225 * the EC
226 */
227 #address-cells = <1>;
228 #size-cells = <1>;
229 flash@8000000 {
230 reg = <0x08000000 0x20000>;
231 erase-value = <0xff>;
232 };
Simon Glassb021e052014-11-14 18:18:36 -0700[diff] [blame]233 };
Simon Glass6ddc4fd2014-10-10 07:30:13 -0600[diff] [blame]234 };
235 };
236 };
Simon Glass9c678e12014-11-12 22:42:22 -0700[diff] [blame]237
Simon Glass6e474ea2015-08-22 18:31:37 -0600[diff] [blame]238 tpm {
239 reg = <0xfed40000 0x5000>;
240 compatible = "infineon,slb9635lpc";
241 };
242
Simon Glass9c678e12014-11-12 22:42:22 -0700[diff] [blame]243 microcode {
244 update@0 {
Simon Glasscf29e3e2014-12-15 22:02:40 -0700[diff] [blame]245#include "microcode/m12306a9_0000001b.dtsi"
Simon Glass9c678e12014-11-12 22:42:22 -0700[diff] [blame]246 };
247 };
248
Simon Glass2712f082012-12-03 13:56:51 +0000[diff] [blame]249};