blob: 5b017a910cd7bbfd919cb5c3d8033a568302f91e [file] [log] [blame]
Jon Loeliger7237c032006-10-19 11:02:16 -05001/*
Timur Tabi92477a62009-09-04 16:28:35 -05002 * Copyright 2006,2009 Freescale Semiconductor, Inc.
Jon Loeliger7237c032006-10-19 11:02:16 -05003 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
16 * MA 02111-1307 USA
17 */
18
Jon Loeliger7237c032006-10-19 11:02:16 -050019#include <common.h>
Jon Loeliger7237c032006-10-19 11:02:16 -050020
21#ifdef CONFIG_HARD_I2C
22
Jon Loeliger4d45f692006-10-19 12:02:24 -050023#include <command.h>
Jon Loeliger20476722006-10-20 15:50:15 -050024#include <i2c.h> /* Functional interface */
25
Jon Loeliger7237c032006-10-19 11:02:16 -050026#include <asm/io.h>
Jon Loeliger20476722006-10-20 15:50:15 -050027#include <asm/fsl_i2c.h> /* HW definitions */
Jon Loeliger7237c032006-10-19 11:02:16 -050028
Timur Tabi92477a62009-09-04 16:28:35 -050029/* The maximum number of microseconds we will wait until another master has
30 * released the bus. If not defined in the board header file, then use a
31 * generic value.
32 */
33#ifndef CONFIG_I2C_MBB_TIMEOUT
34#define CONFIG_I2C_MBB_TIMEOUT 100000
35#endif
36
37/* The maximum number of microseconds we will wait for a read or write
38 * operation to complete. If not defined in the board header file, then use a
39 * generic value.
40 */
41#ifndef CONFIG_I2C_TIMEOUT
42#define CONFIG_I2C_TIMEOUT 10000
43#endif
Jon Loeliger7237c032006-10-19 11:02:16 -050044
Joakim Tjernlund1939d962006-11-28 16:17:27 -060045#define I2C_READ_BIT 1
46#define I2C_WRITE_BIT 0
47
Timur Tabid8c82db2008-03-14 17:45:29 -050048DECLARE_GLOBAL_DATA_PTR;
49
Timur Tabibe5e6182006-11-03 19:15:00 -060050/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
51 * Default is bus 0. This is necessary because the DDR initialization
52 * runs from ROM, and we can't switch buses because we can't modify
53 * the global variables.
54 */
Trent Piepho5e3ab682008-11-12 17:29:48 -080055#ifndef CONFIG_SYS_SPD_BUS_NUM
56#define CONFIG_SYS_SPD_BUS_NUM 0
Timur Tabibe5e6182006-11-03 19:15:00 -060057#endif
Trent Piepho5e3ab682008-11-12 17:29:48 -080058static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM;
Heiko Schocherc1bce4f2009-02-24 11:30:37 +010059#if defined(CONFIG_I2C_MUX)
60static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0;
61#endif
Timur Tabibe5e6182006-11-03 19:15:00 -060062
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED};
Timur Tabid8c82db2008-03-14 17:45:29 -050064
65static const struct fsl_i2c *i2c_dev[2] = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET),
67#ifdef CONFIG_SYS_I2C2_OFFSET
68 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET)
Timur Tabibe5e6182006-11-03 19:15:00 -060069#endif
70};
Jon Loeliger7237c032006-10-19 11:02:16 -050071
Timur Tabid8c82db2008-03-14 17:45:29 -050072/* I2C speed map for a DFSR value of 1 */
73
74/*
75 * Map I2C frequency dividers to FDR and DFSR values
76 *
77 * This structure is used to define the elements of a table that maps I2C
78 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
79 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
80 * Sampling Rate (DFSR) registers.
81 *
82 * The actual table should be defined in the board file, and it must be called
83 * fsl_i2c_speed_map[].
84 *
85 * The last entry of the table must have a value of {-1, X}, where X is same
86 * FDR/DFSR values as the second-to-last entry. This guarantees that any
87 * search through the array will always find a match.
88 *
89 * The values of the divider must be in increasing numerical order, i.e.
90 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
91 *
92 * For this table, the values are based on a value of 1 for the DFSR
93 * register. See the application note AN2919 "Determining the I2C Frequency
94 * Divider Ratio for SCL"
TsiChung Liew5d9a5ef2008-08-19 00:56:46 +060095 *
96 * ColdFire I2C frequency dividers for FDR values are different from
97 * PowerPC. The protocol to use the I2C module is still the same.
98 * A different table is defined and are based on MCF5xxx user manual.
99 *
Timur Tabid8c82db2008-03-14 17:45:29 -0500100 */
101static const struct {
102 unsigned short divider;
Timur Tabid8c82db2008-03-14 17:45:29 -0500103 u8 fdr;
104} fsl_i2c_speed_map[] = {
Joakim Tjernlund99404202009-09-17 11:07:17 +0200105#ifdef __M68K__
TsiChung Liew5d9a5ef2008-08-19 00:56:46 +0600106 {20, 32}, {22, 33}, {24, 34}, {26, 35},
107 {28, 0}, {28, 36}, {30, 1}, {32, 37},
108 {34, 2}, {36, 38}, {40, 3}, {40, 39},
109 {44, 4}, {48, 5}, {48, 40}, {56, 6},
110 {56, 41}, {64, 42}, {68, 7}, {72, 43},
111 {80, 8}, {80, 44}, {88, 9}, {96, 41},
112 {104, 10}, {112, 42}, {128, 11}, {128, 43},
113 {144, 12}, {160, 13}, {160, 48}, {192, 14},
114 {192, 49}, {224, 50}, {240, 15}, {256, 51},
115 {288, 16}, {320, 17}, {320, 52}, {384, 18},
116 {384, 53}, {448, 54}, {480, 19}, {512, 55},
117 {576, 20}, {640, 21}, {640, 56}, {768, 22},
118 {768, 57}, {960, 23}, {896, 58}, {1024, 59},
119 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
120 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
121 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
122 {-1, 31}
123#endif
Timur Tabid8c82db2008-03-14 17:45:29 -0500124};
125
126/**
127 * Set the I2C bus speed for a given I2C device
128 *
129 * @param dev: the I2C device
130 * @i2c_clk: I2C bus clock frequency
131 * @speed: the desired speed of the bus
132 *
133 * The I2C device must be stopped before calling this function.
134 *
135 * The return value is the actual bus speed that is set.
136 */
137static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
138 unsigned int i2c_clk, unsigned int speed)
139{
140 unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);
Timur Tabid8c82db2008-03-14 17:45:29 -0500141
142 /*
143 * We want to choose an FDR/DFSR that generates an I2C bus speed that
144 * is equal to or lower than the requested speed. That means that we
145 * want the first divider that is equal to or greater than the
146 * calculated divider.
147 */
Joakim Tjernlund99404202009-09-17 11:07:17 +0200148#ifdef __PPC__
149 u8 dfsr, fdr = 0x31; /* Default if no FDR found */
150 /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
151 unsigned short a, b, ga, gb;
152 unsigned long c_div, est_div;
153
154#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
155 dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
156#else
157 /* Condition 1: dfsr <= 50/T */
158 dfsr = (5 * (i2c_clk / 1000)) / 100000;
159#endif
160#ifdef CONFIG_FSL_I2C_CUSTOM_FDR
161 fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
162 speed = i2c_clk / divider; /* Fake something */
163#else
164 debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
165 if (!dfsr)
166 dfsr = 1;
167
168 est_div = ~0;
169 for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
170 for (gb = 0; gb < 8; gb++) {
171 b = 16 << gb;
172 c_div = b * (a + ((3*dfsr)/b)*2);
173 if ((c_div > divider) && (c_div < est_div)) {
174 unsigned short bin_gb, bin_ga;
175
176 est_div = c_div;
177 bin_gb = gb << 2;
178 bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
179 fdr = bin_gb | bin_ga;
180 speed = i2c_clk / est_div;
181 debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, "
182 "a:%d, b:%d, speed:%d\n",
183 fdr, est_div, ga, gb, a, b, speed);
184 /* Condition 2 not accounted for */
185 debug("Tr <= %d ns\n",
186 (b - 3 * dfsr) * 1000000 /
187 (i2c_clk / 1000));
188 }
189 }
190 if (a == 20)
191 a += 2;
192 if (a == 24)
193 a += 4;
194 }
195 debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
196 debug("FDR:0x%.2x, speed:%d\n", fdr, speed);
197#endif
198 writeb(dfsr, &dev->dfsrr); /* set default filter */
199 writeb(fdr, &dev->fdr); /* set bus speed */
200#else
201 unsigned int i;
Timur Tabid8c82db2008-03-14 17:45:29 -0500202
203 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
204 if (fsl_i2c_speed_map[i].divider >= divider) {
TsiChung Liew5d9a5ef2008-08-19 00:56:46 +0600205 u8 fdr;
Joakim Tjernlund99404202009-09-17 11:07:17 +0200206
Joakim Tjernlundd01ee4d2009-09-17 11:07:16 +0200207 fdr = fsl_i2c_speed_map[i].fdr;
208 speed = i2c_clk / fsl_i2c_speed_map[i].divider;
Joakim Tjernlundd01ee4d2009-09-17 11:07:16 +0200209 writeb(fdr, &dev->fdr); /* set bus speed */
210
Timur Tabid8c82db2008-03-14 17:45:29 -0500211 break;
212 }
Joakim Tjernlund99404202009-09-17 11:07:17 +0200213#endif
Timur Tabid8c82db2008-03-14 17:45:29 -0500214 return speed;
215}
216
Jerry Huangc9a8b252011-10-26 15:29:38 +0000217unsigned int get_i2c_clock(int bus)
218{
219 if (bus)
220 return gd->i2c2_clk; /* I2C2 clock */
221 else
222 return gd->i2c1_clk; /* I2C1 clock */
223}
224
Jon Loeliger7237c032006-10-19 11:02:16 -0500225void
226i2c_init(int speed, int slaveadd)
227{
Kumar Galaaa551212011-11-08 03:39:43 +0000228 const struct fsl_i2c *dev;
Stefan Roesef2302d42008-08-06 14:05:38 +0200229 unsigned int temp;
Jerry Huangc9a8b252011-10-26 15:29:38 +0000230 int bus_num, i;
Jon Loeliger7237c032006-10-19 11:02:16 -0500231
Heiko Schocher39df00d2009-07-09 12:04:26 +0200232#ifdef CONFIG_SYS_I2C_INIT_BOARD
Richard Retanubun26a33502010-04-12 15:08:17 -0400233 /* Call board specific i2c bus reset routine before accessing the
234 * environment, which might be in a chip on that bus. For details
235 * about this problem see doc/I2C_Edge_Conditions.
236 */
Heiko Schocher39df00d2009-07-09 12:04:26 +0200237 i2c_init_board();
238#endif
Jerry Huangc9a8b252011-10-26 15:29:38 +0000239#ifdef CONFIG_SYS_I2C2_OFFSET
240 bus_num = 2;
241#else
242 bus_num = 1;
Timur Tabid8c82db2008-03-14 17:45:29 -0500243#endif
Jerry Huangc9a8b252011-10-26 15:29:38 +0000244 for (i = 0; i < bus_num; i++) {
245 dev = i2c_dev[i];
246
247 writeb(0, &dev->cr); /* stop I2C controller */
248 udelay(5); /* let it shutdown in peace */
249 temp = set_i2c_bus_speed(dev, get_i2c_clock(i), speed);
250 if (gd->flags & GD_FLG_RELOC)
251 i2c_bus_speed[i] = temp;
252 writeb(slaveadd << 1, &dev->adr);/* write slave address */
253 writeb(0x0, &dev->sr); /* clear status register */
254 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
255 }
Richard Retanubun26a33502010-04-12 15:08:17 -0400256
257#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
258 /* Call board specific i2c bus reset routine AFTER the bus has been
259 * initialized. Use either this callpoint or i2c_init_board;
260 * which is called before i2c_init operations.
261 * For details about this problem see doc/I2C_Edge_Conditions.
262 */
263 i2c_board_late_init();
264#endif
Jon Loeliger7237c032006-10-19 11:02:16 -0500265}
266
Joakim Tjernlund21f4cbb2009-09-17 11:07:15 +0200267static int
Jon Loeliger7237c032006-10-19 11:02:16 -0500268i2c_wait4bus(void)
269{
Stefan Roesef2302d42008-08-06 14:05:38 +0200270 unsigned long long timeval = get_ticks();
Timur Tabi92477a62009-09-04 16:28:35 -0500271 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
Jon Loeliger7237c032006-10-19 11:02:16 -0500272
Timur Tabibe5e6182006-11-03 19:15:00 -0600273 while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
Timur Tabi92477a62009-09-04 16:28:35 -0500274 if ((get_ticks() - timeval) > timeout)
Jon Loeliger7237c032006-10-19 11:02:16 -0500275 return -1;
Jon Loeliger7237c032006-10-19 11:02:16 -0500276 }
277
278 return 0;
279}
280
281static __inline__ int
282i2c_wait(int write)
283{
284 u32 csr;
Stefan Roesef2302d42008-08-06 14:05:38 +0200285 unsigned long long timeval = get_ticks();
Timur Tabi92477a62009-09-04 16:28:35 -0500286 const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
Jon Loeliger7237c032006-10-19 11:02:16 -0500287
288 do {
Timur Tabibe5e6182006-11-03 19:15:00 -0600289 csr = readb(&i2c_dev[i2c_bus_num]->sr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500290 if (!(csr & I2C_SR_MIF))
291 continue;
Joakim Tjernlund21f4cbb2009-09-17 11:07:15 +0200292 /* Read again to allow register to stabilise */
293 csr = readb(&i2c_dev[i2c_bus_num]->sr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500294
Timur Tabibe5e6182006-11-03 19:15:00 -0600295 writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500296
297 if (csr & I2C_SR_MAL) {
298 debug("i2c_wait: MAL\n");
299 return -1;
300 }
301
302 if (!(csr & I2C_SR_MCF)) {
303 debug("i2c_wait: unfinished\n");
304 return -1;
305 }
306
Joakim Tjernlund1939d962006-11-28 16:17:27 -0600307 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
Jon Loeliger7237c032006-10-19 11:02:16 -0500308 debug("i2c_wait: No RXACK\n");
309 return -1;
310 }
311
312 return 0;
Timur Tabi92477a62009-09-04 16:28:35 -0500313 } while ((get_ticks() - timeval) < timeout);
Jon Loeliger7237c032006-10-19 11:02:16 -0500314
315 debug("i2c_wait: timed out\n");
316 return -1;
317}
318
319static __inline__ int
320i2c_write_addr (u8 dev, u8 dir, int rsta)
321{
322 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
323 | (rsta ? I2C_CR_RSTA : 0),
Timur Tabibe5e6182006-11-03 19:15:00 -0600324 &i2c_dev[i2c_bus_num]->cr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500325
Timur Tabibe5e6182006-11-03 19:15:00 -0600326 writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500327
Joakim Tjernlund1939d962006-11-28 16:17:27 -0600328 if (i2c_wait(I2C_WRITE_BIT) < 0)
Jon Loeliger7237c032006-10-19 11:02:16 -0500329 return 0;
330
331 return 1;
332}
333
334static __inline__ int
335__i2c_write(u8 *data, int length)
336{
337 int i;
338
Jon Loeliger7237c032006-10-19 11:02:16 -0500339 for (i = 0; i < length; i++) {
Timur Tabibe5e6182006-11-03 19:15:00 -0600340 writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500341
Joakim Tjernlund1939d962006-11-28 16:17:27 -0600342 if (i2c_wait(I2C_WRITE_BIT) < 0)
Jon Loeliger7237c032006-10-19 11:02:16 -0500343 break;
344 }
345
346 return i;
347}
348
349static __inline__ int
350__i2c_read(u8 *data, int length)
351{
352 int i;
353
354 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
Timur Tabibe5e6182006-11-03 19:15:00 -0600355 &i2c_dev[i2c_bus_num]->cr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500356
357 /* dummy read */
Timur Tabibe5e6182006-11-03 19:15:00 -0600358 readb(&i2c_dev[i2c_bus_num]->dr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500359
360 for (i = 0; i < length; i++) {
Joakim Tjernlund1939d962006-11-28 16:17:27 -0600361 if (i2c_wait(I2C_READ_BIT) < 0)
Jon Loeliger7237c032006-10-19 11:02:16 -0500362 break;
363
364 /* Generate ack on last next to last byte */
365 if (i == length - 2)
366 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
Timur Tabibe5e6182006-11-03 19:15:00 -0600367 &i2c_dev[i2c_bus_num]->cr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500368
Joakim Tjernlundd1c9e5b2009-09-22 13:40:44 +0200369 /* Do not generate stop on last byte */
Jon Loeliger7237c032006-10-19 11:02:16 -0500370 if (i == length - 1)
Joakim Tjernlundd1c9e5b2009-09-22 13:40:44 +0200371 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
372 &i2c_dev[i2c_bus_num]->cr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500373
Timur Tabibe5e6182006-11-03 19:15:00 -0600374 data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500375 }
376
377 return i;
378}
379
380int
381i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
382{
Joakim Tjernlundf6f5f702007-01-31 11:04:19 +0100383 int i = -1; /* signal error */
Jon Loeliger7237c032006-10-19 11:02:16 -0500384 u8 *a = (u8*)&addr;
385
Jon Loeliger4d45f692006-10-19 12:02:24 -0500386 if (i2c_wait4bus() >= 0
Joakim Tjernlund1939d962006-11-28 16:17:27 -0600387 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
Joakim Tjernlundf6f5f702007-01-31 11:04:19 +0100388 && __i2c_write(&a[4 - alen], alen) == alen)
389 i = 0; /* No error so far */
390
391 if (length
392 && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0)
Jon Loeliger4d45f692006-10-19 12:02:24 -0500393 i = __i2c_read(data, length);
Jon Loeliger7237c032006-10-19 11:02:16 -0500394
Timur Tabibe5e6182006-11-03 19:15:00 -0600395 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500396
Joakim Tjernlundd1c9e5b2009-09-22 13:40:44 +0200397 if (i2c_wait4bus()) /* Wait until STOP */
398 debug("i2c_read: wait4bus timed out\n");
399
Jon Loeliger4d45f692006-10-19 12:02:24 -0500400 if (i == length)
401 return 0;
402
403 return -1;
Jon Loeliger7237c032006-10-19 11:02:16 -0500404}
405
406int
407i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
408{
Joakim Tjernlundf6f5f702007-01-31 11:04:19 +0100409 int i = -1; /* signal error */
Jon Loeliger7237c032006-10-19 11:02:16 -0500410 u8 *a = (u8*)&addr;
411
Jon Loeliger4d45f692006-10-19 12:02:24 -0500412 if (i2c_wait4bus() >= 0
Joakim Tjernlund1939d962006-11-28 16:17:27 -0600413 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
Jon Loeliger4d45f692006-10-19 12:02:24 -0500414 && __i2c_write(&a[4 - alen], alen) == alen) {
415 i = __i2c_write(data, length);
416 }
Jon Loeliger7237c032006-10-19 11:02:16 -0500417
Timur Tabibe5e6182006-11-03 19:15:00 -0600418 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
Joakim Tjernlund21f4cbb2009-09-17 11:07:15 +0200419 if (i2c_wait4bus()) /* Wait until STOP */
420 debug("i2c_write: wait4bus timed out\n");
Jon Loeliger7237c032006-10-19 11:02:16 -0500421
Jon Loeliger4d45f692006-10-19 12:02:24 -0500422 if (i == length)
423 return 0;
424
425 return -1;
Jon Loeliger7237c032006-10-19 11:02:16 -0500426}
427
428int
429i2c_probe(uchar chip)
430{
Joakim Tjernlundf6f5f702007-01-31 11:04:19 +0100431 /* For unknow reason the controller will ACK when
432 * probing for a slave with the same address, so skip
433 * it.
Jon Loeliger7237c032006-10-19 11:02:16 -0500434 */
Joakim Tjernlundf6f5f702007-01-31 11:04:19 +0100435 if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1))
436 return -1;
Jon Loeliger7237c032006-10-19 11:02:16 -0500437
Joakim Tjernlundf6f5f702007-01-31 11:04:19 +0100438 return i2c_read(chip, 0, 0, NULL, 0);
Jon Loeliger7237c032006-10-19 11:02:16 -0500439}
440
Timur Tabibe5e6182006-11-03 19:15:00 -0600441int i2c_set_bus_num(unsigned int bus)
442{
Heiko Schocherc1bce4f2009-02-24 11:30:37 +0100443#if defined(CONFIG_I2C_MUX)
444 if (bus < CONFIG_SYS_MAX_I2C_BUS) {
445 i2c_bus_num = bus;
446 } else {
447 int ret;
448
449 ret = i2x_mux_select_mux(bus);
450 if (ret)
451 return ret;
452 i2c_bus_num = 0;
453 }
454 i2c_bus_num_mux = bus;
455#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#ifdef CONFIG_SYS_I2C2_OFFSET
Timur Tabibe5e6182006-11-03 19:15:00 -0600457 if (bus > 1) {
458#else
459 if (bus > 0) {
460#endif
461 return -1;
462 }
463
464 i2c_bus_num = bus;
Heiko Schocherc1bce4f2009-02-24 11:30:37 +0100465#endif
Timur Tabibe5e6182006-11-03 19:15:00 -0600466 return 0;
467}
468
469int i2c_set_bus_speed(unsigned int speed)
470{
Timur Tabid8c82db2008-03-14 17:45:29 -0500471 unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk;
472
473 writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */
474 i2c_bus_speed[i2c_bus_num] =
475 set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed);
476 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */
477
478 return 0;
Timur Tabibe5e6182006-11-03 19:15:00 -0600479}
480
481unsigned int i2c_get_bus_num(void)
482{
Heiko Schocherc1bce4f2009-02-24 11:30:37 +0100483#if defined(CONFIG_I2C_MUX)
484 return i2c_bus_num_mux;
485#else
Timur Tabibe5e6182006-11-03 19:15:00 -0600486 return i2c_bus_num;
Heiko Schocherc1bce4f2009-02-24 11:30:37 +0100487#endif
Timur Tabibe5e6182006-11-03 19:15:00 -0600488}
489
490unsigned int i2c_get_bus_speed(void)
491{
Timur Tabid8c82db2008-03-14 17:45:29 -0500492 return i2c_bus_speed[i2c_bus_num];
Timur Tabibe5e6182006-11-03 19:15:00 -0600493}
Timur Tabid8c82db2008-03-14 17:45:29 -0500494
Jon Loeliger7237c032006-10-19 11:02:16 -0500495#endif /* CONFIG_HARD_I2C */