Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Masahiro Yamada | 254d68b | 2014-03-18 16:38:13 +0900 | [diff] [blame] | 2 | /* |
| 3 | * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c |
| 4 | * |
| 5 | * This program is used to generate definitions needed by |
| 6 | * assembly language modules. |
| 7 | * |
| 8 | * We use the technique used in the OSF Mach kernel code: |
| 9 | * generate asm statements containing #defines, |
| 10 | * compile this file to assembler, and then extract the |
| 11 | * #defines from the assembly-language output. |
Masahiro Yamada | 254d68b | 2014-03-18 16:38:13 +0900 | [diff] [blame] | 12 | */ |
| 13 | |
| 14 | #include <common.h> |
| 15 | #include <linux/kbuild.h> |
Masahiro Yamada | c54bcf6 | 2017-04-14 11:10:23 +0900 | [diff] [blame] | 16 | #include <linux/arm-smccc.h> |
Masahiro Yamada | 254d68b | 2014-03-18 16:38:13 +0900 | [diff] [blame] | 17 | |
Masahiro Yamada | 254d68b | 2014-03-18 16:38:13 +0900 | [diff] [blame] | 18 | #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \ |
| 19 | || defined(CONFIG_MX51) || defined(CONFIG_MX53) |
| 20 | #include <asm/arch/imx-regs.h> |
| 21 | #endif |
| 22 | |
| 23 | int main(void) |
| 24 | { |
| 25 | /* |
| 26 | * TODO : Check if each entry in this file is really necessary. |
Masahiro Yamada | 254d68b | 2014-03-18 16:38:13 +0900 | [diff] [blame] | 27 | * - struct esdramc_regs |
| 28 | * - struct max_regs |
| 29 | * - struct aips_regs |
| 30 | * - struct aipi_regs |
| 31 | * - struct clkctl |
| 32 | * - struct dpll |
| 33 | * are used only for generating asm-offsets.h. |
| 34 | * It means their offset addresses are referenced only from assembly |
| 35 | * code. Is it better to define the macros directly in headers? |
| 36 | */ |
| 37 | |
Masahiro Yamada | 254d68b | 2014-03-18 16:38:13 +0900 | [diff] [blame] | 38 | #if defined(CONFIG_MX25) |
| 39 | /* Clock Control Module */ |
| 40 | DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); |
| 41 | DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0)); |
| 42 | DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1)); |
| 43 | DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2)); |
| 44 | DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2])); |
| 45 | DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr)); |
| 46 | |
| 47 | /* Enhanced SDRAM Controller */ |
| 48 | DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0)); |
| 49 | DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0)); |
| 50 | DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc)); |
| 51 | |
| 52 | /* Multi-Layer AHB Crossbar Switch */ |
| 53 | DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); |
| 54 | DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); |
| 55 | DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); |
| 56 | DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); |
| 57 | DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); |
| 58 | DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); |
| 59 | DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); |
| 60 | DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); |
| 61 | DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); |
| 62 | DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); |
| 63 | DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); |
| 64 | DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); |
| 65 | DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); |
| 66 | DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); |
| 67 | DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); |
| 68 | |
| 69 | /* AHB <-> IP-Bus Interface */ |
| 70 | DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); |
| 71 | DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); |
| 72 | #endif |
| 73 | |
| 74 | #if defined(CONFIG_MX27) |
| 75 | DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); |
| 76 | DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); |
| 77 | DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0)); |
| 78 | DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1)); |
| 79 | |
| 80 | DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); |
| 81 | DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); |
| 82 | DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); |
| 83 | DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); |
| 84 | DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); |
| 85 | DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); |
| 86 | DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); |
| 87 | |
| 88 | DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0)); |
| 89 | DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0)); |
| 90 | DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1)); |
| 91 | DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); |
| 92 | DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc)); |
| 93 | |
| 94 | DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + |
| 95 | offsetof(struct system_control_regs, gpcr)); |
| 96 | DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + |
| 97 | offsetof(struct system_control_regs, fmcr)); |
| 98 | #endif |
| 99 | |
| 100 | #if defined(CONFIG_MX35) |
| 101 | /* Round up to make sure size gives nice stack alignment */ |
| 102 | DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr)); |
| 103 | DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0)); |
| 104 | DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1)); |
| 105 | DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2)); |
| 106 | DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3)); |
| 107 | DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4)); |
| 108 | DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr)); |
| 109 | DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl)); |
| 110 | DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl)); |
| 111 | DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr)); |
| 112 | DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr)); |
| 113 | DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0)); |
| 114 | DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1)); |
| 115 | DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2)); |
| 116 | DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3)); |
| 117 | |
| 118 | /* Multi-Layer AHB Crossbar Switch */ |
| 119 | DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); |
| 120 | DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); |
| 121 | DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); |
| 122 | DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); |
| 123 | DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); |
| 124 | DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); |
| 125 | DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); |
| 126 | DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); |
| 127 | DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); |
| 128 | DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); |
| 129 | DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); |
| 130 | DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); |
| 131 | DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); |
| 132 | DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); |
| 133 | DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); |
| 134 | DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5)); |
| 135 | |
| 136 | /* AHB <-> IP-Bus Interface */ |
| 137 | DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); |
| 138 | DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); |
| 139 | DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7)); |
| 140 | DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15)); |
| 141 | DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23)); |
| 142 | DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31)); |
| 143 | DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7)); |
| 144 | DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15)); |
| 145 | DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23)); |
| 146 | DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31)); |
| 147 | DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39)); |
| 148 | #endif |
| 149 | |
| 150 | #if defined(CONFIG_MX51) || defined(CONFIG_MX53) |
| 151 | /* Round up to make sure size gives nice stack alignment */ |
| 152 | DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); |
| 153 | DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr)); |
| 154 | DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr)); |
| 155 | DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr)); |
| 156 | DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr)); |
| 157 | DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr)); |
| 158 | DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr)); |
| 159 | DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1)); |
| 160 | DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2)); |
| 161 | DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1)); |
| 162 | DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr)); |
| 163 | DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr)); |
| 164 | DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr)); |
| 165 | DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr)); |
| 166 | DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2)); |
| 167 | DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3)); |
| 168 | DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4)); |
| 169 | DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr)); |
| 170 | DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr)); |
| 171 | DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr)); |
| 172 | DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor)); |
| 173 | DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr)); |
| 174 | DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr)); |
| 175 | DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr)); |
| 176 | DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr)); |
| 177 | DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr)); |
| 178 | DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0)); |
| 179 | DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1)); |
| 180 | DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2)); |
| 181 | DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3)); |
| 182 | DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4)); |
| 183 | DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5)); |
| 184 | DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6)); |
| 185 | DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor)); |
| 186 | #if defined(CONFIG_MX53) |
| 187 | DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7)); |
| 188 | #endif |
| 189 | |
| 190 | /* DPLL */ |
| 191 | DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl)); |
| 192 | DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config)); |
| 193 | DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op)); |
| 194 | DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd)); |
| 195 | DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn)); |
| 196 | DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op)); |
| 197 | DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd)); |
| 198 | DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn)); |
| 199 | #endif |
| 200 | |
Masahiro Yamada | c54bcf6 | 2017-04-14 11:10:23 +0900 | [diff] [blame] | 201 | #ifdef CONFIG_ARM_SMCCC |
| 202 | DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0)); |
| 203 | DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2)); |
| 204 | DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id)); |
| 205 | DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state)); |
| 206 | #endif |
| 207 | |
Masahiro Yamada | 254d68b | 2014-03-18 16:38:13 +0900 | [diff] [blame] | 208 | return 0; |
| 209 | } |