blob: fafd306f95b11e242ea156c33636039c2fad761a [file] [log] [blame]
Andre Przywara83843c92017-01-02 11:48:36 +00001@
2@ ARMv8 RMR reset sequence on Allwinner SoCs.
3@
4@ All 64-bit capable Allwinner SoCs reset in AArch32 (and continue to
5@ exectute the Boot ROM in this state), so we need to switch to AArch64
6@ at some point.
7@ Section G6.2.133 of the ARMv8 ARM describes the Reset Management Register
8@ (RMR), which triggers a warm-reset of a core and can request to switch
9@ into a different execution state (AArch32 or AArch64).
10@ The address at which execution starts after the reset is held in the
11@ RVBAR system register, which is architecturally read-only.
12@ Allwinner provides a writable alias of this register in MMIO space, so
13@ we can easily set the start address of AArch64 code.
14@ This code below switches to AArch64 and starts execution at the specified
15@ start address. It needs to be assembled by an ARM(32) assembler and
16@ the machine code must be inserted as verbatim .word statements into the
17@ beginning of the AArch64 U-Boot code.
18@ To get the encoded bytes, use:
19@ ${CROSS_COMPILE}gcc -c -o rmr_switch.o rmr_switch.S
20@ ${CROSS_COMPILE}objdump -d rmr_switch.o
21@
22@ The resulting words should be inserted into the U-Boot file at
23@ arch/arm/include/asm/arch-sunxi/boot0.h.
24@
25@ This file is not build by the U-Boot build system, but provided only as a
26@ reference and to be able to regenerate a (probably fixed) version of this
27@ code found in encoded form in boot0.h.
28
Icenowy Zheng80197802018-07-21 16:20:22 +080029#include <config.h>
30
Andre Przywara83843c92017-01-02 11:48:36 +000031.text
32
Icenowy Zheng80197802018-07-21 16:20:22 +080033#ifndef CONFIG_MACH_SUN50I_H6
Andre Przywara83843c92017-01-02 11:48:36 +000034 ldr r1, =0x017000a0 @ MMIO mapped RVBAR[0] register
Icenowy Zheng80197802018-07-21 16:20:22 +080035#else
36 ldr r1, =0x09010040 @ MMIO mapped RVBAR[0] register
37#endif
Andre Przywara83843c92017-01-02 11:48:36 +000038 ldr r0, =0x57aA7add @ start address, to be replaced
39 str r0, [r1]
40 dsb sy
41 isb sy
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
43 orr r0, r0, #3 @ request reset in AArch64
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
45 isb sy
461: wfi
47 b 1b