Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 1 | menu "Timer Support" |
| 2 | |
| 3 | config TIMER |
Bin Meng | 435ae76 | 2015-11-13 00:11:14 -0800 | [diff] [blame] | 4 | bool "Enable driver model for timer drivers" |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 5 | depends on DM |
| 6 | help |
Bin Meng | 435ae76 | 2015-11-13 00:11:14 -0800 | [diff] [blame] | 7 | Enable driver model for timer access. It uses the same API as |
| 8 | lib/time.c, but now implemented by the uclass. The first timer |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 9 | will be used. The timer is usually a 32 bits free-running up |
| 10 | counter. There may be no real tick, and no timer interrupt. |
| 11 | |
Philipp Tomsich | e9e5d9d | 2017-07-28 17:38:42 +0200 | [diff] [blame] | 12 | config SPL_TIMER |
| 13 | bool "Enable driver model for timer drivers in SPL" |
| 14 | depends on TIMER && SPL |
| 15 | help |
| 16 | Enable support for timer drivers in SPL. These can be used to get |
| 17 | a timer value when in SPL, or perhaps for implementing a delay |
| 18 | function. This enables the drivers in drivers/timer as part of an |
| 19 | SPL build. |
| 20 | |
| 21 | config TPL_TIMER |
| 22 | bool "Enable driver model for timer drivers in TPL" |
| 23 | depends on TIMER && TPL |
| 24 | help |
| 25 | Enable support for timer drivers in TPL. These can be used to get |
| 26 | a timer value when in TPL, or perhaps for implementing a delay |
| 27 | function. This enables the drivers in drivers/timer as part of an |
| 28 | TPL build. |
| 29 | |
Simon Glass | c95fec3 | 2016-02-24 09:14:49 -0700 | [diff] [blame] | 30 | config TIMER_EARLY |
| 31 | bool "Allow timer to be used early in U-Boot" |
| 32 | depends on TIMER |
Simon Glass | 97d20f6 | 2018-09-02 17:02:24 -0600 | [diff] [blame] | 33 | # initr_bootstage() requires a timer and is called before initr_dm() |
| 34 | # so only the early timer is available |
| 35 | default y if X86 && BOOTSTAGE |
Simon Glass | c95fec3 | 2016-02-24 09:14:49 -0700 | [diff] [blame] | 36 | help |
| 37 | In some cases the timer must be accessible before driver model is |
| 38 | active. Examples include when using CONFIG_TRACE to trace U-Boot's |
| 39 | execution before driver model is set up. Enable this option to |
| 40 | use an early timer. These functions must be supported by your timer |
| 41 | driver: timer_early_get_count() and timer_early_get_rate(). |
| 42 | |
Thomas Chou | a54915d | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 43 | config ALTERA_TIMER |
Bin Meng | 435ae76 | 2015-11-13 00:11:14 -0800 | [diff] [blame] | 44 | bool "Altera timer support" |
Thomas Chou | a54915d | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 45 | depends on TIMER |
| 46 | help |
Bin Meng | 435ae76 | 2015-11-13 00:11:14 -0800 | [diff] [blame] | 47 | Select this to enable a timer for Altera devices. Please find |
Thomas Chou | a54915d | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 48 | details on the "Embedded Peripherals IP User Guide" of Altera. |
| 49 | |
Sean Anderson | 7dbebeb | 2020-10-25 21:46:57 -0400 | [diff] [blame] | 50 | config ANDES_PLMT_TIMER |
Sean Anderson | 79b135f | 2020-10-25 21:46:56 -0400 | [diff] [blame] | 51 | bool |
| 52 | depends on RISCV_MMODE || SPL_RISCV_MMODE |
| 53 | help |
| 54 | The Andes PLMT block holds memory-mapped mtime register |
| 55 | associated with timer tick. |
| 56 | |
Bin Meng | 73fe411 | 2018-10-10 22:07:02 -0700 | [diff] [blame] | 57 | config ARC_TIMER |
| 58 | bool "ARC timer support" |
| 59 | depends on TIMER && ARC && CLK |
| 60 | help |
| 61 | Select this to enable built-in ARC timers. |
| 62 | ARC cores may have up to 2 built-in timers: timer0 and timer1, |
| 63 | usually at least one of them exists. Either of them is supported |
| 64 | in U-Boot. |
| 65 | |
| 66 | config AST_TIMER |
| 67 | bool "Aspeed ast2400/ast2500 timer support" |
| 68 | depends on TIMER |
| 69 | default y if ARCH_ASPEED |
| 70 | help |
| 71 | Select this to enable timer for Aspeed ast2400/ast2500 devices. |
| 72 | This is a simple sys timer driver, it is compatible with lib/time.c, |
| 73 | but does not support any interrupts. Even though SoC has 8 hardware |
| 74 | counters, they are all treated as a single device by this driver. |
| 75 | This is mostly because they all share several registers which |
| 76 | makes it difficult to completely separate them. |
| 77 | |
| 78 | config ATCPIT100_TIMER |
| 79 | bool "ATCPIT100 timer support" |
| 80 | depends on TIMER |
| 81 | help |
| 82 | Select this to enable a ATCPIT100 timer which will be embedded |
| 83 | in AE3XX, AE250 boards. |
| 84 | |
Wenyou.Yang@microchip.com | 47edaea | 2017-08-15 17:40:26 +0800 | [diff] [blame] | 85 | config ATMEL_PIT_TIMER |
| 86 | bool "Atmel periodic interval timer support" |
| 87 | depends on TIMER |
| 88 | help |
| 89 | Select this to enable a periodic interval timer for Atmel devices, |
| 90 | it is designed to offer maximum accuracy and efficient management, |
| 91 | even for systems with long response time. |
| 92 | |
Eugen Hristev | 632422d | 2022-04-04 11:35:51 +0300 | [diff] [blame^] | 93 | config SPL_ATMEL_PIT_TIMER |
| 94 | bool "Atmel periodic interval timer support in SPL" |
| 95 | depends on SPL_TIMER |
| 96 | help |
| 97 | Select this to enable a periodic interval timer for Atmel devices, |
| 98 | it is designed to offer maximum accuracy and efficient management, |
| 99 | even for systems with long response time. |
| 100 | Select this to be available in SPL. |
| 101 | |
Clément Léger | 70fb1ae | 2022-03-31 10:55:06 +0200 | [diff] [blame] | 102 | config ATMEL_TCB_TIMER |
| 103 | bool "Atmel timer counter support" |
| 104 | depends on TIMER |
| 105 | depends on ARCH_AT91 |
| 106 | help |
| 107 | Select this to enable the use of the timer counter as a monotonic |
| 108 | counter. |
| 109 | |
Eugen Hristev | e135d2c | 2022-04-04 11:35:50 +0300 | [diff] [blame] | 110 | config SPL_ATMEL_TCB_TIMER |
| 111 | bool "Atmel timer counter support in SPL" |
| 112 | depends on SPL_TIMER |
| 113 | depends on ARCH_AT91 |
| 114 | help |
| 115 | Select this to enable the use of the timer counter as a monotonic |
| 116 | counter in SPL. |
| 117 | |
Michal Simek | 72c37d1 | 2018-04-17 13:40:46 +0200 | [diff] [blame] | 118 | config CADENCE_TTC_TIMER |
| 119 | bool "Cadence TTC (Triple Timer Counter)" |
| 120 | depends on TIMER |
| 121 | help |
| 122 | Enables support for the cadence ttc driver. This driver is present |
| 123 | on Xilinx Zynq and ZynqMP SoCs. |
| 124 | |
Marek Vasut | 66011a0 | 2018-08-18 15:58:32 +0200 | [diff] [blame] | 125 | config DESIGNWARE_APB_TIMER |
| 126 | bool "Designware APB Timer" |
| 127 | depends on TIMER |
| 128 | help |
| 129 | Enables support for the Designware APB Timer driver. This timer is |
| 130 | present on Altera SoCFPGA SoCs. |
| 131 | |
Bin Meng | 73fe411 | 2018-10-10 22:07:02 -0700 | [diff] [blame] | 132 | config MPC83XX_TIMER |
| 133 | bool "MPC83xx timer support" |
| 134 | depends on TIMER |
Thomas Chou | 9961a0b | 2015-10-30 15:35:52 +0800 | [diff] [blame] | 135 | help |
Bin Meng | 73fe411 | 2018-10-10 22:07:02 -0700 | [diff] [blame] | 136 | Select this to enable support for the timer found on |
| 137 | devices based on the MPC83xx family of SoCs. |
Bin Meng | 7030f27 | 2015-11-13 00:11:24 -0800 | [diff] [blame] | 138 | |
Marek Vasut | 4d0732b | 2019-05-04 17:30:58 +0200 | [diff] [blame] | 139 | config RENESAS_OSTM_TIMER |
| 140 | bool "Renesas RZ/A1 R7S72100 OSTM Timer" |
| 141 | depends on TIMER |
| 142 | help |
| 143 | Enables support for the Renesas OSTM Timer driver. |
| 144 | This timer is present on Renesas RZ/A1 R7S72100 SoCs. |
| 145 | |
Bin Meng | 5824bc6 | 2021-07-28 12:00:22 +0800 | [diff] [blame] | 146 | config X86_TSC_TIMER_FREQ |
| 147 | int "x86 TSC timer frequency in Hz" |
Bin Meng | 6ce3836 | 2018-10-13 20:52:10 -0700 | [diff] [blame] | 148 | depends on X86_TSC_TIMER |
Bin Meng | 5824bc6 | 2021-07-28 12:00:22 +0800 | [diff] [blame] | 149 | default 1000000000 |
Bin Meng | 6ce3836 | 2018-10-13 20:52:10 -0700 | [diff] [blame] | 150 | help |
Bin Meng | 5824bc6 | 2021-07-28 12:00:22 +0800 | [diff] [blame] | 151 | Sets the estimated CPU frequency in Hz when TSC is used as the |
Bin Meng | 6ce3836 | 2018-10-13 20:52:10 -0700 | [diff] [blame] | 152 | early timer and the frequency can neither be calibrated via some |
| 153 | hardware ways, nor got from device tree at the time when device |
| 154 | tree is not available yet. |
| 155 | |
Stephan Gerhold | 057b613 | 2020-01-04 18:45:15 +0100 | [diff] [blame] | 156 | config NOMADIK_MTU_TIMER |
| 157 | bool "Nomadik MTU Timer" |
| 158 | depends on TIMER |
| 159 | help |
| 160 | Enables support for the Nomadik Multi Timer Unit (MTU), |
| 161 | used in ST-Ericsson Ux500 SoCs. |
| 162 | The MTU provides 4 decrementing free-running timers. |
| 163 | At the moment, only the first timer is used by the driver. |
| 164 | |
Mugunthan V N | dadf313 | 2015-12-24 16:08:07 +0530 | [diff] [blame] | 165 | config OMAP_TIMER |
| 166 | bool "Omap timer support" |
| 167 | depends on TIMER |
| 168 | help |
| 169 | Select this to enable an timer for Omap devices. |
| 170 | |
Bin Meng | 60262cd0 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 171 | config RISCV_TIMER |
| 172 | bool "RISC-V timer support" |
| 173 | depends on TIMER && RISCV |
| 174 | help |
Sean Anderson | c33efaf | 2020-09-28 10:52:21 -0400 | [diff] [blame] | 175 | Select this to enable support for a generic RISC-V S-Mode timer |
| 176 | driver. |
Bin Meng | 60262cd0 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 177 | |
Bin Meng | 73fe411 | 2018-10-10 22:07:02 -0700 | [diff] [blame] | 178 | config ROCKCHIP_TIMER |
| 179 | bool "Rockchip timer support" |
maxims@google.com | 4697abe | 2017-01-18 13:44:55 -0800 | [diff] [blame] | 180 | depends on TIMER |
maxims@google.com | 4697abe | 2017-01-18 13:44:55 -0800 | [diff] [blame] | 181 | help |
Bin Meng | 73fe411 | 2018-10-10 22:07:02 -0700 | [diff] [blame] | 182 | Select this to enable support for the timer found on |
| 183 | Rockchip devices. |
| 184 | |
| 185 | config SANDBOX_TIMER |
| 186 | bool "Sandbox timer support" |
| 187 | depends on SANDBOX && TIMER |
| 188 | help |
| 189 | Select this to enable an emulated timer for sandbox. It gets |
| 190 | time from host os. |
maxims@google.com | 4697abe | 2017-01-18 13:44:55 -0800 | [diff] [blame] | 191 | |
Patrice Chotard | 347cb2e | 2017-02-21 13:37:05 +0100 | [diff] [blame] | 192 | config STI_TIMER |
| 193 | bool "STi timer support" |
| 194 | depends on TIMER |
| 195 | default y if ARCH_STI |
| 196 | help |
| 197 | Select this to enable a timer for STi devices. |
| 198 | |
Patrice Chotard | 5120a08 | 2018-02-07 10:44:45 +0100 | [diff] [blame] | 199 | config STM32_TIMER |
Bin Meng | 73fe411 | 2018-10-10 22:07:02 -0700 | [diff] [blame] | 200 | bool "STM32 timer support" |
Patrice Chotard | 5120a08 | 2018-02-07 10:44:45 +0100 | [diff] [blame] | 201 | depends on TIMER |
| 202 | help |
| 203 | Select this to enable support for the timer found on |
| 204 | STM32 devices. |
| 205 | |
Bin Meng | 73fe411 | 2018-10-10 22:07:02 -0700 | [diff] [blame] | 206 | config X86_TSC_TIMER |
| 207 | bool "x86 Time-Stamp Counter (TSC) timer support" |
| 208 | depends on TIMER && X86 |
Mario Six | 2c21749 | 2018-08-06 10:23:38 +0200 | [diff] [blame] | 209 | help |
Bin Meng | 73fe411 | 2018-10-10 22:07:02 -0700 | [diff] [blame] | 210 | Select this to enable Time-Stamp Counter (TSC) timer for x86. |
Mario Six | 2c21749 | 2018-08-06 10:23:38 +0200 | [diff] [blame] | 211 | |
Simon Glass | 77dd7c6 | 2019-12-06 21:41:49 -0700 | [diff] [blame] | 212 | config X86_TSC_READ_BASE |
| 213 | bool "Read the TSC timer base on start-up" |
| 214 | depends on X86_TSC_TIMER |
| 215 | help |
| 216 | On x86 platforms the TSC timer tick starts at the value 0 on reset. |
| 217 | This it makes no sense to read the timer on boot and use that as the |
| 218 | base, since we will miss some time taken to load U-Boot, etc. This |
| 219 | delay is controlled by the SoC and we cannot reduce it, but for |
| 220 | bootstage we want to record the time since reset as accurately as |
| 221 | possible. |
| 222 | |
| 223 | The only exception is when U-Boot is used as a secondary bootloader, |
| 224 | where this option should be enabled. |
| 225 | |
Simon Glass | 642e848 | 2019-12-06 21:41:50 -0700 | [diff] [blame] | 226 | config TPL_X86_TSC_TIMER_NATIVE |
| 227 | bool "x86 TSC timer uses native calibration" |
| 228 | depends on TPL && X86_TSC_TIMER |
| 229 | help |
| 230 | Selects native timer calibration for TPL and don't include the other |
| 231 | methods in the code. This helps to reduce code size in TPL and works |
| 232 | on fairly modern Intel chips. Code-size reductions is about 700 |
| 233 | bytes. |
| 234 | |
Ryder Lee | d3c3606 | 2018-11-15 10:07:56 +0800 | [diff] [blame] | 235 | config MTK_TIMER |
| 236 | bool "MediaTek timer support" |
| 237 | depends on TIMER |
| 238 | help |
| 239 | Select this to enable support for the timer found on |
| 240 | MediaTek devices. |
| 241 | |
Claudiu Beznea | ed1b726 | 2020-09-07 18:36:33 +0300 | [diff] [blame] | 242 | config MCHP_PIT64B_TIMER |
| 243 | bool "Microchip 64-bit periodic interval timer support" |
| 244 | depends on TIMER |
| 245 | help |
| 246 | Select this to enable support for Microchip 64-bit periodic |
| 247 | interval timer. |
| 248 | |
Giulio Benetti | f8c8573 | 2021-05-13 12:18:31 +0200 | [diff] [blame] | 249 | config IMX_GPT_TIMER |
| 250 | bool "NXP i.MX GPT timer support" |
| 251 | depends on TIMER |
| 252 | help |
| 253 | Select this to enable support for the timer found on |
| 254 | NXP i.MX devices. |
| 255 | |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 256 | endmenu |